JPH05102127A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPH05102127A JPH05102127A JP26164091A JP26164091A JPH05102127A JP H05102127 A JPH05102127 A JP H05102127A JP 26164091 A JP26164091 A JP 26164091A JP 26164091 A JP26164091 A JP 26164091A JP H05102127 A JPH05102127 A JP H05102127A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- film
- water
- semiconductor device
- repellent coating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Formation Of Insulating Films (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置のうち、特
に、半導体装置の保護被膜及びその製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a protective film for a semiconductor device and a method for manufacturing the same.
【０００２】[0002]
【従来の技術】半導体装置の素子エレメントを保護する
ため、素子を形成した後に保護絶縁膜による被覆が行わ
れている。ここで、保護絶縁膜は通常の絶縁膜と同じよ
うに、ＣＶＤ法、スパッタリング法、液相成長法等によ
り形成される。また、保護絶縁膜の他、絶縁膜には、所
望のマスクを形成した後にエッチングなどの処理を施
し、引き出し電極、配線のコンタクト孔を多々形成して
いる。2. Description of the Related Art In order to protect an element element of a semiconductor device, a protective insulating film is coated after the element is formed. Here, the protective insulating film is formed by a CVD method, a sputtering method, a liquid phase epitaxy method, or the like, similarly to a normal insulating film. In addition to the protective insulating film, the insulating film is subjected to a treatment such as etching after forming a desired mask to form a large number of contact holes for lead electrodes and wirings.
【０００３】[0003]
【発明が解決しようとする課題】上述のように堆積法に
よる保護絶縁膜では膜構造が粗であり、しばしば吸湿性
・透湿性を示す。このような保護絶縁膜では水分の浸透
を防げず、水分によって電極配線の酸化コロージョン反
応が進行し、配線をコロージョンが侵食したり、配線表
面に酸化物質が析出したりし、導通不良を引き起こす。
また、しばしば水分による半導体装置の電荷保持特性の
劣化を生じる。As described above, the protective insulating film formed by the deposition method has a rough film structure and often exhibits hygroscopicity and moisture permeability. Such a protective insulating film cannot prevent the penetration of moisture, and the moisture causes the oxidation corrosion reaction of the electrode wiring to proceed, the corrosion of the wiring corrodes, and an oxide substance is deposited on the wiring surface, which causes poor conduction.
In addition, moisture often causes deterioration of the charge retention characteristics of the semiconductor device.
【０００４】この他、電極を形成するために絶縁膜を開
口し、コンタクト孔を設けると、コンタクト孔側壁にや
はり吸湿性・透湿性を示す絶縁膜が露出し、水分の浸透
や電極形成後の酸化コロージョン反応等による不良を生
じる恐れがある。また、絶縁膜自体に吸湿性がない場合
にも、絶縁膜表面水分が吸着した場合には電極間の表面
リークの問題が生じる。In addition to this, when an insulating film is opened to form an electrode and a contact hole is provided, the insulating film also showing hygroscopicity / moisture permeability is exposed on the side wall of the contact hole, so that the penetration of moisture and the formation of an electrode after the formation of the electrode can be prevented. There is a possibility that defects may occur due to oxidation corrosion reaction or the like. Further, even when the insulating film itself has no hygroscopic property, when water on the surface of the insulating film is adsorbed, a problem of surface leakage between the electrodes occurs.
【０００５】これらの問題は、半導体装置の製造中に行
程の滞留などによる放置があった場合に、より顕著に現
れるため、厳しい工程管理が不可欠となる。そこで、絶
縁膜の表面を容易に耐湿処理・撥水性加工する方法が強
く望まれていた。These problems become more prominent when the semiconductor device is left as it is due to staying in the process during manufacturing, so that strict process control is indispensable. Therefore, there has been a strong demand for a method of easily subjecting the surface of the insulating film to moisture-proof treatment and water-repellent treatment.
【０００６】[0006]
【課題を解決するための手段】上述の問題点を解決する
ため本発明は、半導体基板と、前記半導体基板上に形成
された絶縁膜と、前記絶縁膜表面上に形成された撥水性
被膜とを有することを特徴とする半導体装置を提供す
る。同時に、半導体基板上に絶縁膜を形成する工程と、
前記絶縁膜表面上に撥水性被膜を形成する工程とを有す
ることを特徴とする半導体装置の製造方法をも提供す
る。ここで、前記絶縁膜が最外層の保護絶縁膜である場
合、前記縁膜表面が開口された孔側壁部に露出した絶縁
膜表面である場合であってもよい。また、前記絶縁膜表
面上に有機硅素化合物を塗布した後に、加熱乾燥して前
記撥水性被膜を形成しても良い。更に、エッチング処理
液または洗浄用水よりも比重の軽い有機硅素化合物と前
記エッチング処理液または洗浄用水とを一槽に貯め、前
記絶縁膜をエッチング処理した後で、前記半導体基板を
前記エッチング処理液または洗浄用水から引き上げると
きに前記硅素化合物層を通過させることによって前記撥
水性被膜を形成しても良い。In order to solve the above-mentioned problems, the present invention provides a semiconductor substrate, an insulating film formed on the semiconductor substrate, and a water-repellent coating formed on the surface of the insulating film. There is provided a semiconductor device having: At the same time, a step of forming an insulating film on the semiconductor substrate,
And a step of forming a water-repellent coating on the surface of the insulating film. Here, when the insulating film is the outermost protective insulating film, the insulating film surface may be the insulating film surface exposed on the side wall portion of the opening. Further, the water repellent coating may be formed by applying an organic silicon compound on the surface of the insulating film and then heating and drying. Further, an organic silicon compound having a specific gravity lower than that of the etching treatment liquid or cleaning water and the etching treatment liquid or cleaning water are stored in one tank, and after the insulating film is etched, the semiconductor substrate is treated with the etching treatment liquid or The water-repellent coating may be formed by passing through the silicon compound layer when the water-repellent coating is pulled up from the cleaning water.
【０００７】前記撥水性被膜は有機硅素化合物であり、
更に、前記有機硅素化合物は直鎖状ポリオルガノシロキ
サン、または環状ポリオルガノシロキサンから選ばれた
少なくとも１種の低分子量ポリオルガノシロキサンであ
っても良い。The water-repellent coating is an organic silicon compound,
Further, the organosilicon compound may be at least one low molecular weight polyorganosiloxane selected from linear polyorganosiloxane and cyclic polyorganosiloxane.
【０００８】[0008]
【作用】絶縁膜表面上に撥水性の被膜を形成しておくこ
とにより、絶縁膜内への水分の浸透を強力に防止し、電
極配線のコロージョン反応を抑え、水分による電荷保持
特性の劣化を防ぎ、素子の耐湿性を向上させる。また、
金属等の汚染も防止することができる。[Function] By forming a water-repellent coating on the surface of the insulating film, the penetration of water into the insulating film is strongly prevented, the corrosion reaction of the electrode wiring is suppressed, and the deterioration of the charge retention characteristics due to water is prevented. Prevents and improves the moisture resistance of the device. Also,
It is also possible to prevent contamination of metals and the like.
【０００９】更に、吸湿・透湿のみならず、絶縁膜表面
の水分の吸着を防ぐとともに、有機硅素化合物が良好な
絶縁物質であることから、絶縁膜上での電極間の表面リ
ークをも抑える。Furthermore, not only moisture absorption and moisture permeation but also the adsorption of moisture on the surface of the insulating film is prevented, and the surface leakage between the electrodes on the insulating film is suppressed because the organic silicon compound is a good insulating material. ..
【００１０】また、絶縁膜に電極等のため、開口部を設
けた時にも、孔側壁部に露出した絶縁膜表面上に撥水性
被膜を形成しておくことにより、絶縁膜への吸湿・透湿
を防止することができ、素子の耐久性を向上できる。Further, since the insulating film is an electrode or the like, even when an opening is provided, a water-repellent film is formed on the surface of the insulating film exposed on the side wall of the hole, so that the insulating film absorbs moisture and permeates the insulating film. Moisture can be prevented, and the durability of the device can be improved.
【００１１】[0011]
【実施例】（実施例１）以下、本発明の第１の実施例を
詳細に説明する。本実施例は、本発明をＥＰＲＯＭに用
いるものである。(Embodiment 1) A first embodiment of the present invention will be described in detail below. This embodiment uses the present invention for an EPROM.
【００１２】本発明に用いる有機硅素化合物として、例
えば、ポリオルガノシロキサン（以下シリコーンと称す
る）の中のポリジオルガノシロキサンを図４、図５に示
す。シリコーンはその性状により、オイル・ゴム・レジ
ンの３基本形に分類できるが、その中で図４はシリコー
ンオイルの持つ鎖状分子構造を示したもので、ｌは０以
上の整数を示し、図５は環状分子構造を示したもので、
ｍは３以上の整数を示す。ここで、Ｒは同一または相異
なる置換または非置換の１価の炭化水素基で、主にメチ
ル基（ＣＨ3 ）、フェニル基（Ｃ6 Ｈ5 ）、長鎖アルキ
ル基（Ｃn Ｈ2n+1）、トリフルオロプロピル基（ＣＦ3
ＣＨ2 ＣＨ2 ）などである。As the organic silicon compound used in the present invention, for example, polydiorganosiloxane in polyorganosiloxane (hereinafter referred to as silicone) is shown in FIGS. Silicone can be classified into three basic types of oil, rubber, and resin according to its properties. Among them, FIG. 4 shows a chain molecular structure of silicone oil, and l is an integer of 0 or more, and FIG. Is a cyclic molecular structure,
m represents an integer of 3 or more. Here, R is a substituted or unsubstituted monovalent hydrocarbon group which is the same or different and is mainly a methyl group (CH 3 ), a phenyl group (C 6 H 5 ), a long chain alkyl group (C n H 2n + 1 ), trifluoropropyl group (CF 3
CH 2 CH 2 ) and the like.
【００１３】本発明をＥＰＲＯＭ素子に用いる場合につ
いて図１から図３を参照しながら説明する。図１はＥＰ
ＲＯＭの一部を示す平面図、図２は図１中のＡＡ’に沿
う断面の一部を示す断面図、図３は図１中のＢＢ’に沿
う断面を示す断面図である。A case where the present invention is applied to an EPROM device will be described with reference to FIGS. Figure 1 EP
2 is a plan view showing a part of the ROM, FIG. 2 is a cross-sectional view showing a part of a cross section taken along AA ′ in FIG. 1, and FIG. 3 is a cross-sectional view showing a cross section taken along BB ′ in FIG.
【００１４】ＥＰＲＯＭは従来の方法を用いて形成す
る。即ち、まず、改良ＬＯＣＯＳ等の方法で、半導体基
板１表面にメモリセルを分離するための素子分離領域９
を膜厚800nm 程度形成する。この後、例えば、塩酸を用
いて素子予定領域に30nm程度の第１ゲート絶縁膜３を形
成し、イオン打ち込み法等により、例えば、ボロンを濃
度１×1023cm-3程度導入し、チャネル領域８を形成す
る。次に、例えば、ＣＶＤ法により、浮遊ゲート４を形
成する第１のポリシリコン層を第１ゲート絶縁膜３上の
全面に膜厚400nm 程度堆積させ、不純物を濃度１×1020
〜1021cm-3程度拡散させる。また、素子分離領域９上に
ドライエッチング法などを用いて第１のポリシリコン層
と第１ゲート絶縁膜３を除去し、浮遊ゲート７を分離す
るためのスリット領域１０を形成しておく。この後、90
0℃以上の温度で酸化処理を施し、第１のポリシリコン
層上に第２ゲート絶縁膜５を膜厚40nm程度形成する。続
いて、ＣＶＤ法等を用いて、第２ゲート絶縁膜５上に膜
厚400nm 程度の第２のポリシリコン層を堆積させ、第２
のポリシリコン層中に不純物を濃度１×1020〜1021cm-3
程度導入する。The EPROM is formed using conventional methods. That is, first, an element isolation region 9 for isolating a memory cell is formed on the surface of the semiconductor substrate 1 by a method such as improved LOCOS.
To a thickness of about 800 nm. After that, for example, hydrochloric acid is used to form the first gate insulating film 3 having a thickness of about 30 nm in the device planned region, and, for example, boron is introduced at a concentration of about 1 × 10 23 cm −3 by an ion implantation method or the like to form a channel region. 8 is formed. Next, for example, by CVD, a first polysilicon layer for forming the floating gate 4 is deposited on the entire surface of the first gate insulating film 3 to a film thickness of about 400 nm, and the impurity concentration is set to 1 × 10 20.
Disperse about 10 21 cm -3 . Further, the first polysilicon layer and the first gate insulating film 3 are removed on the element isolation region 9 by using a dry etching method or the like to form a slit region 10 for separating the floating gate 7. After this, 90
Oxidation is performed at a temperature of 0 ° C. or higher to form the second gate insulating film 5 on the first polysilicon layer with a thickness of about 40 nm. Then, a second polysilicon layer having a thickness of about 400 nm is deposited on the second gate insulating film 5 by using the CVD method or the like,
Concentration of impurities in the polysilicon layer of 1 × 10 20 to 10 21 cm -3
Introduce a degree.
【００１５】次に、まずドライエッチング法により第２
のポリシリコン層をエッチングし、チャネル領域８上に
延びるコントロールゲート６と、スリット領域１０を形
成する。次に、セルフアライン技術を用いて、第２のゲ
ート絶縁膜５と第１のポリシリコン層をエッチングし、
コントロールゲート６の下に浮遊ゲート４を形成する。
また、以上の工程の途中に周辺の素子を形成する工程を
含ませても良い。Next, first, a second dry etching method is performed.
The polysilicon layer is etched to form a control gate 6 extending above the channel region 8 and a slit region 10. Next, the second gate insulating film 5 and the first polysilicon layer are etched using the self-alignment technique,
The floating gate 4 is formed below the control gate 6.
In addition, a step of forming peripheral elements may be included in the middle of the above steps.
【００１６】次に、コントロールゲート６、浮遊ゲート
４をマスクに１×1015cm-2程度のヒ素イオン等をセルフ
アラインで打ち込み、コントロールゲート６を挟む半導
体基板１上にソース領域２ａ、ドレイン領域２ｂを形成
する。最後に、ＣＶＤ法等を用いて保護絶縁膜７を全面
に堆積させ、ＥＰＲＯＭを形成する。Next, using the control gate 6 and the floating gate 4 as a mask, arsenic ions of about 1 × 10 15 cm -2 are implanted by self-alignment to form a source region 2a and a drain region on the semiconductor substrate 1 with the control gate 6 interposed therebetween. 2b is formed. Finally, the protective insulating film 7 is deposited on the entire surface by using the CVD method or the like to form an EPROM.
【００１７】保護絶縁膜７を形成後に、シリコーンオイ
ル槽に浸積し、加熱乾燥を行い、保護絶縁膜７上にシリ
コーン等による非常に薄い撥水性被膜１１を形成する。
加熱乾燥を施すと、いち早く工程を終了することがで
き、作業を効率化できる。ここでは、シリコーンオイル
槽に浸積することによって保護絶縁膜７上にシリコーン
を塗布したが、この他、シリコーンオイルを噴霧塗布し
ても良い。また、塗布後加熱により乾燥させたが、この
他、風乾、自然乾燥によっても良く、更に、乾燥させず
に濡れたままの状態でも効果に変わりはない。After forming the protective insulating film 7, the protective insulating film 7 is immersed in a silicone oil bath and dried by heating to form a very thin water-repellent coating 11 made of silicone or the like on the protective insulating film 7.
By heating and drying, the process can be completed quickly, and the work efficiency can be improved. Here, the silicone is applied onto the protective insulating film 7 by immersing it in a silicone oil tank, but in addition to this, the silicone oil may be applied by spraying. Further, although it is dried by heating after coating, it may be dried by air or by natural drying, and the effect is not changed even when it remains wet without being dried.
【００１８】この他、シリコーン被覆の前に１００℃以
上の熱処理を行い、一度放置などにより吸湿した絶縁膜
でも熱処理により水分焼き出し後に撥水性被膜１１を形
成すると、含水率の少ない状態での保管が可能になる。In addition, if the water-repellent coating 11 is formed after the moisture is baked out by heat treatment even on an insulating film that has absorbed moisture by leaving it for a while, it is stored in a state of low water content. Will be possible.
【００１９】図６は、吸湿・透湿の程度を確認するため
に、ＥＰＲＯＭの電荷保持率を計測した結果である。絶
縁膜に水分が含まれると、この水分が絶縁性を損なう原
因となって、電荷保持率を引き下げることになる。ここ
では、保護絶縁膜にＰＳＧ膜を使用し、湿度１００％雰
囲気中の室温で２４時間放置し、３００℃の高温放置し
たときのもので、６１は撥水性被膜を形成しない従来
例、６２は本発明を用いた場合の結果である。従来例６
１では放置にともない電荷保持特性が急激に劣化してゆ
くのに対し、本発明を用いた場合７２ではほぼ１００％
の電荷保持率が保たれ、耐湿性に優れていることを確認
することができた。FIG. 6 shows the result of measuring the charge holding ratio of the EPROM in order to confirm the degree of moisture absorption / moisture transmission. When the insulating film contains water, this water causes the deterioration of the insulating property and lowers the charge retention rate. Here, a PSG film is used as a protective insulating film, left for 24 hours at room temperature in an atmosphere of 100% humidity, and left at a high temperature of 300 ° C., 61 is a conventional example in which a water-repellent film is not formed, and 62 is It is a result when using this invention. Conventional example 6
In No. 1, the charge retention property deteriorates sharply with leaving, whereas in the case of using the present invention, it is almost 100% in 72.
It was confirmed that the charge retention rate was maintained and the moisture resistance was excellent.
【００２０】また、図７は、テトラエチルオルトシリケ
ートを用いてプラズマＣＶＤ法により半導体基板上に成
膜したシリコン酸化膜を４５０℃で熱処理し、水分の焼
き出しを行った後、撥水性被膜を形成し、大気中に１６
８時間放置したときの絶縁膜中の含水量の測定結果であ
る。横軸は真空加熱時の温度、縦軸は放出ガス中の水の
分圧を示し、７１は撥水性被膜を持たない従来例で、７
２は本発明を用いた場合の結果である。図からも明らか
なように、従来例７１では１００℃〜２００℃に水分放
出のピークを持ち、その他の温度でも水分放出量は極め
て多いが、本発明を用いた場合７２はピークはなく、水
分放出がほとんど検出されず、撥水性被膜が酸化膜中へ
の吸湿・透湿を強力に阻止していることがわかる。ここ
では、ＣＶＤ法により酸化膜を堆積したが、この他に、
スパッタリング法、液相成長法、塗布法等があるが、こ
れらの堆積法によって撥水性被膜を形成した絶縁膜でも
同様の結果がえられた。また、上述のようにして形成し
た撥水性被膜は電気絶縁性に優れており、絶縁膜上の電
極間の表面リークも抑制することができた。Further, FIG. 7 shows that a silicon oxide film formed on a semiconductor substrate by a plasma CVD method using tetraethyl orthosilicate is heat-treated at 450 ° C. to bake out water, and then a water-repellent film is formed. 16 in the atmosphere
It is a measurement result of the water content in the insulating film when left for 8 hours. The horizontal axis represents the temperature during vacuum heating, the vertical axis represents the partial pressure of water in the released gas, and 71 represents the conventional example having no water-repellent coating.
2 is the result when the present invention is used. As is clear from the figure, the conventional example 71 has a water release peak at 100 ° C. to 200 ° C., and the amount of water release is extremely large at other temperatures. Almost no release was detected, indicating that the water-repellent coating strongly blocks moisture absorption and moisture permeation into the oxide film. Here, an oxide film is deposited by the CVD method, but in addition to this,
Although there are sputtering method, liquid phase growth method, coating method and the like, similar results were obtained with an insulating film having a water repellent film formed by these deposition methods. In addition, the water-repellent coating formed as described above was excellent in electrical insulation, and the surface leak between the electrodes on the insulating film could be suppressed.
【００２１】特に、保護絶縁膜上に撥水性被膜を形成し
た場合は、この後のウエハー裏面研削工程、ウエハー切
断工程、検査工程、封止工程までの間の吸湿・透湿防止
に有効である。または、上記の工程の前工程として、本
発明の撥水性被膜形成工程を施すことにより、各工程間
での吸湿・透湿を防止することができ、耐久性を向上さ
せることができる。In particular, when a water-repellent coating is formed on the protective insulating film, it is effective in preventing moisture absorption and moisture permeation during the subsequent wafer back surface grinding step, wafer cutting step, inspection step and sealing step. .. Alternatively, by performing the water-repellent coating forming step of the present invention as a step prior to the above-mentioned steps, it is possible to prevent moisture absorption / moisture transmission between the steps and improve durability.
【００２２】以上では、ＥＰＲＯＭについての例を説明
してきたが、その他、ＭＯＳ型ＦＥＴなど、さまざまな
半導体素子の絶縁膜上の被膜に用いることができる。ま
た、封止工程の前工程として本発明を用いることにより
半導体素子の耐久性の向上、特性変化の阻止が可能であ
る。 （実施例２）以下、本発明の第２の実施例を詳細に説明
する。本実施例は、本発明をコンタクト孔等の開口工程
に用いるものである。Although the example of the EPROM has been described above, it can be used as a film on the insulating film of various semiconductor elements such as a MOS type FET. Further, by using the present invention as the pre-process of the sealing process, it is possible to improve the durability of the semiconductor element and prevent the characteristic change. (Embodiment 2) Hereinafter, a second embodiment of the present invention will be described in detail. The present embodiment uses the present invention in the step of opening contact holes and the like.
【００２３】従来の方法により、図８のような、ＭＯＳ
型ＦＥＴを形成する。即ち、半導体基板５１上に通常の
ＬＯＣＯＳ工程により素子分離領域５３を形成し、素子
予定領域にＣＶＤ法等を用いて膜厚30nm程度のゲート絶
縁膜５４を形成する。次に、ポリシリコン等を400nm 程
度堆積し、所定のゲートパターンをマスクとしてエッチ
ングを行い、ゲート電極５５を形成する。この後、ゲー
ト電極５５をマスクとして、例えばヒ素を２×1015cm-2
程度イオン注入し、ソース領域５２ａ、ドレイン領域５
２ｂを形成し、200nm 程度の絶縁膜５６を堆積させる。According to the conventional method, as shown in FIG.
Form a FET. That is, the element isolation region 53 is formed on the semiconductor substrate 51 by a normal LOCOS process, and the gate insulating film 54 having a film thickness of about 30 nm is formed in the element planned region by the CVD method or the like. Next, polysilicon or the like is deposited to a thickness of about 400 nm, and etching is performed using a predetermined gate pattern as a mask to form a gate electrode 55. Then, using the gate electrode 55 as a mask, for example, arsenic is added at 2 × 10 15 cm -2.
Source region 52a, drain region 5
2b is formed and an insulating film 56 of about 200 nm is deposited.
【００２４】次に、ソース領域５２ａ、ドレイン領域５
２ｂ上のゲート絶縁膜５４、絶縁膜５６をエッチングし
てコンタクト孔５７を形成する。ここで、絶縁膜５６に
吸湿性・透湿性があるとコンタクト孔５７側壁部が水分
の浸透や金属等の汚染を受け易く、後に素子特性の劣化
や電極材料にコロージョンが生じる恐れがある。Next, the source region 52a and the drain region 5
A contact hole 57 is formed by etching the gate insulating film 54 and the insulating film 56 on 2b. Here, if the insulating film 56 has hygroscopicity / moisture permeability, the side wall of the contact hole 57 is likely to be permeated with water or contaminated with metal or the like, which may result in deterioration of element characteristics or corrosion of the electrode material.
【００２５】そこで、エッチング溶液等の絶縁膜加工溶
液とシリコーンオイルを一つの槽に入れ、シリコーンオ
イルの比重が１よりも軽いことから、処理液とシリコー
ンオイルを２層とした処理槽にコンタクト孔５７を除く
部分をマスクした半導体基板５１を浸し、エッチング処
理を行い、コンタクト孔５７を形成後、半導体基板５１
引き上げの際にシリコーンオイル層を通過させて、熱処
理を施すことにより、コンタクト孔５７側壁部に薄い撥
水性膜５９を形成することができる。または、エッチン
グ処理後、水洗用の水槽を水とシリコーンの２層とし、
水洗後にシリコーン層を通し、シリコーンからなる撥水
性被膜５９を形成しても良い。もちろん、エッチング処
理後、引き続きシリコーンオイルを噴霧塗布するなどの
方法によって撥水性膜を形成することもできる。また、
熱処理をしてシリコーンオイルを乾燥させたが、風乾、
自然乾燥でもよい。Therefore, an insulating film processing solution such as an etching solution and silicone oil are put in one tank, and since the specific gravity of the silicone oil is less than 1, a contact hole is formed in the processing tank having two layers of the processing solution and the silicone oil. The semiconductor substrate 51 masked at a portion other than 57 is dipped and etched to form a contact hole 57, and then the semiconductor substrate 51 is formed.
A thin water-repellent film 59 can be formed on the side wall of the contact hole 57 by passing through the silicone oil layer and performing heat treatment during pulling up. Alternatively, after the etching treatment, the water tank for washing is made of two layers of water and silicone,
After washing with water, the silicone layer may be passed through to form the water-repellent coating 59 made of silicone. Of course, after the etching treatment, the water-repellent film can be formed by a method such as spray coating silicone oil. Also,
It was heat treated to dry the silicone oil, but it was air dried,
Natural drying is also acceptable.
【００２６】次に、従来からのように、電極材との接面
となるソース領域５２ａ、ドレイン領域ｂ表面上の撥水
性被膜５９をアルゴンスパッタリング法等で取り除きい
た後、電極となるＡｌなどの金属をスパッタリング法等
で堆積させ、電極５８を形成し、ＭＯＳ型ＦＥＴを完成
する。撥水性被膜５９は薄く、容易に取り除くことが可
能である。Next, as in the prior art, after removing the water-repellent coating 59 on the surfaces of the source region 52a and the drain region b, which are the contact surfaces with the electrode material, by an argon sputtering method or the like, Al or the like which becomes the electrode is removed. A metal is deposited by a sputtering method or the like to form an electrode 58, and the MOS type FET is completed. The water-repellent coating 59 is thin and can be easily removed.
【００２７】このようにしてコンタクト孔側壁部に薄い
撥水性膜５９を形成しておくと、絶縁膜中に水分が浸透
することがなく、電荷保持特性等の素子特性の劣化を阻
止できる。また、電極材料にコロージョンのような侵食
や析出を防ぐことができる。また、撥水性被膜５９によ
って金属等の汚染も防ぐことが可能である。By forming the thin water-repellent film 59 on the side wall of the contact hole in this manner, moisture does not penetrate into the insulating film, and deterioration of device characteristics such as charge retention characteristics can be prevented. Further, it is possible to prevent erosion and precipitation such as corrosion on the electrode material. In addition, the water-repellent coating 59 can prevent contamination of metals and the like.
【００２８】以上では、ＭＯＳ型ＦＥＴに本発明を用い
た場合について説明してきたが、この他、コンタクト孔
や電極パッドの開口工程を要する場合について広く応用
が可能である。Although the case where the present invention is used for the MOS type FET has been described above, the present invention can be widely applied to cases where the step of opening contact holes and electrode pads is required.
【００２９】[0029]
【発明の効果】以上の説明からも明らかなように、絶縁
膜表面に撥水性被膜を形成しておくことにより、撥水性
被膜が水分をはじき、吸湿・透湿を防止することができ
る。これにより、電荷保持特性等、素子特性の変化、電
極配線等のコロージョン反応を良好に抑えることができ
る。また、撥水性の被膜は金属等の汚染も有効に抑える
ことができる。As is apparent from the above description, by forming a water-repellent coating on the surface of the insulating film, the water-repellent coating repels water and prevents moisture absorption and moisture permeation. This makes it possible to favorably suppress changes in device characteristics such as charge retention characteristics and corrosion reactions such as electrode wiring. Further, the water-repellent coating can effectively suppress the contamination of metals and the like.
【００３０】さらに、吸湿性・透湿性のない絶縁膜にお
いても、絶縁膜表面の水分の吸着を防ぐと同時に、撥水
性被膜に絶縁性があることから電極間の表面リークを有
効に抑える。Further, even in the case of an insulating film having no hygroscopicity or moisture permeability, the adsorption of water on the surface of the insulating film is prevented, and at the same time, the surface leakage between the electrodes is effectively suppressed because the water-repellent film has an insulating property.
【００３１】この他、絶縁膜に電極等のための開口部を
設ける場合にも、孔側壁部に露出した絶縁膜表面上に撥
水性被膜を形成しておくことにより、工程途中での絶縁
膜への吸湿・透湿を防止することができ、素子特性の変
化を防ぎ、素子の耐性を向上させることができる。ま
た、工程間で遅滞が生じたとしても、絶縁膜表面上に撥
水被膜を形成してあるので吸湿・透湿等を防止すること
ができる。In addition, when an opening for an electrode or the like is provided in the insulating film, a water-repellent coating is formed on the surface of the insulating film exposed on the side wall of the hole, so that the insulating film is formed during the process. It is possible to prevent moisture absorption and moisture permeation to the element, prevent changes in element characteristics, and improve element resistance. Further, even if there is a delay between the steps, since the water-repellent coating is formed on the surface of the insulating film, it is possible to prevent moisture absorption and moisture permeation.
【図１】本発明の第１の実施例を示すＥＰＲＯＭの平面
図の一部である。FIG. 1 is a part of a plan view of an EPROM showing a first embodiment of the present invention.
【図２】図１中のＡＡ’に沿う断面の一部を示す断面図
である。FIG. 2 is a cross-sectional view showing a part of a cross section taken along AA ′ in FIG.
【図３】図１中のＢＢ’に沿う断面の一部を示す断面図
である。FIG. 3 is a cross-sectional view showing a part of a cross section taken along BB ′ in FIG.
【図４】直鎖状ポリジオルガノシロキサンの一般式であ
る。ここに、Ｒは同一または相異なる置換または非置換
の１価の炭化水素基で、主にメチル基（ＣＨ3 ）、フェ
ニル基（Ｃ6 Ｈ5 ）、長鎖アルキル基（Ｃn Ｈ2n+1）、
トリフルオロプロピル基（ＣＦ3 ＣＨ2 ＣＨ2 ）等であ
る。また、ｌは０以上の整数を示す。FIG. 4 is a general formula for linear polydiorganosiloxanes. Here, R is the same or different substituted or unsubstituted monovalent hydrocarbon group, and is mainly a methyl group (CH 3 ), a phenyl group (C 6 H 5 ), a long-chain alkyl group (C n H 2n + 1 ),
And a trifluoropropyl group (CF 3 CH 2 CH 2 ). In addition, l represents an integer of 0 or more.
【図５】環状ポリジオルガノシロキサンの一般式であ
る。ここに、Ｒは同一または相異なる置換または非置換
の１価の炭化水素基で、主にメチル基（ＣＨ3）、フェ
ニル基（Ｃ6 Ｈ5 ）、長鎖アルキル基（Ｃn Ｈ2n+1）、
トリフルオロプロピル基（ＣＦ3 ＣＨ2 ＣＨ2 ）等であ
る。また、ｍは３以上の整数を示す。FIG. 5 is a general formula for cyclic polydiorganosiloxanes. Here, R is the same or different substituted or unsubstituted monovalent hydrocarbon group, and is mainly a methyl group (CH 3 ), a phenyl group (C 6 H 5 ), a long-chain alkyl group (C n H 2n + 1 ),
And a trifluoropropyl group (CF 3 CH 2 CH 2 ). Further, m represents an integer of 3 or more.
【図６】本発明の第１の実施例による３００℃の高温放
置時の電荷保持率を示す実験結果である。FIG. 6 is an experimental result showing the charge retention rate when left at a high temperature of 300 ° C. according to the first embodiment of the present invention.
【図７】酸化膜形成後、大気中に１６８時間放置し、真
空加熱したときの放出ガス中の水の分圧を示す実験結果
である。FIG. 7 is an experimental result showing the partial pressure of water in the released gas when the film is left in the air for 168 hours and vacuum-heated after the oxide film is formed.
【図８】本発明の第２の実施例を示す断面図である。FIG. 8 is a sectional view showing a second embodiment of the present invention.
１、５１ 半導体基板 ２ａ、５２ａ ソース領域 ２ｂ、５２ｂ ドレイン領域 ３、５３ 第１ゲート絶縁膜 ４ 浮遊ゲート ５ 第２のゲート絶縁膜 ６ コントロールゲート ７ 保護絶縁膜 ８ チャネル領域 ９ 素子分離領域 １０ スリット領域 １１、５９ 撥水性被膜 ５４ ゲート絶縁膜 ５５ ゲート電極 ５６ 絶縁膜 ５７ コンタクト孔 ５８ 電極 ６１ 絶縁膜中の含水量を従来例について計測した結果
である。 ６２ 絶縁膜中の含水量を本発明を用いた場合について
計測した結果である。 ７１ 従来のＥＰＲＯＭの電荷保持率を計測した結果で
ある。 ７２ 本発明の第１の実施例のＥＰＲＯＭの電荷保持率
を計測した結果である。1, 51 Semiconductor substrate 2a, 52a Source region 2b, 52b Drain region 3, 53 First gate insulating film 4 Floating gate 5 Second gate insulating film 6 Control gate 7 Protective insulating film 8 Channel region 9 Element isolation region 10 Slit region 11, 59 Water-repellent coating 54 Gate insulating film 55 Gate electrode 56 Insulating film 57 Contact hole 58 Electrode 61 Results of measuring the water content in the insulating film for a conventional example. 62 is the result of measuring the water content in the insulating film in the case of using the present invention. 71 This is the result of measuring the charge retention rate of the conventional EPROM. 72 is the result of measuring the charge retention rate of the EPROM of the first example of the present invention.
Claims (8)
とを特徴とする半導体装置。1. A semiconductor device comprising a semiconductor substrate, an insulating film formed on the semiconductor substrate, and a water-repellent coating formed on the surface of the insulating film.
ることを特徴とする半導体装置の製造方法。2. A method of manufacturing a semiconductor device, comprising: a step of forming an insulating film on a semiconductor substrate; and a step of forming a water repellent coating film on the surface of the insulating film.
とを特徴とする特許請求の範囲請求項１乃至請求項２記
載の半導体装置またはその製造方法。3. The semiconductor device according to claim 1, wherein the insulating film is an outermost protective insulating film, or a method for manufacturing the same.
出した絶縁膜表面であることを特徴とする特許請求の範
囲請求項１乃至請求項２記載の半導体装置またはその製
造方法。4. The semiconductor device according to claim 1 or 2, wherein the surface of the insulating film is the surface of the insulating film exposed at the side wall of the opened hole.
した後に、加熱乾燥して前記撥水性被膜を形成すること
を特徴とする特許請求の範囲請求項２記載の半導体装置
の製造方法。5. The method for manufacturing a semiconductor device according to claim 2, wherein the water repellent film is formed by applying an organic silicon compound on the surface of the insulating film and then heating and drying.
重の軽い有機硅素化合物と前記エッチング処理液または
洗浄用水とを一槽に貯め、前記絶縁膜をエッチング処理
した後で、前記半導体基板を前記エッチング処理液また
は洗浄用水から引き上げるときに前記硅素化合物層を通
過させることによって前記撥水性被膜を形成することを
特徴とする特許請求の範囲請求項２記載の半導体装置の
製造方法。6. An organic silicon compound having a specific gravity lower than that of an etching treatment liquid or cleaning water and the etching treatment liquid or cleaning water are stored in one tank, and after the insulating film is subjected to an etching treatment, the semiconductor substrate is subjected to the etching treatment. 3. The method for manufacturing a semiconductor device according to claim 2, wherein the water-repellent coating is formed by passing through the silicon compound layer when the water repellent film is pulled up from the treatment liquid or the cleaning water.
とを特徴とする特許請求の範囲請求項１乃至請求項４記
載の半導体装置またはその製造方法。7. A semiconductor device or a method for manufacturing the same according to claim 1, wherein the water-repellent coating is an organic silicon compound.
シロキサン、または環状ポリオルガノシロキサンから選
ばれた少なくとも１種のポリオルガノシロキサンである
ことを特徴とする特許請求の範囲請求項７記載の半導体
装置またはその製造方法。8. The semiconductor according to claim 7, wherein the organosilicon compound is at least one polyorganosiloxane selected from linear polyorganosiloxanes and cyclic polyorganosiloxanes. Device or manufacturing method thereof.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26164091A JP3150378B2 (en) | 1991-10-09 | 1991-10-09 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26164091A JP3150378B2 (en) | 1991-10-09 | 1991-10-09 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05102127A true JPH05102127A (en) | 1993-04-23 |
| JP3150378B2 JP3150378B2 (en) | 2001-03-26 |
Family
ID=17364708
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26164091A Expired - Fee Related JP3150378B2 (en) | 1991-10-09 | 1991-10-09 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3150378B2 (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6176098B1 (en) | 1997-06-23 | 2001-01-23 | Mitsubishi Denki Kabushiki Kaisha | Water vaporization type cooler for heat-generating element |
| US6959490B2 (en) | 2002-08-12 | 2005-11-01 | Seiko Epson Corporation | Method of manufacturing silicon device, method of manufacturing liquid jet head and liquid jet head |
| JP2006111739A (en) * | 2004-10-15 | 2006-04-27 | Jsr Corp | Composition for surface-hydrophobizing use, surface-hydrophobizing method, semiconductor device and method for producing the same |
| WO2007029971A1 (en) * | 2005-09-07 | 2007-03-15 | Iferro Co., Ltd. | Method of forming organic layer on semiconductor substrate |
| WO2007032621A1 (en) * | 2005-09-12 | 2007-03-22 | Iferro Co., Ltd. | Ferroelectric memory device and method of manufacturing the same |
| JP2012182256A (en) * | 2011-02-28 | 2012-09-20 | Nichia Chem Ind Ltd | Light-emitting device |
-
1991
- 1991-10-09 JP JP26164091A patent/JP3150378B2/en not_active Expired - Fee Related
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6176098B1 (en) | 1997-06-23 | 2001-01-23 | Mitsubishi Denki Kabushiki Kaisha | Water vaporization type cooler for heat-generating element |
| US6959490B2 (en) | 2002-08-12 | 2005-11-01 | Seiko Epson Corporation | Method of manufacturing silicon device, method of manufacturing liquid jet head and liquid jet head |
| JP2006111739A (en) * | 2004-10-15 | 2006-04-27 | Jsr Corp | Composition for surface-hydrophobizing use, surface-hydrophobizing method, semiconductor device and method for producing the same |
| WO2007029971A1 (en) * | 2005-09-07 | 2007-03-15 | Iferro Co., Ltd. | Method of forming organic layer on semiconductor substrate |
| WO2007032621A1 (en) * | 2005-09-12 | 2007-03-22 | Iferro Co., Ltd. | Ferroelectric memory device and method of manufacturing the same |
| US8120082B2 (en) | 2005-09-12 | 2012-02-21 | University of Seoul, Foundation of Industry-Academic Cooperation | Ferroelectric memory device and method for manufacturing the same |
| JP2012182256A (en) * | 2011-02-28 | 2012-09-20 | Nichia Chem Ind Ltd | Light-emitting device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3150378B2 (en) | 2001-03-26 |
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