KR0140808B1 - Thin film transistor - Google Patents
Thin film transistorInfo
- Publication number
- KR0140808B1 KR0140808B1 KR1019940034510A KR19940034510A KR0140808B1 KR 0140808 B1 KR0140808 B1 KR 0140808B1 KR 1019940034510 A KR1019940034510 A KR 1019940034510A KR 19940034510 A KR19940034510 A KR 19940034510A KR 0140808 B1 KR0140808 B1 KR 0140808B1
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- Prior art keywords
- film
- bpsg
- channel
- oxide film
- thin film
- Prior art date
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- 239000010409 thin film Substances 0.000 title claims abstract description 16
- 239000010408 film Substances 0.000 claims abstract description 86
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 29
- 229920005591 polysilicon Polymers 0.000 claims abstract description 29
- 239000005380 borophosphosilicate glass Substances 0.000 claims abstract description 23
- 238000000034 method Methods 0.000 claims abstract description 19
- 238000004519 manufacturing process Methods 0.000 claims abstract description 13
- 230000001590 oxidative effect Effects 0.000 claims abstract description 5
- 238000010438 heat treatment Methods 0.000 claims description 6
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 claims description 5
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 5
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 2
- 230000003647 oxidation Effects 0.000 abstract description 4
- 238000007254 oxidation reaction Methods 0.000 abstract description 4
- 238000005984 hydrogenation reaction Methods 0.000 abstract description 3
- 238000005280 amorphization Methods 0.000 abstract 1
- 230000000694 effects Effects 0.000 abstract 1
- 150000002500 ions Chemical class 0.000 description 4
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 3
- 229910052739 hydrogen Inorganic materials 0.000 description 3
- 239000001257 hydrogen Substances 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 238000003949 trap density measurement Methods 0.000 description 3
- 238000009832 plasma treatment Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78672—Polycrystalline or microcrystalline silicon transistor
- H01L29/78678—Polycrystalline or microcrystalline silicon transistor with inverted-type structure, e.g. with bottom gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Formation Of Insulating Films (AREA)
- Thin Film Transistor (AREA)
Abstract
본 발명은 게이트 전도막, 상기 게이트 전도막상의 게이트 절연막, 상기 게이트 절연막 상부의 채널용 폴리실리콘막으로 이루어지는 구조를 갖는 박막트랜지스터 제조 방법에 있어서, 상기 채널 폴리실리콘막상에 산화막(8)을 형성하는 단계, 상기 산화막(8) 상에 수분을 다량 함유한 제1BPSG막(9)을 형성하고, 이어서 한 장비내에서 연속하여 치밀한 구조를 갖는 제2BPSG막(9')을 형성하는 단계, 열처리 공정을 통하여 상기 제1 및 제2BPSG막을 평탄화 시키는 동시에 상기 제1BPSG막(9)에 포함된 다량의 수분을 상기 채널 폴리실리콘막(7)에 침투시켜 상기 산화막(8) 및 게이트 산화막(6)과 접촉되는 채널 폴리실리콘막(7) 계면을 산화(10, 10')시키는 단계를 포함하는 것을 특징으로 하는 박막트랜지스터 제조 방법에 관한 것으로, 추가적인 수소화 처리나 산화 공정 없이 채널 폴리실리콘막 계면을 비정질화 하여 결정립계에서의 댕글링 결합을 제거함으로써 포획밀도를 감소시켜 온전류와 오프전류의 비(Ion/Ioff)를 증가시키는 효과가 있다.A thin film transistor manufacturing method having a structure comprising a gate conductive film, a gate insulating film on the gate conductive film, and a polysilicon film for channel on the gate insulating film, wherein the oxide film 8 is formed on the channel polysilicon film. Step, forming a first BPSG film 9 containing a large amount of moisture on the oxide film 8, and subsequently forming a second BPSG film 9 'having a dense structure continuously in one equipment, Planarizing the first and second BPSG films through the same, and injecting a large amount of moisture contained in the first BPSG film 9 into the channel polysilicon film 7 to contact the oxide film 8 and the gate oxide film 6. A method of fabricating a thin film transistor, comprising the step of oxidizing (10, 10 ') an interface of a channel polysilicon film (7), and without additional hydrogenation or oxidation process. It has the effect of increasing the ratio (Ion / Ioff) of the on-current and off-current by reducing the density of trapped by the amorphization of the channel polysilicon film surface to remove the dangling bonds at the grain boundaries.
Description
제 1a 도 내지 제 1c 도는 본 발명에 의한 박막트랜지스터 제조 공정도.1a to 1c is a process chart for manufacturing a thin film transistor according to the present invention.
* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
1: 기판2: 필드산화막1: substrate 2: field oxide film
3: 도전층4, 9, 9': BPSG막3: conductive layer 4, 9, 9 ': BPSG film
5, 7: 폴리실리콘막6: 게이트산화막5, 7: polysilicon film 6: gate oxide film
8, 10, 10': 산화막8, 10, 10 ': oxide film
본 발명은 반도체 제조 공정중 박막트랜지스터(Thin Film Transistor) 제조 방법에 관한 것이다.The present invention relates to a method for manufacturing a thin film transistor (Thin Film Transistor) during the semiconductor manufacturing process.
박막트랜지스터는 채널 부위를 폴리실리콘을 사용하는 트랜지스터이다.The thin film transistor is a transistor using polysilicon in the channel region.
따라서 채널 부위의 폴리실리콘의 오프전류(Off Current)를 억제하거나 온전류(On Current)를 증가시키기가 매우 어려운 단점이 있다.Therefore, it is very difficult to suppress the off current of the polysilicon of the channel portion or to increase the on current.
특히 활성화된 채널영역의 결정립계에서의 댕글링(dangling) 결합(bond)에 운반자(carrier)가 포획(trapping) 되어 온전류 감소와 전기적으로 활성화된 불순물들이 결정립계에 편석됨으로써 불순물 농도감소에 의한 문턱전압(VT) 변화 뿐 아니라 결정립계에 포획된 운반자의 열방출 및 누설전류 증가 등의 문제점이 있다.In particular, carriers are trapped in dangling bonds in the grain boundaries of the activated channel region, thereby reducing the on-current and segregating electrically activated impurities in the grain boundaries, thereby reducing the threshold voltage due to the impurity concentration. In addition to the (VT) change, there are problems such as heat release and leakage current increase of the carrier trapped in the grain boundary.
이러한 문제점을 해결하기 위하여 결정립 크기를 증가시켜 포획밀도(trap density)를 감소시키거나 H2-N2 플라즈마 처리에 의해 활성화된 수소가 폴리실리콘으로 확산하여 결정립계의 실리콘 댕글링 결합에 수소를 결합시켜 포획밀도를 감소시켜 온전류와 오프전류의 비(Ion/Ioff)를 증가시키는 방법이 사용되고 있다.To solve this problem, increase the grain size to reduce the trap density, or hydrogen activated by H2-N2 plasma treatment diffuses into polysilicon to bond hydrogen to the silicon dangling bonds of the grain boundary. A method of increasing the ratio of on current and off current (Ion / Ioff) by reducing the current is used.
그러나 이는 플라즈마 처리를 위한 추가적인 공정이 필요하여 후속 열공정시 450℃ 이상에서 결합된 수소가 다시 방출되는 단점이 있다.However, this requires a further process for the plasma treatment has the disadvantage that the combined hydrogen is released again at more than 450 ℃ during the subsequent thermal process.
또 다른 방법으로는 채널 폴리실리콘막 형성 후 스팀(steam) 분위기에서 열처리 함으로써 채널 폴리실리콘막 계면을 산화시켜 비정질화 함으로써 결정립계를 제거하여 포획밀도를 감소시키는 방법이 있으나, 추가적인 산화공정이 필요한 단점이 있다.Another method is to remove the grain boundary by removing the grain boundary by oxidizing and amorphizing the channel polysilicon film interface by heat treatment in a steam atmosphere after forming the channel polysilicon film, but there is a disadvantage that requires additional oxidation process have.
따라서, 본 발명은 상기의 문제점을 해결하기 위하여 추가적인 수소화 처리나 산화 공정 없이 채널 폴리실리콘막 계면을 비정질화 하여 결정립계에서의 댕글링 결합을 제거함으로써 포획밀도를 감소시켜 온전류와 오프전류의 비(Ion/Ioff)를 증가시키는 박막트랜지스터 제조방법을 제공함을 그 목적으로 한다.Therefore, in order to solve the above problems, the present invention provides a method for ameliorating the channel polysilicon film interface without additional hydrogenation or oxidation to remove dangling bonds at grain boundaries, thereby reducing the capture density, thereby reducing the ratio of on current and off current. It is an object of the present invention to provide a method for manufacturing a thin film transistor which increases Ion / Ioff).
상기 목적을 달성하기 위하여 본 발명은 게이트 전도막, 상기 게이트 전도막상의 게이트 절연막, 상기 게이트 절연막 상부의 채널용 폴리실리콘막으로 이루어지는 구조를 갖는 박막트랜지스터 제조 방법에 있어서, 상기 채널 폴리실리콘막상에 산화막을 형성하는 단계, 상기 산화막 상에 수분을 다량 함유한 제1BPSG막을 형성하고, 이어서 한 장비내에서 연속하여 치밀한 구조를 갖는 제2BPSG막을 형성하는 단계, 열처리 공정을 통하여 상기 제1 및 제2BPSG막을 평탄화 시키는 동시에 상기 제1BPSG막에 포함된 다량의 수분을 상기 채널 폴리실리콘막에 침투시켜 상기 산화막 및 게이트 산화막과 접촉되는 채널 폴리실리콘막 계면을 산화시키는 단계를 포함하는 것을 특징으로 한다.In order to achieve the above object, the present invention provides a thin film transistor manufacturing method comprising a gate conductive film, a gate insulating film on the gate conductive film, and a polysilicon film for channel on the gate insulating film, wherein the oxide film is formed on the channel polysilicon film. Forming a first BPSG film containing a large amount of water on the oxide film, and then forming a second BPSG film having a dense structure continuously in one device, and planarizing the first and second BPSG films through a heat treatment process. And oxidizing a channel polysilicon film interface in contact with the oxide film and the gate oxide film by infiltrating the channel polysilicon film with a large amount of water included in the first BPSG film.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
제 1a 도 내지 제 1c 도는 본 발명에 의한 박막트랜지스터 제조 공정도로서, 채널 폴리실리콘막 계면을 산화시키는 단계를 설명하기 위한 것이다.1A to 1C are process charts for manufacturing a thin film transistor according to the present invention, which illustrate the step of oxidizing a channel polysilicon film interface.
먼저, 제 1a 도는 필드산화막(2) 및 패터닝된 도전층(3)이 형성된 기판(1)상에 BPSG(Boro-Phospho-Silicate-Glass)막(4)을 사용하여 평탄화 시킨 상태에서 평탄화된 상부에 박막트랜지스터의 게이트 전극용 폴리실리콘막(5)을 증착하여 패턴화하고, 게이트산화막(6)을 형성한 후, 채널용 폴리실리콘막(7)을 증착하여 패턴화 한다. 그리고 채널 폴리실리콘막(7)상에 산화막(8)을 형성한다.First, FIG. 1A or the top planarized in the state in which the field oxide film 2 and the patterned conductive layer 3 are planarized by using a BOSG (Boro-Phospho-Silicate-Glass) film 4 on the substrate 1 formed thereon. The polysilicon film 5 for the gate electrode of the thin film transistor is deposited and patterned, the gate oxide film 6 is formed, and then the polysilicon film 7 for the channel is deposited and patterned. An oxide film 8 is formed on the channel polysilicon film 7.
이때, 산화막(8)은 후속 공정인 BPSG막 증착시 BPSG막의 불순물(붕소, 인)이 채널 폴리실리콘막(7)으로 확산되는 것을 방지하기 위한 것이다.At this time, the oxide film 8 is to prevent the impurities (boron, phosphorus) of the BPSG film from being diffused into the channel polysilicon film 7 during the subsequent deposition of the BPSG film.
이어서, 제 1b 도에 도시된 바와같이 상기 산화막(8) 상에 수분을 다량 함유한 제1BPSG막(9)을 형성하고, 이어서 한 장비내에서 연속하여 치밀한 구조를 갖는 제2BPSG 막(9')을 형성한다.Subsequently, as shown in FIG. 1B, a first BPSG film 9 containing a large amount of water is formed on the oxide film 8, and then a second BPSG film 9 'having a continuously compact structure in one equipment is formed. To form.
이때 제1BPSG막(9)은 TEOS/O3 상압 CVD 장비에서 오존(O3)농도 0.5 mol % ∼ 3.0 mol %의 낮은 오존농도를 사용하여 증착하며, 제2BPSG막(9')은 오존 농도 3.0 mol % 이상의 조건에서 증착한다.At this time, the first BSPSG film 9 is deposited using a low ozone concentration of 0.5 mol% to 3.0 mol% ozone (O3) concentration in a TEOS / O3 atmospheric CVD apparatus, and the second BBPSG film 9 'is 3.0 mol% ozone concentration. It deposits on the above conditions.
계속해서, 제 1c 도는 상기 연속하여 적층한 BPSG막을 800℃ 내지 900℃ 에서 평탄화 열처리한 후의 상태를 도시한 것으로, 하층의 제1BPSG막(9)에 포함된 다량의 수분은 열처리 공정시 상층의 제2BPSG막(9')으로 확산되어 증발하고, 동시에 산화막(8) 및 게이트 산화막(6)과 접촉되는 채널 폴리실리콘막(7) 계면을 산화시켜 산화막(10, 10')을 형성한다.Subsequently, FIG. 1C shows a state after the successively stacked BPSG films are subjected to planarization heat treatment at 800 ° C to 900 ° C. The 2BPSG film 9 'is diffused and evaporated, and at the same time, the interface of the channel polysilicon film 7 in contact with the oxide film 8 and the gate oxide film 6 is oxidized to form the oxide films 10 and 10'.
이와같이, 상기 채널 폴리실리콘막 계면을 산화시켜 결정립계에서의 댕글링 결합을 제거함으로써, 포획밀도(trap density)를 효과적으로 감소시켜 Ion/Ioff 비를 증가시킨다.As such, the channel polysilicon film interface is oxidized to remove dangling bonds at grain boundaries, thereby effectively reducing the trap density and increasing the Ion / Ioff ratio.
이상, 상기 설명과 같이 이루어지는 본 발명은 채널 폴리실리콘막의 포획밀도를 감소시키기 위한 추가적인 수소화 처리나 산화공정 없이 이후의 후속 공정에서 BPSG막을 연속하여 적층함으로써 평탄화 열처리 공정시 채널 폴리실리콘막 계면을 산화시켜 포획 밀도의 감소로 Ion/Ioff 비를 효과적으로 증가시킬 수 있다.As described above, the present invention as described above oxidizes the channel polysilicon film interface during the planarization heat treatment process by successively stacking BPSG films in a subsequent process without further hydrogenation or oxidation to reduce the trap density of the channel polysilicon film. Reducing the capture density can effectively increase the Ion / Ioff ratio.
Claims (4)
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| KR1019940034510A KR0140808B1 (en) | 1994-12-15 | 1994-12-15 | Thin film transistor |
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