KR100262297B1 - Method for fabricating transistor of semiconductor device - Google Patents
Method for fabricating transistor of semiconductor device Download PDFInfo
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- KR100262297B1 KR100262297B1 KR1019980021127A KR19980021127A KR100262297B1 KR 100262297 B1 KR100262297 B1 KR 100262297B1 KR 1019980021127 A KR1019980021127 A KR 1019980021127A KR 19980021127 A KR19980021127 A KR 19980021127A KR 100262297 B1 KR100262297 B1 KR 100262297B1
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- Prior art keywords
- film
- titanium
- spacer
- silicon nitride
- transistor
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 24
- 238000000034 method Methods 0.000 title claims abstract description 23
- 125000006850 spacer group Chemical group 0.000 claims abstract description 21
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 17
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims abstract description 17
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 17
- 229910052719 titanium Inorganic materials 0.000 claims abstract description 17
- 239000010936 titanium Substances 0.000 claims abstract description 17
- 229910021341 titanium silicide Inorganic materials 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 13
- 229920005591 polysilicon Polymers 0.000 claims abstract description 13
- 238000000137 annealing Methods 0.000 claims abstract description 9
- 238000005498 polishing Methods 0.000 claims abstract description 8
- 238000000151 deposition Methods 0.000 claims abstract description 5
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 4
- 150000002500 ions Chemical class 0.000 claims description 4
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 4
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 3
- 229910001873 dinitrogen Inorganic materials 0.000 claims description 3
- 238000010030 laminating Methods 0.000 claims description 2
- 238000000059 patterning Methods 0.000 claims 1
- 238000009792 diffusion process Methods 0.000 abstract description 4
- 239000001257 hydrogen Substances 0.000 abstract description 4
- 229910052739 hydrogen Inorganic materials 0.000 abstract description 4
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 abstract description 3
- 230000006866 deterioration Effects 0.000 abstract description 3
- 238000004519 manufacturing process Methods 0.000 abstract 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
Abstract
본 발명은 트랜지스터를 제조하는 방법에 관한 것으로서, 특히, 반도체기판상에 게이트산화막, 폴리실리게이트막을 적층한 게이트의 양측면에 스페이서막을 형성하는 트랜지스터에서, 상기 폴리실리게이트막과 반도체기판의 소오스/드레인 상에 티타늄막을 적층하여 어닐링으로 폴리실리게이트막과 반응하여 티타늄실리사이드막을 형성하는 단계와; 상기 단계 후에 상기 티타늄실리사이드막 상에 잔류된 티타늄막과 양측면에 있는 스페이서막을 제거하는 단계와; 상기 단계 후에 게이트의 티타늄실리사이드막 및 반도체기판의 소오스/드레인 상에 실리콘나이트라이드막을 적층하는 단계와; 상기 단계 후에 실리콘나이트라이드막 상에 절연막을 적층하여 이 절연막에 CMP연마로 평탄화하는 단계로 이루어진 반도체소자의 트랜지스터형성방법인 바, 소오스/드레인간의 단락을 효율적으로 방지하고, LDD영역의 저항을 낮추어서 소자의 성능을 향상시키며, 제1절연층으로서 실리콘나이트라이드막을 사용하므로 수소의 디퓨젼을 막아서 소자의 열화를 방지하도록 하는 매우 유용하고 효과적인 발명이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a transistor. In particular, in a transistor in which a spacer film is formed on both sides of a gate in which a gate oxide film and a polysilicon film are laminated on a semiconductor substrate, source / drain of the polysilicon film and the semiconductor substrate is provided. Stacking a titanium film on the surface and reacting with the polysilicon film by annealing to form a titanium silicide film; Removing the titanium film remaining on the titanium silicide film and the spacer film on both sides after the step; Depositing a silicon nitride film on the titanium silicide film of the gate and the source / drain of the semiconductor substrate after the step; After the above step, a method of forming a transistor of a semiconductor device comprising the step of stacking an insulating film on a silicon nitride film and planarizing the film by CMP polishing, which effectively prevents short-circuit between source / drain and lowers the resistance of the LDD region. It is a very useful and effective invention to improve the performance of the device and to prevent the deterioration of the device by preventing the diffusion of hydrogen because the silicon nitride film is used as the first insulating layer.
Description
본 발명은 반도체소자에서 트랜지스터를 형성하는 방법에 관한 것으로, 특히, 트랜지스터의 게이트 좌,우 양측에 형성된 스페이서막을 제거한 후에 게이트 상에 실리콘나이트라이드막과 HDP산화막을 순차적으로 적층하여 CMP연마로 평탄화하여 소오스/드레인간의 단락을 방지하고, LDD영역의 저항을 낮추어서 소자의 성능을 향상시키도록 하는 반도체소자의 트랜지스터형성방법에 관한 것이다.The present invention relates to a method of forming a transistor in a semiconductor device, and in particular, after removing the spacer film formed on the left and right sides of the gate of the transistor, the silicon nitride film and the HDP oxide film are sequentially stacked on the gate and planarized by CMP polishing. The present invention relates to a method for forming a transistor in a semiconductor device, which prevents a short circuit between the source and drain and improves the device performance by lowering the resistance of the LDD region.
일반적으로, 모스페트 전계효과트랜지스터(MOSFET TR)는 전계효과 트랜지스터중에 절연막을 산화막으로 형성시킨 대표적인 절연게이트형 트랜지스터로서, 반도체기판에 도핑이 낮게되는 영역을 이용하여 반도체소자의 동작전압을 향상시킬 목적으로 LDD영역(Lightly Doped Drain)을 형성하게 된다.In general, a MOSFET field transistor is a typical insulated gate transistor in which an insulating film is formed of an oxide film in a field effect transistor, and an operation voltage of a semiconductor device is improved by using a region having low doping in a semiconductor substrate. LDD region (Lightly Doped Drain) is formed.
도 1은 일반적인 종래의 반도체소자에서 트랜지스터의 단면을 보인 도면으로서, 종래의 트랜지스터의 형성과정을 살펴 보도록 한다.1 is a cross-sectional view of a transistor in a conventional conventional semiconductor device, and looks at a process of forming a conventional transistor.
우선, 도 1에 도시된 바와 같이, 반도체기판(1)에 게이트산화막(2), 폴리실리게이트막(5) 및 타타늄막(6)을 순차적으로 적층하고, 그 위에 감광막을 적층하여 식각을 통하여 불필요한 부분을 제거한후 게이트전극을 형성하도록 한다.First, as shown in FIG. 1, the gate oxide film 2, the polysilicon film 5, and the titanium film 6 are sequentially stacked on the semiconductor substrate 1, and a photoresist film is stacked thereon to form an etching process. After removing unnecessary parts, the gate electrode is formed.
그리고, 상기 게이트전극의 좌,우 양측에 있는 반도체기판(1) 상에 LDD영역을 형성한 후에 게이트전극 상부에 산화막을 적층하여 식각을 통하여 게이트전극의 좌,우측에 스페이서막(7)을 라운딩형상으로 형성하도록 한다.After forming the LDD region on the semiconductor substrate 1 on the left and right sides of the gate electrode, the oxide layer is stacked on the gate electrode and the spacer layer 7 is rounded on the left and right sides of the gate electrode through etching. To form a shape.
그 후에 반도체기판(1)상의 LDD영역에 이온을 주입하여 소오스(Source)(2)/드레인(Drain)(3)을 형성하고, 계속하여 게이트전극의 폴리실리게이트(5) 상에 적층된 티타늄막(6)을 어닐링을 통하여 티타늄실리사이드막(6)으로 형성시키고, 이 티타늄실리사이드막(6)상에 TEOS막/O3-BPSG막/TEOS막으로 이루어진 다층절연막(8)을 순차적으로 적층시키고서 화학기계적연마(CMP, Chemical Mechanical Polishing)로 이 다층절연막(8)을 연마하고, 그 후의 연속된 다른 공정을 진행하도록 한다.Thereafter, ions are implanted into the LDD region on the semiconductor substrate 1 to form a source 2 / drain 3, followed by titanium deposited on the polysilicon 5 of the gate electrode. The film 6 is formed of a titanium silicide film 6 through annealing, and a multilayer insulating film 8 made of a TEOS film / O 3 -BPSG film / TEOS film is sequentially stacked on the titanium silicide film 6. Then, the multilayer insulating film 8 is polished by chemical mechanical polishing (CMP), and then another subsequent process is performed.
그런데, 상기한 바와 같이, 종래의 트랜지스터의 구조는 LDD영역의 구조가 완전하게 게이트에 오버랩되지 않으므로 LDD영역의 저항값이 높게 유지되고, 이로 인하여 통과전류값이 낮아지게 되어 전류의 흐름이 원활하지 못할 뿐만아니라 빽엔드(Back-End)공정에서 발생할 수 있는 수소의 확산을 차단하지 못하여 반도체소자의 열화를 가져오는 문제점을 지니고 있었다.However, as described above, in the structure of the conventional transistor, since the structure of the LDD region is not completely overlapped with the gate, the resistance value of the LDD region is maintained high, which causes the passage current value to be low, thereby smoothly flowing the current. Not only does it prevent the diffusion of hydrogen that may occur in the back-end process has a problem that leads to degradation of the semiconductor device.
본 발명은 이러한 점을 감안하여 안출한 것으로서, 트랜지스터의 게이트 좌,우 양측에 형성된 스페이서막을 제거한 후에 게이트 상에 실리콘나이트라이드막과 HDP산화막을 순차적으로 적층하여 CMP연마를 수행하므로 소오스/드레인간의 단락을 방지하고, LDD영역의 저항을 낮추어서 소자의 성능을 향상시키도록 하는 것이 목적이다.The present invention has been devised in view of the above-mentioned problem, and after removing the spacer films formed at the left and right sides of the gate of the transistor, the silicon nitride film and the HDP oxide film are sequentially stacked on the gate to perform CMP polishing, thereby shorting the source / drain. The purpose is to improve the performance of the device by preventing the resistance and lowering the resistance of the LDD region.
도 1은 종래의 일반적인 반도체소자에서 트랜지스터의 구성을 보인 도면.1 is a view showing the configuration of a transistor in a conventional general semiconductor device.
도 2 내지 도 6은 본 발명에 따른 트랜지스터를 형성하는 방법을 순차적으로 보인 도면.2 to 6 are views sequentially showing a method of forming a transistor according to the present invention.
-도면의 주요부분에 대한 부호의 설명-Explanation of symbols on the main parts of the drawing
10 : 반도체기판 20 : 게이트산화막10: semiconductor substrate 20: gate oxide film
30 : 폴리실리콘막 40 : 소오스30 polysilicon film 40 source
45 : 드레인 50 : 스페이서막45 drain 50 spacer film
60 : 티타늄막 65 : 티타늄실리사이드막60: titanium film 65: titanium silicide film
70 : 실리콘나이트라이드막 80 : 절연막70 silicon nitride film 80 insulating film
이러한 목적은 폴리실리게이트막과 반도체기판의 소오스/드레인 상에 티타늄막을 적층하여 어닐링으로 폴리실리게이트막과 반응하여 티타늄실리사이드막을 형성하는 단계와; 상기 단계 후에 상기 티타늄실리사이드막 상에 잔류된 티타늄막과 스페이서막을 제거하는 단계와; 상기 단계 후에 게이트의 티타늄실리사이드막 및 반도체기판의 소오스/드레인 상에 실리콘나이트라이드막을 적층하는 단계와; 상기 단계 후에 실리콘나이트라이드막 상에 절연막을 적층하여 이 절연막에 CMP연마로 평탄화하는 단계로 이루어진 반도체소자의 트랜지스터형성방법을 제공함으로써 달성된다.The object is to stack a titanium film on a source / drain of a polysilicon film and a semiconductor substrate, and react with the polysilicon film by annealing to form a titanium silicide film; Removing the titanium film and the spacer film remaining on the titanium silicide film after the step; Depositing a silicon nitride film on the titanium silicide film of the gate and the source / drain of the semiconductor substrate after the step; It is achieved by providing a method for forming a transistor of a semiconductor device, which comprises laminating an insulating film on a silicon nitride film after the above step and flattening the insulating film with CMP polishing.
그리고, 상기 스페이서막을 TiN으로 형성하고, 이 스페이서막의 두께는 1000 ∼1200Å으로 형성하는 것이 바람직하고, 상기 티타늄막의 두께는 400 ∼ 500Å으로 증착하고, 이 티타늄막을 어닐링하는 조건은 RTP공정으로 질소가스 분위기에서 720℃, 20초동안 어닐링하는 것이 바람직하다.The spacer film is formed of TiN, and the thickness of the spacer film is preferably 1000 to 1200 kPa. The thickness of the titanium film is deposited to 400 to 500 kPa, and the annealing of the titanium film is carried out in a nitrogen gas atmosphere by an RTP process. Annealing at 720 ° C. for 20 seconds is preferred.
또한, 상기 티타늄막 및 스페이서막에서 불필요한 부분을 제거한 후에 상기 티타늄실리사이드막을 RTP공정으로 850℃에서 20초간 어닐링하는 것이 바람직하고, 상기 실리콘나이트라이드막은 LPCVD법으로 1000 ∼ 2000Å의 두께로 형성되도록 한다.In addition, after removing unnecessary portions from the titanium film and the spacer film, the titanium silicide film is preferably annealed at 850 ° C. for 20 seconds by an RTP process, and the silicon nitride film is formed to have a thickness of 1000 to 2000 kPa by LPCVD.
이하, 첨부한 도면에 의거하여 본 발명의 공정에 대하여 상세히 설명한다.EMBODIMENT OF THE INVENTION Hereinafter, the process of this invention is demonstrated in detail based on an accompanying drawing.
우선, 도 2는 반도체기판(10)상에 게이트산화막(20)을 성장시키고, 그 게이트산화막(20) 상에 폴리실리콘으로 된 폴리실리게이트막(30)을 증착하고, 폴리마스크로 게이트패턴을 형성한 후에 반도체기판(10) 상에 이온을 주입하여 LDD영역을 형성하고, 티타늄나이트라이드막(TiN)을 1000 ∼1200Å의 두께로 증착하여 식각을 통하여 스페이서막(50)을 형성시키며, 계속하여 LDD영역에 이온을 주입하여 소오스(40)/드레인(45)을 형성시키는 상태를 도시하고 있다.2, a gate oxide film 20 is grown on a semiconductor substrate 10, a polysilicon film 30 made of polysilicon is deposited on the gate oxide film 20, and a gate pattern is formed using a polymask. After the formation, an LDD region is formed by implanting ions onto the semiconductor substrate 10, and a titanium nitride film (TiN) is deposited to a thickness of 1000 to 1200 GPa to form a spacer film 50 through etching. The state in which the source 40 / drain 45 is formed by implanting ions into the LDD region is shown.
이때, 상기 스페이서막(50)을 TiN으로 형성하게 되면, 게이트전극에서 소오스(40)/드레인(45)으로 이동하는 전류의 흐름을 원활하게 유지하는 역할을 한다.In this case, when the spacer layer 50 is formed of TiN, the spacer layer 50 smoothly maintains the current flowing from the gate electrode to the source 40 / drain 45.
그리고, 도 3은 게이트패턴의 폴리실리게이트막(30), 스페이서막(50) 및 소오스(40)/드레인(45)상에 티타늄막(60)을 400 ∼ 500Å의 두께로 증착하도록 하고, RTP공정(Rapid Thermal Processing)으로 질소가스 분위기에서 720℃, 20초동안 어닐링하여 폴리실리게이트막(5)과 소오스(40)/드레인(45) 상에 티타늄실리사이드막(65)을 형성하는 상태를 도시하고 있다.3 shows that the titanium film 60 is deposited on the polysilicon film 30, the spacer film 50, and the source 40 / drain 45 of the gate pattern to a thickness of 400 to 500 kPa, and RTP is used. Rapid thermal processing shows the state of forming the titanium silicide film 65 on the polysilicon film 5 and the source 40 / drain 45 by annealing at 720 ° C. for 20 seconds in a nitrogen gas atmosphere. Doing.
또한, 도 4는 티타늄나이트라이드 스페이서막(50)과 잔류되어 있는 티타늄막(60)을 습식식각으로 제거하고, 상기 티타늄실리사이드막(65)의 저항을 낮추고 안정화시키기 위하여 티타늄실리사이드막(65)을 RTP공정으로 850℃에서 20초간 어닐링한 상태를 도시하고 있다.In addition, FIG. 4 illustrates that the titanium silicide layer 65 is removed to wet and remove the titanium nitride spacer layer 50 and the remaining titanium layer 60 by wet etching. The state which annealed at 850 degreeC for 20 second by the RTP process is shown.
그리고, 도 5는 계속하여 게이트패턴상에 제1절연층 역할을 하는 실리콘나이트라이드막(70)을 LPCVD법(저압화학기상증착법)으로 1000 ∼ 2000Å의 두께로 형성한 상태를 도시하고 있다.5 shows a state in which a silicon nitride film 70 serving as a first insulating layer on the gate pattern is formed to a thickness of 1000 to 2000 kPa by LPCVD (low pressure chemical vapor deposition).
한편, 도 6은 상기 실리콘나이트라이드막(70) 상에 HDP산화막(High Density Plasma Oxide)으로 된 제2의 절연막(80)을 적층하고 소자의 평탄화를 위하여 CMP공정(화학기계적연마)를 수행한 상태를 도시하고 있다.6 shows a second insulating film 80 made of HDP oxide film (High Density Plasma Oxide) on the silicon nitride film 70, and a CMP process (chemical mechanical polishing) is performed to planarize the device. The state is shown.
이때, 상기 제1절연층으로 사용되는 실리콘나이트라이드막(70)은 구조가 치밀하여 Back-End 공정에서 발생하는 수소의 디퓨젼을 막아 반도체소자의 열화를 방지하며, 게이트의 전계(Electric Field)를 LDD영역으로 전달할 수 있어 LDD영역의 저항값을 줄일 수 있어 소자의 성능을 크게 향상시키는 역할을 하게 된다.At this time, the silicon nitride film 70 used as the first insulating layer has a dense structure to prevent the diffusion of hydrogen generated in the back-end process to prevent deterioration of the semiconductor device, and the gate electric field Can be transferred to the LDD region, thereby reducing the resistance value of the LDD region, thereby greatly improving the performance of the device.
따라서, 상기한 바와 같이 본 발명에 따른 트랜지스터 형성방법을 이용하게 되면, 트랜지스터의 게이트 좌,우 양측에 형성된 스페이서막을 제거한 후에 게이트 상에 실리콘나이트라이드막과 HDP산화막을 순차적으로 적층하여 CMP연마를 수행하므로 게이트의 스페이서막이 없어지므로 인하여 소오스/드레인간의 단락을 효율적으로 방지하고, LDD영역의 저항을 낮추어서 소자의 성능을 향상시키며, 제1절연층으로서 실리콘나이트라이드막을 사용하므로 수소의 디퓨젼을 막아서 소자의 열화를 방지하도록 하는 매우 유용하고 효과적인 발명이다.Therefore, when the transistor forming method according to the present invention is used as described above, CMP polishing is performed by sequentially depositing a silicon nitride film and an HDP oxide film on the gate after removing the spacer films formed at both the left and right sides of the gate of the transistor. Therefore, since the gate spacer film is eliminated, the short circuit between the source and drain can be effectively prevented, the device performance is improved by lowering the resistance of the LDD region, and the silicon nitride film is used as the first insulating layer, thereby preventing hydrogen diffusion. It is a very useful and effective invention to prevent deterioration.
Claims (5)
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