JPH0499365A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH0499365A
JPH0499365A JP2208955A JP20895590A JPH0499365A JP H0499365 A JPH0499365 A JP H0499365A JP 2208955 A JP2208955 A JP 2208955A JP 20895590 A JP20895590 A JP 20895590A JP H0499365 A JPH0499365 A JP H0499365A
Authority
JP
Japan
Prior art keywords
ferroelectric film
become
film
oxide film
pbtio3
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2208955A
Other languages
Japanese (ja)
Inventor
Kazuhiro Takenaka
竹中 計廣
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP2208955A priority Critical patent/JPH0499365A/en
Publication of JPH0499365A publication Critical patent/JPH0499365A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B53/00Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE:To enhance insulating breakdown strength and to increase a capacity value per unit area by forming a ferroelectric film on a high concentration diffused layer, and forming an oxide film containing any of Ti, Hf, Zr, V, Nb, Ta as a main ingredient at least in part therebetween. CONSTITUTION:An N-type diffused layer 104 to become a drain is formed simultaneously with an N-type diffused layer 103 to become a source. A gate electrode 105 is formed, for example, of phosphorus-doped polysilicon. A ferroelectric film 105 of PbTiO3, PZT (PbZrO3, PbTiO3), PLZT (La, PbZrO3, PbTiO3) is formed, for example, by a sputtering method. An electrode 107 of the ferroelectric film is made, for example, of polysilicon, and formed, for example, by a CVD method. An oxide film 110 containing any of Ti, Hf, Zr, V, Nb, Ta to become a constituent as a main ingredient is formed, for example, by forming the metal by a sputtering method, and then annealing it in an atmosphere containing oxygen to oxidize the metal to become an oxide film.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、強誘電体を用いた、メモリ、中でも特に、容
量に電荷をためることに°より信号を記憶する、ダイナ
ミックRAMの構造に関するもので〔発明の概要〕 本発明は、強誘電体膜を用いた、メモリの構造において
、強誘電体膜が、高濃度拡散層上に形成され、かつ強誘
電体膜と高濃度拡散層との間の少なくとも一部分に、T
i、Hf、Zr、V、Nb、Taのうちのいずれかを主
成分とする酸化膜を形成することにより、比誘電率の大
きい、かつ、絶縁耐圧の高いキャパシタを集積化させた
メモリを得るようにしたものである。
[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a structure of a memory using a ferroelectric material, particularly a dynamic RAM that stores signals by storing electric charge in a capacitor. [Summary of the Invention] The present invention provides a memory structure using a ferroelectric film, in which the ferroelectric film is formed on a high concentration diffusion layer, and the ferroelectric film and the high concentration diffusion layer are connected to each other. at least a portion between T
By forming an oxide film containing any one of i, Hf, Zr, V, Nb, and Ta as a main component, a memory in which a capacitor with a high dielectric constant and withstand voltage is integrated is obtained. This is how it was done.

〔従来の技術〕[Conventional technology]

従来の半導体メモIJ D RA Mとしては、高濃度
拡散層上に8102をキャパシタの絶縁膜としてもちい
ていた。
In the conventional semiconductor memory IJD RAM, 8102 was used as a capacitor insulating film on a heavily doped diffusion layer.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

しかし、近年、微細化が進み、素子面積を小さ(する努
力がされている。微細化を進めると、キャバシタを形成
する面積も小さ(成り、電荷を貯えるに必要な容量を確
保出来な(なってきた。そこで、例えば、キャパシタの
面積を太き(取るために、トレンチ型のキャパシタや、
キャパシタをトランジスタの上部にまで集積化させたス
タック型のキャパシタなどのように、構造によりキャパ
シタの面積を太き(する試みや、S i tJ9、Ta
O2などのように比誘電率が大きい材料を用いてキャパ
シタの容量を増です試みなどがされてきたしかし、これ
らのいずれの方法も十分な容量を得るまでにはいたって
いない。そこで本発明はこのような課題を解決するもの
で、その目的とするところは、比誘電率が桁違いに大き
い強誘電体膜を用いて、容量の大きいキャパシタを持ち
、がっ、絶縁耐圧の十分なりRAMなどの半導体メモリ
を提供するところにある。
However, in recent years, miniaturization has progressed, and efforts are being made to reduce the element area. Therefore, for example, in order to increase the area of the capacitor, trench-type capacitors,
Attempts have been made to increase the area of the capacitor depending on the structure, such as stacked capacitors in which the capacitor is integrated to the top of the transistor, Si tJ9, Ta
Attempts have been made to increase the capacitance of a capacitor by using a material with a high dielectric constant, such as O2, but none of these methods has reached the point where a sufficient capacitance can be obtained. The present invention is intended to solve these problems, and its purpose is to create a capacitor with a large capacitance by using a ferroelectric film with an order of magnitude higher dielectric constant, and to create a capacitor with a high dielectric strength. There are enough semiconductor memories such as RAM available.

〔課題を解決するための手段〕[Means to solve the problem]

本発明は、強誘電体膜を用いたメモリの構造において、
強誘電体膜が高濃度拡散層上に形成され、かつ強誘電体
膜と高濃度拡散層との間の少なくとも一部分に、Ti、
Hf、Zr、V、Nb、Taのうちのいずれかを主成分
とする酸化膜を形成したことを特徴とする。
The present invention provides a structure of a memory using a ferroelectric film.
A ferroelectric film is formed on the high concentration diffusion layer, and at least a portion between the ferroelectric film and the high concentration diffusion layer contains Ti,
It is characterized in that an oxide film containing any one of Hf, Zr, V, Nb, and Ta as a main component is formed.

〔実施例〕〔Example〕

第1図は、本発明の半導体装置の一実施例に於ける主要
断面図である。以下、第1図に従い、本発明の半導体装
置を説明する。ここでは説明の都合上81基板を用い、
Nチャンネルトランジスタを用いた例につき説明する。
FIG. 1 is a main sectional view of an embodiment of the semiconductor device of the present invention. The semiconductor device of the present invention will be described below with reference to FIG. For convenience of explanation, 81 board is used here.
An example using an N-channel transistor will be explained.

101はP型S1基板であり、例えば200bm、αの
比抵抗のウェハを用いる。102は捩子分離用の絶縁膜
であり、例えば、パ、従来技術であるLOOO3法によ
り酸化膜を60[10A形成する103はソースとなる
N型拡散層であり、例えばリンを80にθV5Eff5
>−2イオン注入することにより形成する。104はド
レインとなるN型拡散層であり、106と同時に形成す
る。105はゲート電極であり、例えばリンでドープさ
れたポIJ S iを用いる。106が本発明の構成要
素となる、強誘電体膜であるPbTiO3、PZT(P
bZrOs  、pb’rio3 、PLZT(La、
PbZrO3、PbTi08)であり、例えばスパッタ
法などにより1000A形成する。107は強誘電体膜
の電極となる例えばボ+) 3 iであり、例えばCV
D法により150[]Aの膜厚で形成する。108は1
07の電極とドレインへの配線電極である109を分離
する絶縁膜であり、(i!:! コテハ、CVD法によ
りS i O2膜を400OA形成する。そして110
が本発明のもう一つの構成要素となるTi、Hf、Zr
、V、Nb、Taの5ちのいずれかを主成分とする酸化
膜であり、例えば、これらの金属をスパッタ法により、
例えば100A形成後、1060強誘電体膜を同じくス
パッタ法により形成後、酸素を含む雰囲気中でアニール
することにより、これらの金属は酸化され酸化膜となる
Reference numeral 101 denotes a P-type S1 substrate, for example, a wafer of 200 bm and a specific resistance of α is used. Reference numeral 102 is an insulating film for screw isolation, and 103 is an N-type diffusion layer that will serve as a source. For example, an oxide film is formed using phosphorus at 60[10A] using the conventional LOOO3 method.
>-2 ion implantation. Reference numeral 104 denotes an N-type diffusion layer which becomes a drain, and is formed at the same time as 106. A gate electrode 105 is made of, for example, phosphorus-doped PoIJSi. 106 is a ferroelectric film PbTiO3, PZT (P
bZrOs, pb'rio3, PLZT(La,
PbZrO3, PbTi08), and is formed with a thickness of 1000 A by, for example, a sputtering method. 107 is an electrode of the ferroelectric film, for example, Bo+) 3 i, for example, CV
It is formed with a film thickness of 150[]A by method D. 108 is 1
This is an insulating film that separates the electrode 07 and the wiring electrode 109 to the drain.
Ti, Hf, Zr, which is another component of the present invention
, V, Nb, and Ta. For example, these metals are sputtered by sputtering.
For example, after forming 100A, a 1060 ferroelectric film is also formed by the sputtering method, and then annealing is performed in an atmosphere containing oxygen, whereby these metals are oxidized and become an oxide film.

さて、第1図のような構造のキャパシタの容量いま例と
してTiO□を用いた場合について考えてみると、強誘
電体膜の比誘電率は、仮に強誘電体膜としてPZTを用
いた場合、約1000であるため、 i / C= I / O(T i O2) + 1 
/ C(P Z T )となり、前述した膜厚(pzT
=t 0OCIA、Ti02=100.A、TiO2の
比誘電率=80)で計算すると、5102換算で膜厚1
0Aのキャビくシタが形成出来る。かりに10OAのT
iO2のみの場合には、絶縁耐圧が数ボルトしかなく、
素子は構成出来なかった。それに対し、第1図のように
TlO2と強誘電体膜を積層化させることにより、絶縁
耐圧としては20Vの値が得られ、絶縁耐圧としても十
分であり、かつ容量としても非常に畦位面檀当たりの容
量値が大ぎいキャパシタが得られた。また、PZTの構
成元素、特に4族、及び5族の遷移金属の酸化物を用い
ることにより、PZTの結晶性が優れ、また比誘電率な
どの電気特性も優れた強誘電体膜が形成出来る。
Now, considering the case where TiO□ is used as an example, the relative dielectric constant of the ferroelectric film is as follows: If PZT is used as the ferroelectric film, Since it is about 1000, i/C=I/O(T i O2) + 1
/C(PZT), and the film thickness (pzT
=t0OCIA, Ti02=100. A, relative dielectric constant of TiO2 = 80), the film thickness is 1 in terms of 5102.
A 0A cavity can be formed. Karini 10OA T
In the case of only iO2, the dielectric strength is only a few volts,
The element could not be configured. On the other hand, by laminating TlO2 and a ferroelectric film as shown in Figure 1, a dielectric strength value of 20V can be obtained, which is sufficient as a dielectric strength voltage and has a very low capacitance. A capacitor with a large capacitance value per unit was obtained. In addition, by using oxides of PZT's constituent elements, particularly group 4 and group 5 transition metals, it is possible to form a ferroelectric film with excellent crystallinity of PZT and excellent electrical properties such as dielectric constant. .

さらにPZTを形成後、酸素を含む雰囲気中でアニール
することにより、さらに比誘電率が大きい強誘電体膜を
得ることが出来る。実際にアニールを行なわない場合に
は比誘電率が500(PZTの場合)に対し、アニール
を行なうことにより、比誘電率として1500の値が得
られた。
Furthermore, by annealing in an atmosphere containing oxygen after forming PZT, a ferroelectric film with an even higher dielectric constant can be obtained. When no annealing was actually performed, the relative permittivity was 500 (in the case of PZT), but by annealing, a relative permittivity of 1500 was obtained.

〔発明の効果〕〔Effect of the invention〕

本発明のように、強誘電体膜を用いた、メモリの構造に
おいて、強誘電体膜が高濃度拡散層上に形成され、かつ
強誘電体膜と高濃度拡散層との間の少なくとも一部分に
、Ti、Hf、Zr、V。
As in the present invention, in a memory structure using a ferroelectric film, the ferroelectric film is formed on a high concentration diffusion layer, and at least a portion between the ferroelectric film and the high concentration diffusion layer is provided. , Ti, Hf, Zr, V.

Nb、Taのうちのいずれかを主成分とする酸化膜を形
成したため、絶縁耐圧が高(、かつ容量としても、非常
に一位面積当たりの容量値が大きいキャパシタが集積化
出来るという効果を有する。
Since an oxide film containing either Nb or Ta as a main component is formed, it has the effect of being able to integrate a capacitor with a high dielectric strength voltage (and a very large capacitance per area). .

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の主要断面図である。 101・・・・・・・・・S1基板 102・・・・・・・・・累子分離絶縁膜106・・・
・・・・・・ソース拡散層・・・・・・・・・ドレイン
拡散層 ・・・・・・・・・ゲート電極 ・・・・・・・・・強誘電体膜 ・・・・・・・・・電 極 ・・・・・・・・・層間絶縁膜 ・・・・・・・・・配線電極 ・・・・・・・・・T i O。
FIG. 1 is a main sectional view of the present invention. 101...S1 substrate 102...Separator isolation insulating film 106...
......Source diffusion layer...Drain diffusion layer...Gate electrode...Ferroelectric film... ...Electrode...Interlayer insulating film...Wiring electrode...T i O.

Claims (1)

【特許請求の範囲】[Claims] (1)強誘電体膜が、能動素子が形成された同一半導体
基板上に、集積された半導体装置において、前記強誘電
体膜が前記高濃度拡散層上に形成され、かつ前記強誘電
体膜と前記高濃度拡散層との間の少なくとも一部分に、
Ti、Hf、Zr、V、Nb、Taのうちのいずれかを
主成分とする酸化膜が形成されていることを特徴とする
半導体装置。
(1) In a semiconductor device in which a ferroelectric film is integrated on the same semiconductor substrate on which active elements are formed, the ferroelectric film is formed on the high concentration diffusion layer, and the ferroelectric film and the high concentration diffusion layer,
A semiconductor device characterized in that an oxide film containing any one of Ti, Hf, Zr, V, Nb, and Ta as a main component is formed.
JP2208955A 1990-08-07 1990-08-07 Semiconductor device Pending JPH0499365A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2208955A JPH0499365A (en) 1990-08-07 1990-08-07 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2208955A JPH0499365A (en) 1990-08-07 1990-08-07 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH0499365A true JPH0499365A (en) 1992-03-31

Family

ID=16564918

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2208955A Pending JPH0499365A (en) 1990-08-07 1990-08-07 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH0499365A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001045161A1 (en) * 1999-12-14 2001-06-21 Matsushita Electric Industrial Co., Ltd. Nonvolatile memory and method of driving nonvolatile memory
US6465260B1 (en) 1999-06-28 2002-10-15 Hyundai Electronics Industries Co., Ltd. Semiconductor device having a ferroelectric capacitor and method for the manufacture thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6465260B1 (en) 1999-06-28 2002-10-15 Hyundai Electronics Industries Co., Ltd. Semiconductor device having a ferroelectric capacitor and method for the manufacture thereof
WO2001045161A1 (en) * 1999-12-14 2001-06-21 Matsushita Electric Industrial Co., Ltd. Nonvolatile memory and method of driving nonvolatile memory
US6667501B2 (en) 1999-12-14 2003-12-23 Matsushita Electric Industrial Co., Ltd. Nonvolatile memory and method for driving nonvolatile memory

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