JPH046867A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH046867A JPH046867A JP2108019A JP10801990A JPH046867A JP H046867 A JPH046867 A JP H046867A JP 2108019 A JP2108019 A JP 2108019A JP 10801990 A JP10801990 A JP 10801990A JP H046867 A JPH046867 A JP H046867A
- Authority
- JP
- Japan
- Prior art keywords
- film
- electrode
- ferroelectric film
- capacitor
- diffused layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 9
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 238000009792 diffusion process Methods 0.000 claims description 9
- 150000004767 nitrides Chemical class 0.000 claims description 6
- 229910052750 molybdenum Inorganic materials 0.000 claims description 2
- 229910052702 rhenium Inorganic materials 0.000 claims description 2
- 229910052707 ruthenium Inorganic materials 0.000 claims description 2
- 229910052719 titanium Inorganic materials 0.000 claims description 2
- 229910052763 palladium Inorganic materials 0.000 claims 1
- 229910052697 platinum Inorganic materials 0.000 claims 1
- 239000003990 capacitor Substances 0.000 abstract description 17
- 238000009413 insulation Methods 0.000 abstract description 3
- 238000000137 annealing Methods 0.000 abstract description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 2
- 150000002500 ions Chemical class 0.000 abstract description 2
- 229910052760 oxygen Inorganic materials 0.000 abstract description 2
- 239000001301 oxygen Substances 0.000 abstract description 2
- 229910052581 Si3N4 Inorganic materials 0.000 abstract 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 1
- 230000015556 catabolic process Effects 0.000 abstract 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract 1
- 229910052814 silicon oxide Inorganic materials 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 8
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 238000002955 isolation Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910004160 TaO2 Inorganic materials 0.000 description 1
- 229910001361 White metal Inorganic materials 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- NQKXFODBPINZFK-UHFFFAOYSA-N dioxotantalum Chemical compound O=[Ta]=O NQKXFODBPINZFK-UHFFFAOYSA-N 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 239000010969 white metal Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、強誘電体を用いた、メモリ、中でも特に、容
量に電荷をためることにより信号を記憶する、ダイナミ
ックＲＡＭの構造に関するものである。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a structure of a memory using a ferroelectric material, and in particular, a dynamic RAM that stores signals by storing charge in a capacitor. .
本発明は、強誘電体膜を用いた、メモリの構造において
、強誘電体膜が、電極に挟まれて形成され、電極のうち
のとちらか一方と、高濃度拡散層との間に、酸化Ｓ１が
、窒化Ｓｉ膜か形成することにより、比誘電率の大きい
、かつ、絶縁耐圧の高いキャパシタを集積化させたメモ
リを得るようにしたものである。The present invention provides a memory structure using a ferroelectric film, in which the ferroelectric film is formed between electrodes, and between one of the electrodes and a high concentration diffusion layer. By forming the oxide S1 as a Si nitride film, a memory in which a capacitor having a high dielectric constant and a high dielectric strength voltage is integrated can be obtained.
従来の半導体メモリＤＲＡＭとしては、高濃度拡散層上
に５ｉ０２をキャパシタの絶縁膜としてもちいていた。In a conventional semiconductor memory DRAM, 5i02 was used as a capacitor insulating film on a heavily doped diffusion layer.
しかし、近年、微細化が進み、素子面積を小さくする努
力がされている。微細化を進めると、キャパシタを形成
する面積も小さく成り、電荷を貯えるに必要な容量を確
保出来なくなってきた。そこで、例えば、キャパシタの
面積を大きく取るために、トレンチ型のキャパシタや、
キャパシタをトランジスタの上部にまで集積化させたス
タック型のキャパシタなどのように、構造によりキャパ
シタの面積を大きくする試みや、ＳｉＮや、ＴａＯ２な
どのように比誘電率か大きい材料を用いてキャパシタの
容量を増やす試みなどがされてきた。However, in recent years, miniaturization has progressed and efforts have been made to reduce the element area. As miniaturization progresses, the area on which a capacitor is formed also becomes smaller, making it difficult to secure the capacity necessary to store charge. Therefore, for example, in order to increase the area of the capacitor, trench-type capacitors,
Attempts have been made to increase the area of the capacitor by changing its structure, such as stacked capacitors in which the capacitor is integrated to the top of the transistor, and by using materials with high dielectric constants such as SiN and TaO2. Attempts have been made to increase capacity.
しかし、これらのいずれの方法も十分な容量を得るまで
にはいたっていない。そこで本発明はこのような課題を
解決するもので、その目的とする所は、比誘電率が桁違
いに大きい強誘電体膜を用いて、容量の大きいキャパシ
タを持ち、かつ、絶縁耐圧の十分なりＲＡＭなどの半導
体メモリを提供する所にある。However, none of these methods has reached the point where sufficient capacity can be obtained. The present invention is intended to solve these problems, and its purpose is to create a capacitor with a large capacitance and sufficient dielectric strength by using a ferroelectric film with an order of magnitude higher relative dielectric constant. It is located in a place that provides semiconductor memory such as RAM.
本発明は、強誘電体膜を用いたメモリの構造において、
強誘電体膜が、電極に挾まれて形成され、電極のうちの
どちらか一方と、高濃度拡散層との間に、酸化Ｓｉが、
窒化Ｓ１膜か形成したことを特徴とする。The present invention provides a structure of a memory using a ferroelectric film.
A ferroelectric film is formed between electrodes, and Si oxide is formed between one of the electrodes and the high concentration diffusion layer.
It is characterized in that a nitride S1 film is formed.
第１図は、本発明の半導体装置の一実施例に於ける主要
断面図である。以下、第１図に従い、本発明の半導体装
置を説明する。ここでは説明の都合上Ｓｉ基板を用い、
Ｎチャンネルトランジスタを用いた例につき説明する。FIG. 1 is a main sectional view of an embodiment of the semiconductor device of the present invention. The semiconductor device of the present invention will be described below with reference to FIG. For convenience of explanation, a Si substrate is used here.
An example using an N-channel transistor will be explained.
（１０１）はＰ型Ｓｉ基板であり、例えば２００ｈｍ、
ｃｍの比抵抗のウエノ＼を用いる。（１０２）は素子分
離用の絶縁膜であり、例えば、従来技術であるＬＯＣＯ
５法により酸化膜を６００ＯＡ形成する。（１０３）は
ソースとなるＮ型拡散層でアリ、例エバリンを８０Ｋｅ
Ｖ５Ｅ１５ｃｍ２イオン注入することにより形成する。(101) is a P-type Si substrate, for example, 200hm,
Ueno\ with a resistivity of cm is used. (102) is an insulating film for element isolation, for example, the conventional LOCO
An oxide film having a thickness of 600 OA is formed using method No. 5. (103) is an N-type diffusion layer that becomes a source, for example Evalin is 80Ke.
It is formed by implanting V5E15cm2 ions.
（１０４）はドレインとなるＮ型拡散層であり、（１０
３）と同時に形成する。（１０５）はゲート電極であり
、例えばリンでドープされたポリＳｔを用いる。（１０
６）が本発明の構成要素となる、強誘電体膜であるＰ
ｂ Ｔ ｉ Ｏ３、Ｐ Ｚ Ｔ （Ｐ ｂ Ｚ ｒ０３
、ＰｂＴ ｉＯ，、ＰＬＺＴ （Ｌａ、ＰｂＺ ｒ０
３ 、Ｐ ｂ Ｔ ｉ ０３ ）であり、例えばスパッ
タ法なとにより１００ＯＡ形成する。（１１１）か本発
明の構成要素である電極であり、例えばｐｔを１０００
Ａ、スパッタ法により形成する。（１０７）は強誘電体
膜の電極となる例えばポリＳｉであり、例えばＣＶＤ法
により１５００Ａの膜厚て形成する。（１０８）は（１
０７）の電極とドレインへの配線電極である（１０９）
を分離する絶縁膜であり、ここでは、ＣＶＤ法により５
ｉ０２膜を４０００Ａ形成する。そして（１１０）か本
発明のもう一つの構成要素となる酸化Ｓｉ膜であり、例
えば、酸素を含む雰囲気中でのランプアニールにより、
１５Ａの均一な酸化Ｓｉ膜を（１０６）の強誘電体膜の
形成前に形成する。(104) is an N-type diffusion layer that becomes a drain, and (10
3) Form at the same time. (105) is a gate electrode, for example, polySt doped with phosphorus is used. (10
6) is a ferroelectric film P which is a component of the present invention.
b T i O3, P Z T (P b Z r03
, PbT iO,, PLZT (La, PbZ r0
3, P b T i 03 ), and is formed with a thickness of 100 OA by, for example, a sputtering method. (111) is an electrode that is a component of the present invention, for example, pt is 1000
A. Formed by sputtering method. (107) is poly-Si, for example, which becomes the electrode of the ferroelectric film, and is formed to a thickness of 1500 Å by, for example, the CVD method. (108) is (1
(109) is the wiring electrode to the electrode and drain of 07)
This is an insulating film that separates the
A 4000A i02 film is formed. And (110) is a Si oxide film which is another component of the present invention, for example, by lamp annealing in an atmosphere containing oxygen.
A uniform Si oxide film of 15A is formed before forming the ferroelectric film (106).
さて、第１図のような構造のキャパシタの容量について
考えてみると、強誘電体膜の比誘電率は、仮に強誘電体
膜としてＰＺＴを用いた場合、約１０００であるため、
１／Ｃ＝１／Ｃ（Ｓ １０２）＋１／Ｃ（ＰＺＴ）とな
り、前述した膜厚で計算すると、５ｉ０２換算て１．４
Ａのキャパシタが形成出来る。この換算膜厚は、（１
１０）の酸化Ｓｉ膜の膜厚とほぼかわりはないが、（１
１０）の様に、１５Ａの膜厚の酸化Ｓｉ膜のみを直接キ
ャパシタの絶縁膜とした場合には、絶縁耐圧が数ボルト
しかなく、素子は構成出来なかった。それに対し、第１
図のように酸化Ｓｉ膜と強誘電体膜を積層化させること
により、絶縁耐圧としては２０Ｖの値が得られ、絶縁耐
圧としても十分であり、かつ容量としても、非常に単位
面積当たりの容量値が大きいキャパシタが得られた。ま
た、強誘電体膜の電極として、ｐｔなとの強誘電体膜（
ＰＺＴ、ＰＬＺＴＳＰｂＴｉ０３など）と格子定数の近
い金属を用いることにより、結晶性の優れ、また比誘電
率などの電気特性も優れた強誘電体膜が形成出来る。実
際に（１１１）の電極を用いない場合には比誘電率が８
００ （ＰＺＴの場合）に対し、（１１１）の電極を用
いることにより、比誘電率として１５００の値が得られ
た。このような効果はｐｔばかりでなく、白金属の他の
金属、Ｒｅや、Ｒｕなと、また高融点金属ＭｏやＴｉｔ
ども効果の差はあれ、効果があることも分かった。Now, if we consider the capacitance of a capacitor with the structure shown in Figure 1, the relative dielectric constant of the ferroelectric film is approximately 1000 if PZT is used as the ferroelectric film, so it is 1/C. = 1/C (S 102) + 1/C (PZT), and when calculated using the film thickness mentioned above, it is 1.4 in terms of 5i02.
Capacitor A can be formed. This equivalent film thickness is (1
Although the thickness is almost the same as that of the Si oxide film in (10),
10), when only a 15A thick Si oxide film was directly used as the insulating film of the capacitor, the dielectric strength was only a few volts, and the device could not be constructed. On the other hand, the first
As shown in the figure, by laminating a Si oxide film and a ferroelectric film, a dielectric strength value of 20V can be obtained, which is sufficient as a dielectric strength voltage and has a very high capacitance per unit area. A capacitor with a large value was obtained. In addition, as an electrode of the ferroelectric film, a ferroelectric film such as PT (
By using a metal with a lattice constant similar to that of PZT, PLZTSPbTi03, etc.), a ferroelectric film with excellent crystallinity and electrical properties such as dielectric constant can be formed. In fact, when the (111) electrode is not used, the dielectric constant is 8
00 (in the case of PZT), by using the (111) electrode, a value of 1500 was obtained as the dielectric constant. This effect is not limited to PT, but also other metals other than white metal, such as Re and Ru, as well as high melting point metals such as Mo and Ti.
It was also found that it was effective, although there were differences in effectiveness.
以上の説明においては、強誘電体膜を積層する絶縁膜と
して、酸化Ｓｉ膜を用いた場合について説明したが、窒
化Ｓｉ膜や、酸化Ｓｉ膜と窒化Ｓｉ膜の積層膜を用いて
も良いことはいうまでもない。In the above explanation, a case was explained in which a Si oxide film was used as the insulating film on which the ferroelectric film is laminated, but it is also possible to use a Si nitride film or a laminated film of a Si oxide film and a Si nitride film. Needless to say.
本発明のように、強誘電体膜を用いた、メモリの構造に
おいて、強誘電体膜が、電極に挟まれて形成され、電極
のうちのどちらか一方と、高濃度拡散層との間に、酸化
Ｓｔが、窒化Ｓｉ膜を形成したため、絶縁耐圧が高く、
かつ容量としても、非常に単位面積当たりの容量値が大
きいキャパシタが集積化出来るという効果を有する。In a memory structure using a ferroelectric film as in the present invention, the ferroelectric film is formed sandwiched between electrodes, and between one of the electrodes and a high concentration diffusion layer. , St oxide formed a Si nitride film, so the dielectric strength was high;
Also, in terms of capacitance, it has the effect that capacitors with extremely large capacitance values per unit area can be integrated.
Ｓｉ基板 素子分離絶縁膜 ソース拡散層 ドレイン拡散層 ゲート電極 強誘電体膜 電極 層間絶縁膜 配線電極 キャパシタ絶縁膜 電極 出願人 セイコーエプソン株式会社 代理人 弁理士 鈴 木 喜三部（他１名）Si substrate Element isolation insulating film source diffusion layer drain diffusion layer gate electrode ferroelectric film electrode interlayer insulation film wiring electrode capacitor insulation film electrode Applicant: Seiko Epson Corporation Agent: Patent attorney Kisanbe Suzuki (1 other person)
第１図は本発明の主要断面図である。 FIG. 1 is a main sectional view of the present invention.
Claims (2)
基板上に、集積された半導体装置において、前記強誘電
体膜が電極に挟まれて形成され、前記電極のうちのどち
らか一方と、前記半導体主表面上に形成された高濃度拡
散層との間の少なくとも一部分に、酸化Ｓｉか、窒化Ｓ
ｉ膜のいずれかの絶縁膜が形成されてることを特徴とす
る半導体装置。(1) In a semiconductor device in which a ferroelectric film is integrated on the same semiconductor substrate on which active elements are formed, the ferroelectric film is formed sandwiched between electrodes, and either one of the electrodes and the high-concentration diffusion layer formed on the main surface of the semiconductor, Si oxide or S nitride is formed.
A semiconductor device characterized in that any one of the insulating films of the i-film is formed.
、Ｗのうちのいずれかの金属を主成分とした電極である
ことを特徴とする請求項１記載の半導体装置。(2) The electrode is made of Pt, Pd, Ru, Re, Mo, Ti
, W. , W. , W. , W. , W. , W. , W.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2108019A JPH046867A (en) | 1990-04-24 | 1990-04-24 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2108019A JPH046867A (en) | 1990-04-24 | 1990-04-24 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH046867A true JPH046867A (en) | 1992-01-10 |
Family
ID=14473920
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2108019A Pending JPH046867A (en) | 1990-04-24 | 1990-04-24 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH046867A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5939744A (en) * | 1995-03-22 | 1999-08-17 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device with x-ray absorption layer |
| US6281536B1 (en) | 1998-04-08 | 2001-08-28 | Nec Corporation | Ferroelectric memory device with improved ferroelectric capacity characteristic |
| US6384440B1 (en) | 1999-11-10 | 2002-05-07 | Nec Corporation | Ferroelectric memory including ferroelectric capacitor, one of whose electrodes is connected to metal silicide film |
-
1990
- 1990-04-24 JP JP2108019A patent/JPH046867A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5939744A (en) * | 1995-03-22 | 1999-08-17 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device with x-ray absorption layer |
| US6049103A (en) * | 1995-03-22 | 2000-04-11 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor capacitor |
| US6281536B1 (en) | 1998-04-08 | 2001-08-28 | Nec Corporation | Ferroelectric memory device with improved ferroelectric capacity characteristic |
| US6384440B1 (en) | 1999-11-10 | 2002-05-07 | Nec Corporation | Ferroelectric memory including ferroelectric capacitor, one of whose electrodes is connected to metal silicide film |
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