JPH0499063A - Master slice type semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To suppress a current, which is made to flow in the state of readout, by a method wherein a P-channel transistor or an N-channel transistor has a fixed potential at the source region or drain region of the P-channel transistor or the N-channel transistor in a single element and as a terminal for storage of a readout-only storage circuit. CONSTITUTION:An N-channel transistor is turned-ON or turned-OFF by input signals from word lines 33 and 34 and a transistor 45 or 46 of the following step is driven by a bit line 50. A P-channel transistor 37 and the N-channel transistor 38 are turned-ON or turned-OFF by output of the transistor 45 or 46 and a potential is supplied to the line 50. The potential is a potential of vss in case the potential of vss is supplied to the turned-ON N-channel transistor of a readout-only storage element, is a potential of vdd in case the potential of vdd is supplied to the N-channel transistor and is decided by the transistor 37 or 38. Accordingly, a current does never flow through the N-channel transistor turned-ON in the state of readout and a power consumption is suppressed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and more particularly to the structure of a read-only memory circuit in a master slice type gate array.

[Prior Art] Current - 1 When configuring a logic including a read-only memory circuit in a master slice type gate array that realizes a dedicated logic by manufacturing the basic cell first and changing the wiring process. , (1) A method of replacing the basic cell with a dedicated basic cell for a read-only memory circuit in which read data is written only in the area of the read-only memory circuit; (2)
) There is a method of writing data by connecting the basic cell and the power supply layer with a metal wiring without using a basic cell for a read-only memory circuit.

When comparing methods (1) and (2), we find that in method (1), the read data of the read-only memory circuit differs depending on the logic of the integrated circuit that constitutes it, and dedicated read data is provided for each logic circuit. A read-only memory circuit area in which the data is written is required. Therefore, it is impossible to realize dedicated logic by changing only the wiring process, and there is no method suitable for gate arrays that is characterized by realizing a dedicated integrated circuit in a short period of time by changing only the wiring process. ,(2
). In the case of (2), a low power supply potential (hereinafter referred to as vs
The basic cell of a master slice type gate array, which writes read data by supplying a high power supply potential (hereinafter referred to as VDD), is usually composed of a Pch transistor and an Nch transistor. Arranged regularly. Therefore, when writing the read data, it is desirable to be able to supply the potential VSS or the potential Vdd to the diffusion region of the transistor regardless of whether it is a Pch transistor or an Nch transistor when configuring a read-only memory circuit.

[Problem to be solved by the invention] However, the potential v in one diffusion region of the Nch transistor
dd, even if the Nch transistor is conductive, the potential of the other diffusion region of the Nch transistor is a potential that is lower than the supplied potential vdd by the threshold potential of the Nch transistor due to the operating principle of the Nch transistor. It only rises to Therefore, current flows and power consumption increases. The same applies to the Pch transistor, and the potential V is applied to one diffusion region of the Pch transistor.
When SS is supplied, even if the Pch transistor becomes conductive, the potential of the other diffusion regions of the Pch transistor is the potential VS.
S increases by the threshold potential of the Pch transistor, current flows, and power consumption increases. Therefore, when constructing a read-only memory circuit, the problem is how to efficiently use the transistors constituting the basic cell and reduce power consumption.

The present invention solves the above-mentioned problems, and provides a method for efficiently using a transistor in a basic cell as a storage element in a read-only memory circuit in a master slice gate array to reduce power consumption. The purpose is to provide.

[Means for Solving the Problems] a) In a master slice type gate array in which basic cells constituting logic are regularly arranged, b) The basic cells have electrically isolated gate electrodes. One or more Pch transistors and one or more Nch transistors
C) the Pch transistor or the Nch transistor alone has a fixed potential in the source region or drain region of the Pch transistor or the Nch transistor as a storage element of a read-only storage circuit; d) the Pch transistor The diffusion region of the transistor or Nch transistor that does not have a fixed potential is connected to the next stage Pch transistor or Nch transistor, and e) the output potential due to the conduction of the Pch transistor or Nch transistor is connected to the next stage Pch transistor or Nch transistor. driving one or more transistors, f) the driven Pch transistor or N of the next stage;
[Embodiment] Fig. 1 shows a gate-separated type Pch transistor including a feedback circuit in which the output potential of the ch transistor becomes an output potential due to conduction of the Pch transistor or the Nch transistor. 11.12.13 in the diagram showing the basic logic of the transistor of a master slice type gate array consisting of a basic cell composed of one Nch transistor and one Nch transistor are the gate electrodes of Pcht-Randisku, and 17.18.19.23 .24
．． 25 is a source diffusion region or a drain diffusion region of a Pch transistor. Also, 14.15.16 is Nc
h At the gate electrode of the transistor, 20.21.22.2
6.27.28 is the source diffusion region or train diffusion region of the Nch transistor.

FIG. 2 shows an example in which a read-only memory circuit is constructed using the conventional method using transistors arranged regularly as shown in FIG. The Pch transistor and the Nch transistor connected to the word lines 29 and 30 (word lines are separated in each transistor, and are similarly separated in FIGS. 3 and 4 below) are used for the readout. Corresponds to one dedicated memory child. 32 is the Pch transistor 43
and the next stage circuit consisting of the Nch transistor 44, and 31 is an output circuit of this circuit. In the circuit configuration shown in FIG. 2, a current flows in the output 49 of the read-only storage element when a potential of VDD is supplied to the Nch transistor and when a potential of VSS is supplied to the Pch transistor.
To reduce current consumption, apply VSS to the Nch transistor.
It is necessary to configure the circuit so as to supply the potential of Vdd to the Pch transistor.

FIG. 3 shows a logic diagram of a read-only memory circuit according to the present invention. 33.34 in FIG. 0 is a word line corresponding to 29.30 in FIG. 2. 35.36.45.46 in Figure 3.
50 correspond to 31, 32, 43, 44, 49 in FIG. 2, respectively. Also.

37 and 38 indicate transistors of the present invention. In FIG.
The hh transistor is turned on or off by the input signal of word $j3133.34 and drives the next stage transistor 45 or 46 by the bit line 50. The output of the transistor turns on or off the Pch transistor 37 and the Nch transistor 38 of the present invention to supply a potential to bit #i50. This potential is a vss potential when a VSS potential is supplied to the Nch transistor of the read-only storage element that is turned on, and a vdd potential when a vdd potential is supplied, and the Pch transistor 37 or the Nch transistor 38. Therefore, regardless of the threshold value of the Nch transistor of the read-only storage element, no current flows through the Nch transistor that is turned on in the read state, and power consumption can be suppressed.

The same applies to the Pch transistor, and the potential VS5,
Even if it is supplied regardless of vdd, no current will flow in the read state.

FIG. 4 shows a logic diagram of a read-only memory circuit using only Nch transistors according to the present invention.

In the figure, 39 is a word line, and 51 is a bit line.

The bit line 51 drives a Pch transistor 47 and an Nch transistor 48, and the output of the transistor is a Pch transistor.
Turns transistor 42 on or off. bit line 51
When becomes the potential of VSS, the Pch transistor is turned off, but there is no problem because the potential of VSS is not affected by the threshold value of the Nchh transistor of the read-only storage element due to the operating principle of the Nch transistor.

In addition, in FIGS. 3 and 4, the transistor of the present invention uses one Pch transistor that holds the potential of vdd, but a plurality of Pch transistors may be used depending on the capability of the read-only recording element. The transistors can be connected in parallel or in series to hold the potential of vdd.

Similarly, the Nch transistor that holds the potential of VSS,
Depending on the capability of the read-only storage element, a plurality of transistors may be used and connected in parallel or in series to hold the potential of VSS.

[Effects of the Invention] As described above, according to the present invention, the regularly arranged transistors in the master slice type gate array can be effectively used regardless of the read data possessed by the read-only memory circuit, and even in the read state. It is possible to suppress the flowing current. Furthermore, by connecting a plurality of Pch transistors for supplying the VDD potential and Nch transistors for supplying the VSS[ potential, the ability of the potential supply transistor can be changed according to the ability of the read-only storage element. have

[Brief explanation of the drawing]

FIG. 1 is a basic logic diagram of a transistor of a gate-separated master slice type gate array. FIG. 2 is a diagram showing an example of a read-only storage circuit constructed using a conventional method. 3 and 4 are logic diagrams of a read-only storage circuit according to the present invention. 11.12, 13...Pch transistor gate 1ti17.18.
19.23.24.25 ... Source diffusion region or drain diffusion region of Pch transistor 14.15.16 ... Gate electrode of Nch transistor 20.21.2
2.26.27.28 ... Source diffusion region or drain diffusion region of Nch transistor 29.30.33.34.39 ... Word line 49.50.51 ... Bit line 43.45.47 ...Pch transistor 44.46.48 ...Nchh transistor 37.42 vd d W level supply Pch transistor 38 . . . vssW level supply supply hh transistor or more 4 +3 +4 Fig. 1 Fig. 2 Fig. 4

Claims (1)

[Scope of Claims] a) In a master slice type gate array in which basic cells constituting logic are arranged regularly, b) One or more of the basic cells have electrically isolated gate electrodes. Pch transistor and one or more Nch transistor
c) the Pch transistor or the Nch transistor alone has a fixed potential in the source region or the drain region of the Pch transistor or the Nch transistor as a storage element of a read-only storage circuit, and d) the Pch transistor or the diffusion region of the Nch transistor that does not have a fixed potential is connected to the next-stage Pch transistor or Nch transistor, and e) the output potential due to conduction of the Pch transistor or Nch transistor f) the driven Pch transistor or N of the next stage;
A master slice type semiconductor integrated circuit device comprising a feedback circuit in which the output potential of the ch transistor becomes the output potential due to conduction of the Pch transistor or the Nch transistor.