JP6618587B2 - Semiconductor device - Google Patents

Description

  The present disclosure relates to a semiconductor memory device, and relates to a configuration for reducing a current during standby.

  Conventionally, SRAM (Static Random Access Memory) has been reduced in current during standby, and only holds data without reading or writing data compared to normal time when reading or writing data. A circuit has been proposed in which the current is reduced by controlling the potential of the source line during standby and lowering the voltage applied to the memory cell.

  In this regard, in Patent Document 1, a power switch transistor connected to a source line of a memory cell and a diode-connected transistor are provided. The transistor of the power switch is controlled so as to be normally conductive and not conductive during standby, and the potential of the source line of the memory cell is controlled by the diode-connected transistor.

  In Patent Document 2, there is no power switch transistor connected to the source line of the memory cell, and only one diode-connected transistor is provided. The transistor is normally turned on to pull down the source line, and at the time of standby, the gate becomes the source potential of the memory cell and is diode-connected to control the potential of the source line of the memory cell.

JP 2004-206745 A JP 2007-150761 A

  However, in the configuration shown in Patent Document 1, since the power switch transistor and the diode-connected transistor for floating the source line of the memory cell are operated independently, it is necessary to secure the area of each transistor. Therefore, the area becomes large.

  In the configuration shown in Patent Document 2, the area can be reduced because the configuration uses only one transistor. However, when the potential of the source line of the memory cell is controlled by diode connection, In order to reduce the current, the transistor size needs to be designed to be small. However, in the transistor size, there is a problem that the transistor size is too small to pull down the source line of the memory cell to the ground side at normal time. Therefore, it is difficult to make both functions compatible with one transistor, and there is a problem that designing the transistor size is very difficult.

  The present disclosure has been made in order to solve the above-described problem, and suppresses the area of the circuit that controls the potential of the source line of the memory cell and holds the data without destroying it during standby. An object of the present invention is to provide a semiconductor memory device that can be easily set to an appropriate potential for reducing leakage current.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  According to one embodiment, a semiconductor memory device includes a memory array including a plurality of static memory cells arranged in a matrix, and a control circuit that controls the memory array. Each static memory cell includes a drive transistor, a transfer transistor, and a load element. The control circuit includes a first switch transistor provided between a source line connected to a source electrode of the driving transistor and a first voltage, and a first switch between the source line and the first voltage. A second switch transistor provided in parallel with the transistor; and a source line potential control circuit that controls the first and second switch transistors to adjust the potential of the source line. The source line potential control circuit conducts the first and second switch transistors to connect the source line and the first voltage during the operation of the static memory cell, and connects the first voltage to the first voltage during standby of the static memory cell. The switch transistor is set to be non-conductive and set so that the gate electrode and the source line of the second switch transistor are connected. The first switch transistor is arranged on one end side of the memory array. The second switch transistor is arranged on the other end side of the memory array located on the opposite side of the one end side of the memory array.

  According to one embodiment, the area of the circuit that controls the potential of the source line of the memory cell is suppressed, and at the time of standby, the data is not destroyed and is easily set to an appropriate potential that reduces the leakage current. Is possible.

It is an external appearance block diagram of the semiconductor memory device based on embodiment. It is a figure explaining the structure of the memory array MA and peripheral circuit based on embodiment. It is a figure explaining the structure of the source line electric potential control circuit based on embodiment. It is a figure explaining the electric potential level of the signal at the time of standby based on embodiment. It is a figure explaining the switch transistor based on the modification 1 of embodiment. It is a figure explaining the layout structure of the memory array based on the modification 1 of embodiment. It is a figure explaining the switch transistor based on the modification 2 of embodiment. It is a figure explaining the layout structure of the memory array based on the modification 2 of embodiment. It is a figure explaining arrangement of drivers 41 and 42 based on modification 2 of an embodiment. It is a figure explaining the structure of the source line electric potential control circuit based on the modification 3 of embodiment. It is a figure explaining the structure of the source line electric potential control circuit based on the modification 4 of embodiment.

  The present embodiment will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated.

FIG. 1 is an external configuration diagram of a semiconductor memory device according to the embodiment.
As shown in FIG. 1, the semiconductor memory device includes a driver & decoder 17, a memory array MA, a control unit 19, and an I / O circuit group 2. The decoder is a simplified version of the address decoder.

  The control unit 19 controls each functional block of the semiconductor memory device. Specifically, the control unit 19 outputs a row address signal to the driver & decoder 17 based on the input of the address signal. The control unit 19 outputs various signals for driving the I / O circuit group 2.

  Memory array MA has a plurality of memory cells arranged in a matrix. Memory cells of the memory array MA are provided so as to be rewritable.

  Driver & decoder 17 drives word lines WL provided corresponding to the memory cell rows of the memory cells arranged in a matrix of memory array MA.

  The I / O circuit group 2 includes a plurality of I / O circuits, and is provided as an input / output circuit that performs data reading or data writing to the memory array MA.

  FIG. 2 is a diagram illustrating the configuration of the memory array MA and peripheral circuits based on the embodiment.

  As shown in FIG. 2, in this example, a configuration of a memory array MA and a source line potential control circuit for adjusting a potential of a source line provided in the memory array MA will be described.

  Memory array MA has a plurality of memory cells MC arranged in a matrix. Each memory cell MC is an SRAM (Static Random Access Memory) cell provided so as to be rewritable. Each memory cell MC is a static memory cell composed of a drive transistor, a transfer transistor, and a load element, which will be described later.

In this example, a memory cell MC of 2 rows and 4 columns is shown as an example.
A plurality of word lines WL are provided corresponding to the memory cell rows of memory array MA.

  Driver & decoder 17 includes a word line driver WD provided corresponding to word line WL.

  The control unit 19 includes various control circuits. In this example, a control circuit & address decoder 20 and a standby control circuit 21 are included.

  The control circuit & address decoder 20 controls a normal time and a standby time and outputs a row address signal obtained by decoding an address signal by the address decoder to the word line driver WD.

  The word line driver WD activates the word line WL selected based on the row address signal.

  The standby control circuit 21 outputs control signals RSB1 and RSB2 in accordance with the control signal RS from the control circuit & address decoder 20, and adjusts the potential of the source line.

  A plurality of bit line pairs BL, / BL are provided corresponding to the memory cell columns of memory array MA. In this example, four memory cell columns are shown. Four bit line pairs provided corresponding to four memory cell columns are provided.

  The I / O circuit 2A is provided for every four memory cell columns arranged in a matrix, and a selection circuit for selecting one of the four columns, a sense amplifier, a write driver, and a bit line precharge circuit Etc.

  The source electrode of each memory cell MC is connected to the source line ARVSS, and a plurality of switch transistors are provided for the source line ARVSS.

  In this example, a plurality of switch transistors are provided between the source line ARVSS and the ground voltage VSS. When the memory cell MC operates, the source line ARVSS is connected to the ground voltage, and when the memory cell MC is on standby, some of the switch transistors connect the gate electrode to the source line ARVSS, and the remaining The switch transistor is set to non-conduction.

  In this example, a first switch transistor 31 and a second switch transistor 32 are provided.

  The first switch transistor 31 and the second switch transistor 32 are each provided in parallel.

FIG. 3 is a diagram illustrating the configuration of the source line potential control circuit based on the embodiment.
As shown in FIG. 3, the source line potential control circuit includes a standby control circuit 21 and first and second switch transistors 31 and 32.

  FIG. 3 shows the configuration of the memory cell MC. The memory cell MC is a six-transistor SRAM cell including two access transistors AT0 and AT1 (transfer transistors), drive transistors NT0 and NT1, and load transistors PT0 and PT1 (load elements).

  Access transistors AT0 and AT1 are electrically connected to the corresponding word line WL. Access transistors AT0 and AT1 conduct in accordance with activated word line WL when data reading or data writing of memory cell MC is executed.

Standby control circuit 21 includes drivers 41 and 42.
Drivers 41 and 42 have an inverter configuration, and driver 41 includes a P-channel MOS transistor 44 and an N-channel MOS transistor 45. Driver 42 includes a P channel MOS transistor 46 and an N channel MOS transistor 47.

  P-channel MOS transistor 44 and N-channel MOS transistor 45 are provided between power supply voltage VDD and ground voltage VSS, and each gate receives control signal RS. The output of the driver 41 is input to the gate of the first switch transistor 31 as the control signal RSB1.

  P-channel MOS transistor 46 and N-channel MOS transistor 47 are provided between power supply voltage VDD and source line ARVSS, and each gate receives control signal RS. The output of the driver 42 is input to the gate of the second switch transistor 32 as the control signal RSB2.

  The first switch transistor 31 is provided between the source line ARVSS and the ground voltage VSS, and the gate thereof receives an input of the control signal RSB1.

  The second switch transistor 32 is provided between the source line ARVSS and the ground voltage VSS, and its gate receives the control signal RSB2.

FIG. 4 is a diagram illustrating the potential level of a signal during standby based on the embodiment.
As shown in FIG. 4, the operation when the control signal RS is raised from the “L” level to the “H” level, that is, the operation during standby will be described.

  The control circuit & address decoder 20 sets the control signal RS to “L” level during normal operation, and sets it to “H” level during standby.

  Drivers 41 and 42 set control signals RSB1 and RSB2 in accordance with control signal RS. Specifically, when control signal RS is at “L” level, P-channel MOS transistors 44 and 46 are rendered conductive and both control signals RSB 1 and RSB 2 are set to “H” level.

  As a result, the potentials of the gates of the first and second switch transistors 31 and 32 are set to the “H” level, so that the first and second switch transistors 31 and 32 become conductive. Therefore, source line ARVSS and ground voltage VSS are electrically coupled.

  When control signal RS is at “H” level, N channel MOS transistor 45 is rendered conductive. As a result, the control signal RSB1 is set to the “L” level, and the gate potential of the first switch transistor 31 is set to the “L” level. Therefore, the electrical coupling between the source line ARVSS and the ground voltage VSS is separated.

  When control signal RS is at “H” level, N channel MOS transistor 47 is rendered conductive. Thereby, the gate of the second switch transistor 32 and the source line ARVSS are electrically coupled. Therefore, the control signal RSB2 is set to the same potential level as the source line ARVSS.

  At this point, the potential of the source line ARVSS is balanced by the leakage current of the memory cell MC and the passing current of the diode-connected second switch transistor 32, and is set to an intermediate potential between the power supply voltage VDD and the ground voltage VSS. Is done. Note that the potential difference between the power supply voltage VDD and the intermediate potential is set to be higher than the voltage at which the memory cell MC can hold data.

  Since the source line ARVSS according to the present embodiment is set to an intermediate potential by the source line potential control circuit during standby, the leakage current can be suppressed. At that time, the potential can be easily adjusted by adjusting the size of the second switch transistor 32 such as the gate length, gate width, and number.

  In the normal mode, the second switch transistor 32 is turned on and the first switch transistor 31 is turned on to lower the source line ARVSS to the ground voltage VSS. Therefore, since the first and second switch transistors 31 and 32 are conductive, it is not necessary to increase the size of the first switch transistor 31 and the area of the transistor can be suppressed. In the standby mode, the first switch transistor 31 is turned off and only the second switch transistor 32 is diode-connected, so that the source potential of the source line ARVSS is adjusted only by the size of the second switch transistor 32. It is possible.

  In this example, the configuration in which at least one first and second switch transistors 31 and 32 are provided in the source line ARVSS as an example has been described. However, the present invention is not limited thereto, and the potential of the source line ARVSS is adjusted. For this purpose, a plurality of first and second switch transistors 31 and 32 may be provided.

<Modification 1>
FIG. 5 is a diagram illustrating a switch transistor according to the first modification of the embodiment.

  As shown in FIG. 5, the first modification has a configuration in which switch transistors are arranged on the upper and lower sides in the column direction of the memory array MA.

  Specifically, the case where the memory array is divided for at least one memory cell column is shown. A source line is provided for each divided memory cell column, and first and second switch transistors 31 and 32 are provided on one end side and the other end side in the column direction of the source line, respectively. In this example, divided memory cell columns MCA0 to MCAn are shown.

  In this example, the case where the memory array is divided for each memory cell column is described. However, the present invention is not limited to this, and the memory array MA can be divided for a plurality of memory cell columns. is there.

With this configuration, charge can be extracted from one end side and the other end side of the source line.
When the switch transistor is provided only on one end side of the source line, it takes time to lower the potential of the source line ARVSS far from the switch transistor to the ground voltage VSS. By pulling down, a difference in the discharge time of charges accumulated in the source line ARVSS hardly occurs, and the operation timing of the memory cell MC can be easily designed.

  Further, since the memory cell columns are repeatedly arranged in the same unit, the potential of the source line ARVSS can be kept constant regardless of the number of memory cell columns.

  FIG. 6 is a diagram illustrating the layout configuration of the memory array based on the first modification of the embodiment.

  As shown in FIG. 6, the case where the switch transistors are laid out at one end and the other end in the column direction is shown as the layout configuration of the memory array.

  Here, as a layout of the memory cell MC, a layout of a six-transistor SRAM cell including access transistors AT0 and AT1 (transfer transistors), drive transistors NT0 and NT1, and load transistors PT0 and PT1 (load elements) is shown. ing.

  Further, first and second switch transistors 31 and 32 are provided adjacent to the memory cell MC.

  The first switch transistor 31 receives a control signal RSB1 at its gate electrode, and three transistor elements having a source electrode connected to the ground voltage VSS and a drain electrode connected to the source line ARVSS may be connected in parallel to each other. It is shown.

  In the second switch transistor 32, two transistor elements having a gate electrode receiving the control signal RSB 2 and having a source electrode connected to the ground voltage VSS and a drain electrode connected to the source line ARVSS may be connected in parallel to each other. It is shown.

  As shown in the configuration, the case where the layout area of the first switch transistor 31 is larger than that of the second switch transistor 32 is shown.

<Modification 2>
FIG. 7 is a diagram illustrating a switch transistor according to the second modification of the embodiment.

  As shown in FIG. 7, the first modification has a configuration in which switch transistors are arranged on the upper and lower sides in the column direction of the memory array MA.

  Specifically, the case where the memory array is divided for at least one memory cell column is shown. A source line is provided for each divided memory cell column, the first switch transistor 31 is provided on one end side in the column direction of the source line, and the second switch transistor 32 is provided on the other end side. is there.

With this configuration, charge can be extracted from one end side and the other end side of the source line.
When the switch transistor is provided only on one end side of the source line, it takes time to lower the potential of the source line ARVSS far from the switch transistor to the ground voltage VSS. By pulling down, a difference in the discharge time of charges accumulated in the source line ARVSS hardly occurs, and the operation timing of the memory cell MC can be easily designed.

  Further, since the memory cell columns are repeatedly arranged in the same unit, the potential of the source line ARVSS can be kept constant regardless of the number of memory cell columns.

  FIG. 8 is a diagram illustrating a layout configuration of a memory array based on the second modification of the embodiment.

  As shown in FIG. 8, a case where switch transistors are laid out at one end and the other end in the column direction is shown as a layout configuration of the memory array.

  In addition, a first switch transistor 31 is provided on one end side in the column direction adjacent to the memory cell MC, and a second switch transistor 32 is provided on the other end side.

  The first switch transistor 31 may receive a control signal RSB1 at its gate electrode, and three transistor elements having a source electrode connected to the ground voltage VSS and a drain electrode connected to the source line ARVSS may be connected in parallel to each other. It is shown.

  In the second switch transistor 32, a case is shown in which the gate electrode receives the control signal RSB2, the source electrode is connected to the ground voltage VSS, and the drain electrode is connected to the source line ARVSS. ing.

  As shown in the configuration, the case where the layout area of the first switch transistor 31 is larger than that of the second switch transistor 32 is shown.

FIG. 9 is a diagram illustrating the arrangement of the drivers 41 and 42 based on the second modification of the embodiment.
As shown in FIG. 9, the driver 41 is provided at one end in the column direction where the first switch transistor 31 is provided, and the driver 42 is the other end in the column direction where the second switch transistor 32 is provided. The case where it is provided on the side is shown.

  As described above, the first switch transistor 31 is arranged on one end side in the column direction of the memory cell column, the second switch transistor 32 is arranged on the other end side, and the source lines ARVSS are connected by the upper layer wiring. In addition, each memory cell is connected via a lower layer wiring provided for each memory cell row. Correspondingly, the drivers 41 and 42 for driving the first and second switch transistors 31 and 32 are arranged on one end side and the other end side in the column direction, respectively, so that the first and second switch transistors are arranged. It is possible to easily design the wiring layout of the control signals RSB1 and RSB2 for controlling. When the first switch transistor is provided on both sides, it is necessary to provide the signal wiring on both sides, but since it is on one side, it is possible to provide the signal wiring only on one side.

  The first switch transistor 31 is disposed between the memory cell MC and the I / O circuit group 2, and the driver 41 is disposed at one end near the I / O circuit group in the column direction of the memory cell column. . Since many signal wirings such as bit lines are required to connect the memory cell MC and the I / O circuit group 2, a driver 41, which is a simple inverter, is connected to one end near the I / O circuit group. By arranging the driver 42 for controlling the transistor 32 so as to be diode-connected at the time of standby, the wiring layout can be easily designed.

<Modification 3>
In the above embodiment, the source line potential control circuit for setting the potential of the source line ARVSS connected to the drive transistors NT0 and NT1 of the memory cell MC has been described, but it is connected to the source side of the load transistors PT0 and PT1. The source line potential control circuit can be similarly applied to the source power supply line to which the power supply voltage VDD is supplied.

  FIG. 10 is a diagram illustrating a configuration of a source line potential control circuit based on Modification 3 of the embodiment.

  As shown in FIG. 10, standby control circuit 21 as a source line potential control circuit further includes an inverter 60, drivers 61 and 64, and first and second power switch transistors 71 and 72.

  Drivers 61 and 64 have an inverter configuration, and driver 61 includes a P-channel MOS transistor 62 and an N-channel MOS transistor 63. Driver 64 includes a P channel MOS transistor 65 and an N channel MOS transistor 66.

  P-channel MOS transistor 65 and N-channel MOS transistor 66 are provided between power supply voltage VDD and ground voltage VSS, and each gate receives an inverted signal of control signal RS via inverter 60. The output of the driver 64 is input to the gate of the first power switch transistor 71 as the control signal RPB1.

  P-channel MOS transistor 62 and N-channel MOS transistor 63 are provided between source power supply line ARVDD and ground voltage VSS, and each gate receives an input of an inverted signal of control signal RS via inverter 60. The output of the driver 61 is input to the gate of the second power switch transistor 72 as the control signal RPB2.

  The first power switch transistor 71 is provided between the power supply voltage VDD and the source power supply line ARVDD, and its gate receives the control signal RPB1.

  The second power switch transistor 72 is provided between the power supply voltage VDD and the source power supply line ARVDD, and its gate receives the control signal RPB2.

  The control circuit & address decoder 20 sets the control signal RS to “L” level during normal operation, and sets it to “H” level during standby.

  Drivers 61 and 64 set control signals RPB1 and RPB2 in accordance with control signal RS. Specifically, when control signal RS is at “L” level, N channel MOS transistors 63 and 66 are rendered conductive, and control signals RPB 1 and RPB 2 are both set to “L” level.

  As a result, the potentials of the gates of the first and second power switch transistors 71 and 72 are set to the “L” level, so that the first and second power switch transistors 71 and 72 become conductive. Therefore, source power supply line ARVDD and power supply voltage VDD are electrically coupled.

  When control signal RS is at “H” level, P channel MOS transistor 65 is rendered conductive. As a result, the control signal RPB1 is set to the “H” level, and the gate potential of the first power switch transistor 71 is set to the “H” level. Therefore, the electrical coupling between the source power supply line ARVDD and the power supply voltage VDD is separated.

  When control signal RS is at “H” level, P channel MOS transistor 62 is rendered conductive. As a result, the gate of the second power switch transistor 72 and the source power line ARVDD are electrically coupled. Therefore, control signal RPB2 is set to the same potential level as source power supply line ARVDD.

  In this respect, the potential of the source power supply line ARVDD is balanced by the leakage current of the memory cell MC and the passing current of the second power switch transistor 72 that is diode-connected, and an intermediate potential between the power supply voltage VDD and the ground voltage VSS. Set to Note that the potential difference between the power supply voltage VDD and the intermediate potential is set to be higher than the voltage at which the memory cell MC can hold data.

  Since the source power supply line ARVDD according to the present embodiment is set to an intermediate potential by the source line potential control circuit during standby, leakage current can be suppressed. At that time, the potential can be easily adjusted by adjusting the size of the second power switch transistor 72 such as the gate length, gate width, and number.

  In the normal mode, the second power supply switch transistor 72 is turned on and the first power supply switch transistor 71 is turned on to raise the source power supply line ARVDD to the power supply voltage VDD. Therefore, since the first and second power switch transistors 71 and 72 are conductive, it is not necessary to increase the size of the first power switch transistor 71 and the area of the transistor can be suppressed. Further, at the time of standby, the first power switch transistor 71 is turned off and only the second power switch transistor 72 is diode-connected, so that only the size of the second power switch transistor 72 is used for the source of the source power line ARVDD. It is possible to adjust the potential.

In addition, about the said structure, it is possible to combine with each modification.
<Modification 4>
In the above embodiment, the method of setting the potential of the source line ARVSS in accordance with the control signal RS that controls the operation during standby has been described. Specifically, a method has been described in which the potential of the source line ARVSS is set to an intermediate potential between the power supply voltage VDD and the ground voltage VSS during standby to reduce leakage current while retaining data.

  On the other hand, depending on the situation of the semiconductor memory device, there may be a case where it is not necessary to hold data.

  In the fourth modification of the embodiment, a method of controlling the potential of the source line when there is no need to hold data will be described.

  FIG. 11 is a diagram illustrating a configuration of a source line potential control circuit based on Modification Example 4 of the embodiment.

  As shown in FIG. 11, the source line potential control circuit according to the fourth modification of the embodiment replaces the driver 42 with a driver 42 # as compared with the source line potential control circuit described in FIG. The difference is that the control signal SD is input. Since other configurations are the same, detailed description thereof will not be repeated.

  Driver 42 # includes a P channel MOS transistor 46 and an N channel MOS transistor 47, an AND circuit 50, an inverter 51, a NOR circuit 52, and an N channel MOS transistor 53.

  P-channel MOS transistor 46 and N-channel MOS transistor 47 are provided between power supply voltage VDD and source line ARVSS. P channel MOS transistor 46 has its gate receiving control signal RS. N channel MOS transistor 47 has its gate receiving an output signal of AND circuit 50. AND circuit 50 outputs an AND logic operation result of control signal RS and control signal SD to the gate of N-channel MOS transistor 47.

  N channel MOS transistor 53 is connected between the gate of N channel MOS transistor 32 and source line ARVSS. N channel MOS transistor 53 has its gate receiving an output signal of NOR circuit 52. The NOR circuit 52 outputs the NOR logic operation result of the inverted signal of the control signal RS via the inverter 51 and the control signal SD to the gate of the N-channel MOS transistor 53.

  The control circuit & address decoder 20 sets the control signal RS to “L” level during normal operation, and sets it to “H” level during standby.

  The control circuit & address decoder 20 sets the control signal SD to the “L” level during normal operation, and sets the control signal SD to the “H” level during shutdown that does not require data retention.

  Drivers 41 and 42 # set control signals RSB1 and RSB2 in accordance with control signal RS. Specifically, when control signal RS is at “L” level, P-channel MOS transistors 44 and 46 are rendered conductive and both control signals RSB 1 and RSB 2 are set to “H” level.

  As a result, the potentials of the gates of the first and second switch transistors 31 and 32 are set to the “H” level, so that the first and second switch transistors 31 and 32 become conductive. Therefore, source line ARVSS and ground voltage VSS are electrically coupled.

  When control signal RS is at “H” level, N channel MOS transistor 45 is rendered conductive. As a result, the control signal RSB1 is set to the “L” level, and the gate potential of the first switch transistor 31 is set to the “L” level. Therefore, the electrical coupling between the source line ARVSS and the ground voltage VSS is separated.

  On the other hand, in the driver 42 #, when the control signal RS is at the “H” level, the operation differs depending on the state of the control signal SD.

  Specifically, when control signal RS is at “H” level and control signal SD is at “L” level, N-channel MOS transistor 53 is rendered conductive. Thereby, the gate of the second switch transistor 32 and the source line ARVSS are electrically coupled. Therefore, the control signal RSB2 is set to the same potential level as the source line ARVSS.

  On the other hand, when control signal RS is at “H” level and control signal SD is at “H” level, N-channel MOS transistor 47 is rendered conductive. As a result, the gate potential of the second switch transistor 32 becomes “L” level and is set to be non-conductive.

  Accordingly, the source line ARVSS is opened, and the memory cell MC cannot hold data.

  With this structure, depending on the state of the semiconductor memory device, current consumption can be further reduced by cutting off the power supply to the source line ARVSS when there is no need to hold data.

  As mentioned above, although this indication was concretely demonstrated based on embodiment, it cannot be overemphasized that this indication is not limited to embodiment, and can be variously changed in the range which does not deviate from the summary.

  DESCRIPTION OF SYMBOLS 1 Memory cell, 2 I / O circuit group, 17 Driver & decoder, 19 Control part, 20 Control circuit & address decoder, 21 Standby control circuit, 31 1st switching transistor, 32 2nd switching transistor, 41, 42, 42 #, 61, 64 driver, 71 first power switch transistor, 72 second power switch transistor.

Claims (8)

A static memory cell comprising a drive transistor, a transfer transistor, and a load element;
A memory array comprising a plurality of static memory cells arranged in each of a plurality of rows and a plurality of columns;
A source line connected to a source electrode of the driving transistor;
A first switching transistor having a first source to which a first voltage is supplied and a first drain connected to the source line;
A second switching transistor having a second source to which the first voltage is supplied and a second drain connected to the source line;
A first driver that is supplied with the first voltage and the second voltage and drives a first gate of the first switching transistor in response to a first control signal;
A second driver that is supplied with the first voltage and is connected to the source line and drives a second gate of the second switching transistor in response to the first control signal;
The first switching transistor is disposed on one end side of the memory array,
The second switching transistor is disposed on the other end side opposite to the one end side of the memory array ,
The first switching transistor and the first driver are disposed on the one end side of the memory array,
The semiconductor device, wherein the second switching transistor and the second driver are disposed on the other end side opposite to the one end side of the memory array . A plurality of pairs of switching transistors including the first switching transistor and the second switching transistor;
A plurality of the source lines;
The memory array includes a plurality of memory cell columns,
2. The semiconductor device according to claim 1, wherein each of the plurality of source lines is supplied to at least one of the plurality of memory cell columns and connected to at least one of the switching transistor pairs. . Each of the memory cell columns is
A plurality of the static memory cells each arranged in a column direction;
The first side;
A second side,
Each of the plurality of source lines is disposed between the first side and the second side of the corresponding memory cell column along the corresponding memory cell column,
The first switching transistor is connected to the corresponding source line on the first side of the corresponding memory cell column;
The semiconductor device according to claim 2, wherein the second switching transistor is connected to the corresponding source line on the second side of the corresponding memory cell column.   The semiconductor device according to claim 1, wherein the second driver drives the second switching transistor in accordance with a combination of the first control signal and the second control signal.   5. The semiconductor device according to claim 4, wherein the second driver controls the second switching transistor to be in a non-conductive state in accordance with the second control signal.   The semiconductor device according to claim 1, wherein the first switching transistor is larger than the second switching transistor. An input / output circuit for reading data from or writing data to the memory array;
The semiconductor device according to claim 1, wherein the first switching transistor is disposed between the memory array and the input / output circuit. A source line potential control circuit;
The source line potential control circuit includes:
When the static memory cell is in an operation mode, the first and second switching transistors are controlled so that the first and second switching transistors are in a conductive state for supplying the first voltage to the source line. ,
When the static memory cell is in a standby mode, the first switching transistor is set to a non-conductive state, the gate electrode of the second switching transistor is connected to the source line, and the second switching transistor The semiconductor device according to claim 1, wherein the semiconductor device is set to be in a diode connection state.

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