JP2010067309A - Semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory device with a small layout area. <P>SOLUTION: In this MRAM, a DL driver 10 for a memory block MB1 is configured with transistors 20 and 21, a size of an access transistor 19 in a memory block MB2 is adjusted, and the driver transistor 21 is arranged in an open area. Further, a DL driver 14 for the memory block MB2 is configured with transistors 22 and 23, a size of the access transistor 19 in the memory block MB1 is made appropriate, and the driver transistor 23 is arranged in an open area. Therefore, the layout area becomes small. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device, and more particularly to a semiconductor device including a memory cell that magnetically stores a data signal.

  In recent years, MRAM (Magnetic Random Access Memory) has attracted attention as a semiconductor memory device capable of storing nonvolatile data with low power consumption (see, for example, Non-Patent Document 1).

  The MRAM includes a plurality of memory cells arranged in a plurality of rows and a plurality of columns, a plurality of word lines provided corresponding to the plurality of rows, a plurality of digit lines provided corresponding to the plurality of rows, respectively. And a plurality of bit lines provided corresponding to a plurality of columns. Each memory cell is connected in series with a magnetoresistive element that stores a data signal according to a resistance level change, and between the corresponding bit line and the reference voltage line, and its gate is connected to the corresponding word line. A connected access transistor. The access transistor is formed on the surface of the semiconductor substrate, the digit line is formed above the access transistor, and the magnetoresistive element is formed above the digit line.

  During a write operation, a magnetizing current is passed through the selected digit line to place the magnetoresistive element of each memory cell corresponding to the digit line in a half-selected state, and the selected bit line is set to the logic of the data signal. A data current is written in the magnetoresistive element of the memory cell arranged at the intersection of the selected digit line and the bit line by supplying a write current in a corresponding direction.

During the read operation, the selected word line is set to the selection level, the access transistor of each memory cell corresponding to the word line is made conductive, and a voltage sufficiently lower than that during the write operation is applied to the selected bit line. Then, the current flowing through the magnetoresistive element of the selected memory cell via the bit line is detected, and the stored data of the magnetoresistive element is read based on the detection result.
2004 Symposium on VLSI Circuits Digest of Technical Papers p.450-453 A 1.2V 1Mbit Embedded MRAM Core with Folded Bit-Line Array Architecture

  However, the conventional MRAM has a problem that a certain size (gate width) is required for a transistor constituting a driver for passing a magnetizing current to the digit line and the bit line, and the layout area is large.

  On the other hand, the layout area of the memory cell is often determined by the magnetoresistive element, its lower electrode, and the digit line, and there is room on the surface of the semiconductor substrate below them. For this reason, an access transistor having a size larger than necessary is provided.

  Therefore, a main object of the present invention is to provide a semiconductor memory device having a small layout area.

  The semiconductor memory device according to the present invention includes two memory blocks. Each memory block is arranged in a plurality of rows and a plurality of columns, each of which corresponds to a plurality of memory cells each storing a data signal magnetically, a plurality of word lines provided corresponding to the plurality of rows, and a plurality of rows respectively. And a plurality of digit lines provided in correspondence with a plurality of columns. Each memory cell is connected in series with a magnetoresistive element that stores a data signal according to a resistance level change, and between the corresponding bit line and the reference voltage line, and its gate is connected to the corresponding word line. A connected access transistor. The semiconductor memory device further includes a write circuit that writes a data signal to a selected memory cell of a plurality of memory cells of the selected memory block of the two memory blocks. The write circuit includes a digit line driver and a bit line driver. The digit line driver is provided corresponding to each memory block, and causes a magnetizing current to flow through a selected digit line among a plurality of digit lines of the corresponding memory block, thereby causing magnetic memory of each memory cell corresponding to the digit line to The resistance element is set to a half-selected state. The bit line driver is provided corresponding to each memory block, and causes a write current in a direction corresponding to the data signal to flow through a selected bit line among the plurality of bit lines of the corresponding memory block. The digit line driver includes a driver transistor. The driver transistor is provided corresponding to each digit line, and is connected in series with the corresponding digit line between the power supply voltage line and the reference voltage line, and becomes conductive when the corresponding memory cell is selected. . Here, the driver transistor corresponding to one of the two memory blocks is disposed in the other memory block, and the driver transistor corresponding to the other memory block is disposed in the one memory block.

  In the semiconductor memory device according to the present invention, the driver transistor corresponding to one memory block of the two memory blocks is arranged in the other memory block, and the driver transistor corresponding to the other memory block is in the one memory block. Is arranged. Therefore, the layout area can be reduced by optimizing the size of the access transistor and disposing the driver transistor in the vacant region.

  FIG. 1 is a block diagram showing a configuration of an MRAM according to an embodiment of the present invention. In FIG. 1, the MRAM includes a memory array 1, a row decoder 2, a column decoder 3, a write circuit 4, and a read circuit 5. Memory array 1 includes two memory blocks MB1 and MB2. Each of memory blocks MB1 and MB2 is arranged in a plurality of rows and a plurality of columns, and each includes a plurality of memory cells that magnetically store data signals.

  The row decoder 2 selects any one of the memory blocks MB1 and MB2 and any one of a plurality of rows of the memory block MB according to the row address signal. The column decoder 3 selects one of a plurality of columns of the memory block MB selected by the row decoder 2 of the memory blocks MB1 and MB2 according to the column address signal.

  Write circuit 4 writes a data signal to a memory cell of memory block MB selected by decoders 2 and 3 during a write operation. Read circuit 5 reads data signals from the memory cells of memory block MB selected by decoders 2 and 3 during a read operation.

  FIG. 2 is a block diagram showing a main part of the MRAM shown in FIG. In FIG. 2, each of memory blocks MB1 and MB2 is arranged in a plurality of rows and a plurality of columns, each of which has a plurality of memory cells MC that magnetically store data signals, and a plurality of memory cells MC respectively provided corresponding to the plurality of rows. It includes a word line WL, a plurality of digit lines DL provided corresponding to a plurality of rows, and a plurality of bit lines BL provided corresponding to a plurality of columns, respectively.

  As shown in FIG. 3, each memory cell MC includes a magnetoresistive element 18 that stores a data signal according to a change in resistance value level, and an access transistor (N-channel MOS transistor) 19. Access transistor 19 has its gate connected to corresponding word line WL, its source connected to the line of ground voltage VSS, and its drain connected to corresponding bit line BL via magnetoresistive element 18.

  A DL driver 10, BL drivers 11, 12, and WL driver 13 are provided corresponding to the memory block MB1, and a DL driver 14, BL drivers 15, 16, and WL driver 17 are provided corresponding to the memory block MB2. The DL drivers 10 and 14 and the BL drivers 11, 12, 15, and 16 are included in the write circuit 4 of FIG. 1, and the WL drivers 13 and 17 are included in the read circuit 5 of FIG.

  The DL driver 10 is activated in response to the selection of the corresponding memory block MB1 by the row decoder 2 during the write operation, and causes the magnetizing current to flow through the digit line DL of the row selected by the row decoder 2. The magnetoresistive element 18 of each memory cell MC corresponding to the digit line DL is set to a half-selected state.

  The DL driver 14 is activated in response to the selection of the corresponding memory block MB2 by the row decoder 2 during the write operation, and causes the magnetizing current to flow through the digit line DL of the row selected by the row decoder 2, The magnetoresistive element 18 of each memory cell MC corresponding to the digit line DL is set to a half-selected state.

  The BL drivers 11 and 12 are activated in response to selection of the corresponding memory block MB1 by the row decoder 2 during the write operation, and the logic of the write data signal is applied to the bit line BL selected by the column decoder 3. A data signal is written to the magnetoresistive element 18 corresponding to the bit line BL among the plurality of magnetoresistive elements 18 in a half-selected state by passing a current in a direction corresponding to the current.

  The BL drivers 15 and 16 are activated in response to the selection of the corresponding memory block MB2 by the row decoder 2 during the write operation, and the logic of the write data signal is applied to the bit line BL selected by the column decoder 3. A data signal is written to the magnetoresistive element 18 corresponding to the bit line BL among the plurality of magnetoresistive elements 18 in a half-selected state by passing a current in a direction corresponding to the current.

  During the read operation, the WL drivers 13 and 17 set the selected word line WL of the memory block MB selected by the row decoder 2 to the “H” level of the selection level, and each memory cell MC corresponding to the word line WL The access transistor 19 is turned on. The read circuit 5 detects the current flowing from the bit line BL selected by the column decoder 3 to the line of the ground voltage VSS, and reads the data stored in the magnetoresistive element 18 of the selected memory cell MC based on the detection result. .

  3 and 4 are diagrams showing configurations and layouts of the memory blocks MB1 and MB2 and the DL drivers 10 and 14, respectively. 3 and 4, each of memory blocks MB1 and MB2 includes memory cells MC in 4 rows and 4 columns. Actually, each of the memory blocks MB1 and MB2 includes a large number of memory cells MC, but in order to simplify the drawing, memory cells MC of 4 rows and 4 columns are shown.

  A word line WL, a digit line DL, a source line SL, an auxiliary wiring AL, and a gate line GL are provided corresponding to each row, and a bit line BL is provided corresponding to each column. One end of each digit line DL of the memory block MB1 receives the power supply voltage VDD1, and the other end is connected to the auxiliary wiring AL of the corresponding row of the memory block MB2. One end of each digit line DL of the memory block MB2 receives the power supply voltage VDD1, and the other end is connected to the auxiliary wiring AL of the corresponding row of the memory block MB1.

  Each source line SL receives ground voltage VSS. In each column, odd-numbered memory cells MC and even-numbered memory cells MC are grouped and share even-numbered source lines SL. The gate of the access transistor 19 of each memory cell MC is connected to the corresponding word line WL, its drain is connected to the bit line BL via the magnetoresistive element 18, and its source is connected to the corresponding source line SL.

  The DL driver 10 includes a driver transistor (N channel MOS transistor) 20 and a plurality (two in the figure) of driver transistors (N channel MOS transistors) 21 provided corresponding to each row. The DL driver 14 includes a driver transistor (N-channel MOS transistor) 22 and a plurality (two in the drawing) of driver transistors (N-channel MOS transistors) 23 provided corresponding to each row.

  Driver transistor 20 is arranged in region A1 on the memory block MB1 side between memory blocks MB1 and MB2. Driver transistor 20 has its drain connected to the other end of corresponding digit line DL of memory block MB1, its source receiving ground voltage VSS, and its gate connected to corresponding gate line GL of memory block MB2.

  Driver transistor 21 is arranged in memory block MB2. Two driver transistors 21 in each row are arranged in the first and third columns, respectively. In each column, odd-numbered driver transistors 21 and even-numbered driver transistors 21 are grouped and share an odd-numbered source line SL. Driver transistor 21 has a drain connected to corresponding auxiliary line AL, a source connected to corresponding source line SL, and a gate connected to corresponding gate line GL.

  Note that the resistance value of the source line SL can be reduced by connecting two adjacent source lines SL at a plurality of locations. In this case, it is preferable that the source lines SL are connected to each other by a wiring that is orthogonal to the source line SL and is formed of a wiring layer different from the source line SL.

  When one of the plurality of gate lines GL of the memory block MB2 is set to the selection level “H” level, the driver transistors 20 and 21 corresponding to the gate line GL are turned on. Thereby, a magnetizing current flows from the line of the power supply voltage VDD1 to the line of the ground voltage VSS via the digit line DL and the driver transistors 20 and 21 of the memory block MB1 corresponding to the gate line GL.

  The driver transistor 22 is arranged in the area A2 on the memory block MB2 side between the memory blocks MB1 and MB2. Driver transistor 22 has its drain connected to the other end of corresponding digit line DL of memory block MB2, its source receiving ground voltage VSS, and its gate connected to corresponding gate line GL of memory block MB1.

  Driver transistor 23 is arranged in memory block MB1. Two driver transistors 23 in each row are arranged in the first and third columns, respectively. In each column, the odd-numbered driver transistors 23 and the even-numbered driver transistors 23 are grouped and share an odd-numbered source line SL. The drain of driver transistor 23 is connected to corresponding auxiliary line AL, its source is connected to corresponding source line SL, and its gate is connected to corresponding gate line GL.

  When one of the plurality of gate lines GL of the memory block MB1 is set to the “H” level of the selection level, the driver transistors 22 and 23 corresponding to the gate line GL are turned on. As a result, a magnetizing current flows from the line of the power supply voltage VDD1 to the line of the ground voltage VSS via the digit line DL and the driver transistors 22 and 23 of the memory block MB2 corresponding to the gate line GL.

  FIG. 5 is a circuit diagram showing the configuration of the BL drivers 11 and 12. In FIG. 5, the BL driver 11 includes an inverter 25 provided corresponding to each bit line BL. Inverter 25 includes a P channel MOS transistor 26 and an N channel MOS transistor 27. P channel MOS transistor 26 is connected between a line of power supply voltage VDD2 and one end of corresponding bit line BL, and has a gate receiving signal φ1. N-channel MOS transistor 27 is connected between one end of corresponding bit line BL and the line of ground voltage VSS, and the gate thereof receives signal φ1.

  The BL driver 12 includes an inverter 28 provided corresponding to each bit line BL. Inverter 28 includes a P channel MOS transistor 29 and an N channel MOS transistor 30. P channel MOS transistor 29 is connected between the line of power supply voltage VDD2 and the other end of corresponding bit line BL, and has its gate receiving signal φ2. N channel MOS transistor 30 is connected between the other end of corresponding bit line BL and the line of ground voltage VSS, and has its gate receiving signal φ2.

  During standby, signals φ1 and φ2 are both at the “H” level. As a result, transistors 26 and 29 are turned off, transistors 27 and 30 are turned on, and each bit line BL is held at the “L” level.

  When the write data signal is at “H” level during the write operation, for example, signal φ1 of the selected column is lowered to “L” level. As a result, transistor 26 in that column becomes conductive and transistor 27 becomes nonconductive, and writing is performed from the line of power supply voltage VDD2 to the line of ground voltage VSS via transistor 26, bit line BL, and N-channel MOS transistor 30. Current flows.

  When the write data signal is at “L” level, for example, signal φ2 of the selected column is lowered to “L” level. As a result, transistor 29 in that column becomes conductive and transistor 30 becomes nonconductive, and writing is performed from the line of power supply voltage VDD2 to the line of ground voltage VSS via transistor 29, bit line BL, and N-channel MOS transistor 27. Current flows. The BL drivers 15 and 16 have the same configuration as the BL drivers 11 and 12, respectively.

  6A is a diagram showing a layout of four memory cells MC and two N-channel MOS transistors 23 in the memory block MB1, and FIG. 6B is a VIB-VIB line in FIG. 6A. It is sectional drawing. 6A and 6B, two gate lines GL and two word lines WL are formed in parallel on the surface of the silicon substrate 31. A gate oxide film (not shown) is formed between each of the gate line GL and the word line WL and the surface of the silicon substrate 31. Both the gate line GL and the word line WL extend in the Y direction.

  6A, an impurity diffusion region having a predetermined size is formed using the two gate lines GL as a mask. The impurity diffusion region between the two gate lines GL becomes the source S of the two N-channel MOS transistors 23, and the impurity diffusion region on both sides becomes the drain D of the two N-channel MOS transistors 23.

  In each of the upper right end and the lower end on the right side in FIG. 6A, an impurity diffusion region of a predetermined size is formed using two word lines WL as a mask. The impurity diffusion region between the two word lines WL becomes the source S of the two N channel MOS transistors 19, and the impurity diffusion region on both sides becomes the drain D of the two N channel MOS transistors 19.

  A source line SL is formed above the sources S of the two transistors 23, and the source line SL is connected to the sources S of the two transistors 23 via the contact holes CH. A source line SL is formed above the sources S of the two transistors 19, and the source line SL is connected to the sources S of the two transistors 19 through contact holes CH.

  An auxiliary wiring AL is formed above each source line SL. Each auxiliary wiring AL is connected to the drain of the corresponding transistor 23 through a contact hole CH. A digit line DL is formed above each auxiliary line AL. 6A and 6B, a rectangular electrode EL is formed from above the drain D of each transistor 19 on the left side to above the digit line DL on the left side. 6A and 6B, a rectangular electrode EL is formed from above the drain D of each transistor 19 on the right side to above the right digit line DL. In each region where the electrode EL and the digit line DL overlap each other, the magnetoresistive element 18 is formed on the electrode EL. The magnetoresistive element 18 is formed such that a magnetic field is generated in the hard axis direction of the magnetoresistive element 18 when a magnetizing current is passed through the digit line DL. A bit line BL is formed on each of the two magnetoresistive elements 18 arranged in the X direction.

  When a magnetizing current is passed through the selected digit line DL, the magnetoresistive element 18 thereabove is put in a half-selected state. When a write current is passed through the selected bit line BL, a data signal is written to the magnetoresistive element 18 in the half-selected state below it. When the selected word line WL is set to the “H” level, the transistor 19 is turned on, and the bit line BL to which the read voltage is applied from the magnetoresistive element 18, electrode EL, contact hole CH, and the transistor 19 through the source line SL. A current having a value corresponding to the resistance value of the magnetoresistive element 18 flows. When the selected gate line GL is set to the “H” level, the transistor 23 becomes conductive, and a magnetizing current flows from the line of the power supply voltage VDD 2 to the source line SL through the digit line DL, the auxiliary wiring AL, and the transistor 23 of the memory block MB 2 Flowing.

  7 and 8 are circuit diagrams showing comparative examples of the embodiment, and are compared with FIGS. 3 and 4, respectively. 7 and 8, DL driver 10 includes a driver transistor (N-channel MOS transistor) 32 provided corresponding to each row. Driver transistor 32 is arranged in area A1 on the memory block MB1 side between memory blocks MB1 and MB2. Driver transistor 32 has its drain connected to the other end of corresponding digit line DL of memory block MB1, its source receiving ground voltage VSS, and its gate connected to gate line GL.

  When the selected gate line GL is set to “H” level, the N-channel MOS transistor 32 corresponding to the gate line GL becomes conductive. As a result, a magnetizing current flows from the line of power supply voltage VDD1 to the line of ground voltage VSS via digit line DL and N-channel MOS transistor 32.

  The DL driver 14 includes a driver transistor (N-channel MOS transistor) 33 provided corresponding to each row. Driver transistor 33 is arranged in area A2 on the memory block MB2 side between memory blocks MB1 and MB2. Driver transistor 33 has its drain connected to the other end of corresponding digit line DL of memory block MB2, its source receiving ground voltage VSS, and its gate connected to gate line GL.

  When the selected gate line GL is set to “H” level, the N-channel MOS transistor 33 corresponding to the gate line GL becomes conductive. As a result, a magnetizing current flows from the line of the power supply voltage VDD1 to the line of the ground voltage VSS via the digit line DL and the N-channel MOS transistor 33.

  FIG. 9A is a diagram showing a layout of four memory cells MC in the memory block MB1, and FIG. 9B is a cross-sectional view taken along the line IXB-IXB in FIG. 9A. 9A and 9B, two word lines WL are formed in parallel on the surface of the silicon substrate 31. A gate oxide film (not shown) is formed between each word line WL and the surface of the silicon substrate 31. The word line WL extends in the Y direction.

  In each of the upper right and lower right regions in FIG. 9A, impurity diffusion regions of a predetermined size are formed using the two word lines WL as a mask. The impurity diffusion region between the two word lines WL becomes the source S of the two N channel MOS transistors 19, and the impurity diffusion region on both sides becomes the drain D of the two N channel MOS transistors 19. A source line SL is formed above the sources S of the two transistors 19, and the source line SL is connected to the sources S of the two transistors 19 through contact holes CH.

  One digit line DL is formed above each source line SL. Another digit line DL is formed in the left region in FIG. A rectangular electrode EL is formed from above the drain D of each left transistor 19 in FIGS. 9A and 9B to above the left digit line DL. A rectangular electrode EL is formed from above the drain D of the right transistor 19 in FIGS. 9A and 9B to above the right digit line DL. In each region where the electrode EL and the digit line DL overlap each other, the magnetoresistive element 18 is formed on the electrode EL. A bit line BL is formed on each of the two magnetoresistive elements 18 arranged in the X direction.

  In this comparative example, the N-channel MOS transistors 32 and 33 of the DL drivers 10 and 14 need a certain size (gate width), and the layout area of the DL drivers 10 and 14 is large.

  On the other hand, the layout area of the memory cell MC is often determined by the magnetoresistive element 18, the electrode EL, and the digit line DL, and there is room on the surface of the silicon substrate 31 below them. For this reason, an access transistor 19 having a size larger than necessary is provided.

  On the other hand, in the present invention, the N-channel MOS transistor 32 is divided into the N-channel MOS transistor 20 and the plurality of N-channel MOS transistors 21, the size of the access transistor 19 in the memory block MB2 is optimized, and a plurality of spaces are provided in the free space. An N channel MOS transistor 21 is arranged. Further, N channel MOS transistor 33 is divided into N channel MOS transistor 22 and a plurality of N channel MOS transistors 23, the size of access transistor 19 in memory block MB1 is optimized, and a plurality of N channel MOS transistors 23 are arranged in the vacant space. Arranged.

  Therefore, the size of N channel MOS transistors 20 and 22 is sufficiently smaller than the size of N channel MOS transistors 32 and 33. Therefore, according to the present invention, the layout area of the DL drivers 10 and 14 can be reduced, and consequently the layout area of the MRAM can be reduced.

  In this embodiment, the DL driver 10 is composed of the transistor 20 and the plurality of transistors 21, but the transistor 20 may be omitted if a sufficient magnetizing current can be passed only by the plurality of transistors 21. Similarly, the DL driver 14 may be configured by only a plurality of transistors 23 without the transistor 22. In this case, since the regions A1 and A2 in which the transistors 20 and 22 are disposed are not necessary, the layout area can be further reduced.

  Since driver transistors 20 to 23 are formed of MOS transistors (N-channel MOS transistors) having the same conductivity type as access transistor 19, transistors 19 to 23 can be arranged in wells having the same conductivity type. The interval of 23 can be reduced.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

It is a block diagram which shows the structure of MRAM by one embodiment of this invention. It is a block diagram which shows the principal part of MRAM shown in FIG. FIG. 3 is a circuit diagram showing a partial configuration of a memory block and a DL driver shown in FIG. 2. FIG. 3 is a circuit diagram showing a configuration of a remaining part of the memory block and DL driver shown in FIG. 2. FIG. 3 is a circuit diagram illustrating a configuration of a BL driver illustrated in FIG. 2. FIG. 4 is a diagram showing a layout of memory cells and transistors shown in FIG. 3. It is a circuit diagram which shows the structure of a part of memory block and DL driver of the comparative example of embodiment. FIG. 8 is a circuit diagram showing a configuration of the remaining part of the memory block and DL driver shown in FIG. 7. FIG. 8 is a diagram showing a layout of memory cells and transistors shown in FIG. 7.

Explanation of symbols

  1 memory array, 2 row decoder, 3 column decoder, 4 write circuit, 5 read circuit, 10, 14 DL driver, 11, 12, 15, 16 BL driver, 13, 17 WL driver, 18 magnetoresistive element, 19 access Transistor, 20-23, 32, 33 Driver transistor, 25, 28 Inverter, 26, 29 P channel MOS transistor, 27, 30 N channel MOS transistor, 31 Silicon substrate, A1, A2 region, AL auxiliary wiring, BL bit line, CH contact hole, D drain, DL digit line, EL electrode, GL gate line, MB1, MB2 memory block, MC memory cell, S source, SL source line, WL word line.

Claims (1)

A semiconductor memory device,
With two memory blocks,
Each memory block is arranged in a plurality of rows and a plurality of columns, each storing a plurality of memory cells magnetically storing data signals, a plurality of word lines provided corresponding to the plurality of rows, and the plurality of rows, respectively. A plurality of digit lines provided corresponding to the plurality of bit lines, and a plurality of bit lines provided corresponding to the plurality of columns, respectively.
Each memory cell is connected in series with a magnetoresistive element that stores a data signal according to a change in resistance value, a corresponding bit line and a reference voltage line, and a gate thereof corresponding to the corresponding word line And an access transistor connected to
And a write circuit for writing a data signal to the selected memory cell of the plurality of memory cells of the selected memory block of the two memory blocks,
The writing circuit includes:
A magnetoresistive element of each memory cell corresponding to the digit line is provided corresponding to each memory block, and a magnetizing current is passed through a selected digit line of the plurality of digit lines of the corresponding memory block. A digit line driver to be half-selected,
A bit line driver that is provided corresponding to each memory block and that causes a write current in a direction corresponding to the data signal to flow through a selected bit line of the plurality of bit lines of the corresponding memory block;
The digit line driver is provided corresponding to each digit line, connected in series with a corresponding digit line between a power supply voltage line and the reference voltage line, and in response to selection of a corresponding memory cell. A driver transistor that conducts
The driver transistor corresponding to one memory block of the two memory blocks is arranged in the other memory block, and the driver transistor corresponding to the other memory block is arranged in the one memory block. A semiconductor memory device.

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