JP2019012584A5

JP2019012584A5 -

Info

Publication number: JP2019012584A5
Application number: JP2018154647A
Authority: JP
Filing date: 2018-08-21
Publication date: 2019-04-25
Anticipated expiration: 2034-10-31

Claims

A static memory cell comprising a drive transistor, a transfer transistor, and a load element;
A memory array comprising a plurality of static memory cells arranged in each of a plurality of rows and a plurality of columns ;
A source line connected to the source electrode of the drive transistor;
A first switching transistor having a first source to which a first voltage is supplied, and a first drain connected to the source line;
A second switching transistor having a second source to which the first voltage is supplied, and a second drain connected to the source line;
A first driver supplied with the first voltage and the second voltage and driving a first gate of the first switching transistor according to a first control signal;
A second driver supplied with the first voltage and connected to the source line and driving a second gate of the second switching transistor in accordance with the first control signal;
The first switching transistor is disposed at one end of the memory array,
The semiconductor device, wherein the second switching transistor is disposed on the other end side opposite to the one end side of the memory array .

A plurality of switching transistor pairs each including the first switching transistor and the second switching transistor;
Have a plurality of said source lines,
The memory array includes a plurality of memory cell strings,
The semiconductor device according to claim 1, wherein each of the plurality of source lines is supplied to at least one of the plurality of memory cell columns and connected to at least one of the pair of switching transistors. .

Each of the memory cell columns is
A plurality of the static memory cells each arranged in the column direction;
On the first side,
With the second side,
Each of the plurality of source lines is disposed along the corresponding memory cell column between the first side and the second side of the corresponding memory cell column.
The first switching transistor is connected to the corresponding source line at the first side of the corresponding memory cell column,
The semiconductor device according to claim 2, wherein the second switching transistor is connected to the corresponding source line at the second side of the corresponding memory cell column.

The semiconductor device according to claim 1, wherein the second driver drives the second switching transistor in accordance with a combination of the first control signal and the second control signal.

The semiconductor device according to claim 4, wherein the second driver controls the second switching transistor to be in a non-conductive state in response to the second control signal.

The semiconductor device according to claim 1, wherein the first switching transistor is larger than the second switching transistor.

The memory array further includes an input / output circuit that reads data from or writes data to the memory array,
The semiconductor device according to claim 1, wherein the first switching transistor is disposed between the memory array and the input / output circuit.

It further has a source line potential control circuit,
The source line potential control circuit
When the static memory cell is in the operation mode, the first and second switching transistors are controlled such that the first and second switching transistors are in a conductive state for supplying the second voltage to the source line. ,
When the static memory cell is in the standby mode, the first switching transistor is set to the non-conductive state, and the gate electrode of the second switching transistor is connected to the source line, and the second switching transistor is The semiconductor device according to claim 1, wherein the semiconductor device is set to be in a diode connection state.

The first switching transistor and the first driver are disposed at the one end of the memory array,
The semiconductor device according to claim 1, wherein the second switching transistor and the second driver are disposed on the other end side opposite to the one end side of the memory array.