JP2013186926A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve a static noise margin while coping with the miniaturization of memory cells and the reduction in power supply voltage.SOLUTION: When a threshold is lower in a drive transistor D2 than a drive transistor D1, a first cell potential control unit 8 controls a first cell potential of the drive transistor D2 so that a hot carrier is injected into the drive transistor D2, and when the hot carrier is injected into the drive transistor D2, '1' is stored in a storage node Nt and '0' is stored in a storage node Nc.

Description

  Embodiments described herein relate generally to a semiconductor memory device.

  In order to improve the degree of integration of semiconductor memory devices, the size of transistors including memory cells has been reduced. In addition, the threshold value of the transistor also decreases in response to the decrease in power supply voltage. As a result, the threshold variation of the transistors constituting the memory cell increases, and some memory cells have insufficient static noise margins. If the static noise margin is not sufficient, the data held in the memory cell may be inverted when data is written to or read from the memory cell.

JP 2010-182344 A

  An object of one embodiment of the present invention is to provide a semiconductor memory device capable of improving a static noise margin while coping with miniaturization of memory cells and a decrease in power supply voltage.

  According to the semiconductor memory device of the embodiment, the memory cells provided with the first storage node and the second storage node in which data are stored complementarily are arranged in a matrix in the row direction and the column direction, The potential of the first storage node is based on the word line for selecting the memory cell for each row, the first and second bit lines for selecting the memory cell for each column, and the potential of the second storage node. The first load transistor for pulling up the first storage transistor, the first drive transistor for pulling down the potential of the first storage node based on the potential of the second storage node, and the potential of the first storage node Based on the second load transistor that pulls up the potential of the second storage node and the potential of the second storage node based on the potential of the first storage node. Based on the potential of the second drive transistor for pulling down, the first transmission transistor for connecting the first storage node and the first bit line based on the potential of the word line, and the potential of the word line A second transmission transistor connecting the second storage node and the second bit line, a first cell potential of the first driving transistor, and a first cell potential of the second driving transistor, A first cell potential control unit that individually controls the first cell potential control unit.

FIG. 1 is a block diagram showing a schematic configuration of the semiconductor memory device according to the first embodiment. FIG. 2 is a circuit diagram showing a configuration example of the memory cell MC of FIG. FIG. 3 is a plan view showing a layout configuration example of the memory cell MC of FIG. FIG. 4 is a block diagram showing a method for switching the source potential of the semiconductor memory device of FIG. FIG. 5 is a diagram showing the voltage level of each part of the semiconductor memory device according to the embodiment of FIG. FIG. 6 is a block diagram showing a schematic configuration of the semiconductor memory device according to the second embodiment. FIG. 7 is a diagram showing voltage levels of the respective parts of the semiconductor memory device according to the second embodiment. FIG. 8 is a block diagram showing a schematic configuration of the semiconductor memory device according to the third embodiment. FIG. 9 is a block diagram showing a method for switching the source potential of the semiconductor memory device according to the third embodiment. FIG. 10 is a diagram showing voltage levels of the respective parts of the semiconductor memory device according to the third embodiment. FIG. 11 is a diagram showing voltage levels of the respective parts of the semiconductor memory device according to the fourth embodiment.

  The semiconductor memory device according to the embodiment will be described below with reference to the drawings. Note that the present invention is not limited to these embodiments.

(First embodiment)
FIG. 1 is a block diagram showing a schematic configuration of the semiconductor memory device according to the first embodiment.
In FIG. 1, the semiconductor memory device includes a memory cell array 1, a timing controller 2, a row decoder 3, a word line driver 4, a column decoder 5, a column selector 6, a read / write circuit 7, and a first cell potential controller 8. Is provided.

  Here, in the memory cell array 1, memory cells MC are arranged in a matrix in the row direction and the column direction. The memory cell MC can store data complementarily, and for example, an SRAM cell can be used. The memory cell array 1 is provided with word lines wl_0 to wl_m (m is a positive integer) for selecting rows of the memory cells MC for each row, and bit lines blt_0 to blt_k for selecting columns of the memory cells MC. blc_0 to blc_k (k is a positive integer) are provided for each column.

FIG. 2 is a circuit diagram showing a configuration example of the memory cell MC of FIG.
In FIG. 2, the memory cell MC is provided with a pair of drive transistors D1, D2, a pair of load transistors L1, L2, and a pair of transmission transistors F1, F2. As the load transistors L1 and L2, P-channel field effect transistors, drive transistors D1 and D2, and N-channel field effect transistors can be used as the transmission transistors F1 and F2.

  The drive transistor D1 and the load transistor L1 are connected in series to constitute a CMOS inverter, and the drive transistor D2 and the load transistor L2 are connected in series to constitute a CMOS inverter. A flip-flop is configured by cross-coupling the outputs and inputs of the pair of CMOS inverters. The word line wl is connected to the gates of the transmission transistors F1 and F2.

  Here, the connection point between the drain of the drive transistor D1 and the drain of the load transistor L1 constitutes the storage node Nt, and the connection point of the drain of the drive transistor D2 and the drain of the load transistor L2 constitutes the storage node Nc. it can.

  The bit line blt is connected to the storage node Nt via the transmission transistor F1. The bit line blc is connected to the storage node Nc via the transmission transistor F2. The sources of the load transistors L1 and L2 are connected to the second cell potential VDD. The second cell potential VDD can be set to a cell power supply potential, for example. The source of the driving transistor D1 is connected to the first cell potential VSS1, and the source of the driving transistor D2 is connected to the first cell potential VSS2. These first cell potentials VSS1 and VSS2 can be set independently. Further, the N well potential of the load transistors L1 and L2 can be set to Vnw, and the P well potential of the drive transistors D1 and D2 can be set to Vpw.

  In FIG. 1, the row decoder 3 can select the word lines wl_0 to wl_m that perform row selection of the memory cell MC based on the row address. The word line driver 4 can drive the word lines wl_0 to wl_m selected by the row decoder 3.

  The column decoder 5 can select the bit lines blt_0 to blt_k and blc_0 to blc_k that perform column selection of the memory cell MC based on the column address. The column selector 6 can connect the bit lines blt_0 to blt_k and blc_0 to blc_k selected by the column decoder 5 to the read / write circuit 7. The read / write circuit 7 can read data stored in the memory cell MC and write data to the memory cell MC. As the read circuit, a sense amplifier that detects data stored in the memory cell MC based on signals read from the memory cell MC onto the bit lines blt_0 to blt_k and blc_0 to blc_k can be used. . As the write circuit, a write amplifier that drives the bit lines blt_0 to blt_k and the bit lines blc_0 to blc_k in a complementary manner according to write data can be used.

  The first cell potential control unit 8 can individually control the first cell potential VSS1 of the driving transistor D1 and the first cell potential VSS2 of the driving transistor D2. For example, if the drive transistor D2 has a lower threshold value than the drive transistor D1, the first cell potential control unit 8 controls the first cell potential VSS2 so that hot carriers are injected into the drive transistor D2. Can do. The timing control unit 2 can control the timing for operating the row decoder 3, the word line driver 4, the column decoder 5, the column selector 6, the read / write circuit, and the first cell potential control unit 8.

FIG. 3 is a plan view showing a layout configuration example of the memory cell MC of FIG.
In FIG. 3, the drive transistor D1, the load transistor L1, and the transmission transistor F1 are arranged so as to be point-symmetric with respect to the drive transistor D2, the load transistor L2, and the transmission transistor F2. That is, when the driving transistor D1, the load transistor L1, and the transmission transistor F1 are rotated by 180 ° around the center of point symmetry, the driving transistor D2, the load transistor L2, and the transmission transistor F2 can be overlapped.

  The first wiring for setting the first cell potential VSS1 and the second wiring for setting the first cell potential VSS2 are separated, and the first wiring and the second wiring are in parallel with the word line wl. Can be arranged. The third wiring for setting the second cell potential VDD can be arranged in parallel to the bit lines blt and blc.

  Here, the layout of the drive transistors D1, D2, load transistors L1, L2, and transmission transistors F1, F2 is the same even when the first cell potentials VSS1, VSS2 are set independently. Can be set equal to

  In FIG. 2, it is assumed that the threshold values of the drive transistors D1 and D2 of the memory cell MC vary, and the drive transistor D2 has a lower threshold value than the drive transistor D1.

  In this case, '1' is written to the storage node Nt of the selected cell via the read / write circuit 7 and '0' is written to the storage node Nc of the selected cell. Thereafter, the bit line blt is set to a high level (for example, 1 V) via the read / write circuit 7 and the bit line blc is set to a low level (for example, 0 V). Further, the word line wl of the selected row is set to a high level (for example, 1 V) via the word line driver 4 and the transmission transistors F1 and F2 are turned on.

  Then, the first cell potential VSS2 is raised from the reference potential to a high potential (for example, 3V) while the first cell potential VSS1 is set to the reference potential (for example, 0V) via the first cell potential control unit 8. Here, the second cell potential VDD can be set to a cell power supply potential (for example, 1 V). Further, the P well potential Vpw can be set to a lower potential (for example, −4 V) than the first cell potential VSS1.

  At this time, since “1” is written in the storage node Nt, the driving transistor D2 is turned on. Further, since the bit line blc is set to a low level (for example, 0 V), the drain potential of the driving transistor D2 is lowered. For this reason, when the first cell potential VSS2 is raised to a high potential, the source potential of the drive transistor D2 rises, and a high voltage is applied between the source and the channel of the drive transistor D2, and thus the drive transistor D2 Hot carriers are generated on the source side, and the hot carriers are trapped in the gate insulating film of the driving transistor D2. For this reason, the threshold value of the drive transistor D2 increases, and the variation in threshold value between the drive transistors D1 and D2 can be reduced.

  Further, when the threshold value of the drive transistor D2 is lower than that of the drive transistor D1, the threshold value of the drive transistor D2 is increased to read or write to the selected cell specified by the selected row and the selected column. The read disturb and the write disturb of the non-selected cells connected to the selected row and the non-selected column can be reduced while suppressing the decrease in the cell current.

FIG. 4 is a block diagram showing a method for switching the source potential of the semiconductor memory device of FIG.
4, the source power source of the drive transistor D1 of the first memory cell MC in FIG. 2 is the source of the drive transistor D1 of the second memory cell MC adjacent to the first memory cell MC in one column direction. Shared with the power supply, the source power supply of the drive transistor D2 of the first memory cell M is shared with the source power supply of the drive transistor D2 of the third memory cell MC adjacent to the first memory cell MC in the other column direction. Has been.

  Here, the memory cells specified by the selected row and the selected column are MCs, the memory cells connected to the selected row and the non-selected column are MCr, and the memory cell adjacent to the memory cell MCs in one column direction is MCc1, A memory cell adjacent to the memory cell MCs in the other column direction is MCc0, and a memory cell connected to the non-selected row and the non-selected column is MCx.

  In each memory cell MCs, MCr, MCc0, MCc1, and MCx, the wiring H1 that sets the first cell potential VSS1 and the wiring H2 that sets the first cell potential VSS2 are separated. The wiring H1 is shared between the rows, and the wiring H2 is shared between the rows. Then, the potentials of the wirings H1 and H2 are switched to a reference potential (for example, 0 V) or a high potential (for example, 3 V) via the switches SW1 and SW2, respectively.

  In the following description, it is assumed that the threshold values of the drive transistors D1 and D2 of the memory cell MCs vary, and the drive transistor D2 has a lower threshold value than the drive transistor D1. Then, hot carriers are injected into the drive transistor D2 of the memory cell MCs.

FIG. 5 is a diagram showing voltage levels at various parts of the semiconductor memory device of FIG. In the example of FIG. 5, the case where the configuration of FIG. 4 is applied to the configuration of FIG. 1 will be described.
In FIG. 5, when hot carriers are injected into the drive transistor D2 of the memory cell MCs, in each of the memory cells MCs, MCr, MCc0, MCc1, and MCx, the first cell potential VSS1 is set to the low level, and the second cell potential VDD and The potential of the bit line blt is set to a high level, and the first cell potential VSS2 is set to a high potential. The potential of the bit line blc is set to a low level in the memory cells MCs, MCc0, and MCc1, and is set to a high level in the memory cells MCr and MCx. The potential of the word line wl is set to a high potential in the memory cells MCs and MCr, and is set to a low level in the memory cells MCc0, MCc1, and MCx.

  At this time, in the memory cell MCs, if “1” is written to the storage node Nt and “0” is written to the storage node Nc, the drive transistor D2 is turned on. For this reason, a high voltage is applied between the source and channel of the drive transistor D2, and hot carriers are generated on the source side of the drive transistor D2.

  On the other hand, in the memory cells MCr, MCc0, MCc1, and MCx, if “0” is written to the storage node Nt and “1” is written to the storage node Nc, the drive transistor D2 is turned off. For this reason, it is possible to prevent a high voltage from being applied between the source and the channel of the driving transistor D2, and it is possible to prevent hot carriers from being generated on the source side of the driving transistor D2.

  In the memory cells MCr, MCc0, MCc1, and MCx, if “1” is written to the storage node Nt and “0” is written to the storage node Nc, the drive transistor D2 is turned on. For this reason, when the first cell potential VSS2 increases, hot carriers may be generated on the source side of the drive transistor D2. However, in the memory cells MCr, MCc0, MCc1, and MCx, if the threshold value of the drive transistor D2 is lower than that of the drive transistor D1, hot carriers may be generated on the source side of the drive transistor D2. The variation in threshold value can be prevented from increasing.

  In the memory cells MCr, MCc0, MCc1, and MCx, when “1” is written to the storage node Nt and “0” is written to the storage node Nc, when the first cell potential VSS2 increases, the storage node Nt , Nc data is inverted. For this reason, the drive transistor D2 is turned off, and hot carriers can be prevented from being generated on the source side of the drive transistor D2.

(Second Embodiment)
FIG. 6 is a block diagram showing a schematic configuration of the semiconductor memory device according to the second embodiment.
6, in this semiconductor memory device, a second cell potential controller 10 is provided in addition to the configuration of the semiconductor memory device of FIG. The second cell potential control unit 10 can control the second cell potential VDD of the load transistors L1 and L2 for each column. In the selected column, the second cell potential VDD and the potential of the bit line blt are set to a high level (for example, 1 V), and in the non-selected column, the second cell potential VDD and the potential of the bit line blt are set to a low level (for example, 0 V). can do.

  Thereby, in the non-selected column, the driving transistors D1 and D2 can be turned off, and even when the first cell potential VSS2 of the non-selected column is set to a high potential, the driving transistors D1 and D2 are hot on the source side. Carriers can be prevented from being generated. In addition, by turning off the drive transistors D1 and D2 of the non-selected column, it is possible to prevent current from flowing through the drive transistors D1 and D2 of the non-selected column, thereby reducing power consumption.

FIG. 7 is a diagram showing voltage levels of the respective parts of the semiconductor memory device according to the second embodiment. In the example of FIG. 7, a case where the configuration of FIG. 4 is applied to the configuration of FIG. 6 will be described.
7, this method is the same as the method of FIG. 5 except that the second cell potential VDD of the memory cells MCr and MCx in the non-selected column and the potential of the bit line blt are set to the low level.

  Thereby, in the memory cells MCr and MCx, the drive transistors D1 and D2 can be turned off. Even when the first cell potential VSS2 of the memory cells MCr and MCx is set to a high potential, the drive transistors D1 and D2 Hot carriers can be prevented from being generated on the source side, and power consumption can be reduced.

(Third embodiment)
FIG. 8 is a block diagram showing a schematic configuration of the semiconductor memory device according to the third embodiment.
8, in this semiconductor memory device, a first cell potential controller 9 is provided instead of the first cell potential controller 8 of the semiconductor memory device of FIG. The first cell potential control unit 9 can control the first cell potential VSS2 of the load transistor L2 for each row. In this control, two rows can be performed as a pair. In the adjacent row sharing the selected row and the first cell potential VSS2, the first cell potential VSS2 is set to a high potential (eg, 3V), and in the other non-selected rows, the first cell potential VSS2 is set to a low level (eg, 0V). ).

  Accordingly, the first cell potential VSS2 of the selected row can be raised to a high potential without raising the first cell potential VSS2 of the unselected row to a high potential, and hot carriers are generated in the drive transistor D2 of the unselected row. It can be prevented from being injected.

FIG. 9 is a block diagram showing a method for switching the source potential of the semiconductor memory device according to the third embodiment.
In the configuration of FIG. 4, the wiring H1 is shared between the rows and the wiring H2 is shared between the rows. In the configuration of FIG. 9, the wiring H1 is separated between the rows. The wiring H2 is separated between the rows. The potential of the wiring H1 is switched to a reference potential (for example, 0 V) or a high potential (for example, 3 V) for each row through the switches SW12 and SW14. In addition, the potential of the wiring H2 is switched to a reference potential (for example, 0 V) or a high potential (for example, 3 V) for each row via the switches SW11 and SW13. In the example of FIG. 9, since the source power of the driving transistors D1 and D2 is shared between two memory cells adjacent in the column direction, the potentials of the wirings H1 and H2 can be switched in units of two rows. .

FIG. 10 is a diagram showing voltage levels of the respective parts of the semiconductor memory device according to the third embodiment. In the example of FIG. 10, a case where the configuration of FIG. 9 is applied to the configuration of FIG. 8 will be described.
10, this method is the same as the method in FIG. 5 except that the first cell potential VSS2 of the memory cells MCc1 and MCx in the non-selected row is set to the low level.

  As a result, the first cell potential VSS2 of the memory cells MCs can be raised to a high potential without raising the first cell potential VSS2 of the memory cells MCc1 and MCx to a high potential, and the drive transistors of the memory cells MCc1 and MCx It is possible to prevent hot carriers from being injected into D2.

(Fourth embodiment)
FIG. 11 is a diagram showing voltage levels of the respective parts of the semiconductor memory device according to the eighth embodiment. In the example of FIG. 11, a case where the configuration of FIG. 9 is applied to the configuration of FIG. 6 will be described.
In FIG. 11, in this method, the second cell potential VDD of the memory cells MCr and MCx in the unselected column and the potentials of the bit lines blt and blc are set to the low level, and the first cells of the memory cells MCc1 and MCx in the unselected row. The method is the same as that shown in FIG. 5 except that the potential VSS2 is set to a low level.

  As a result, in the memory cells MCr and MCx, the drive transistors D1 and D2 can be turned off, and the first cell potential VSS2 of the memory cells MCc1 and MCx can be increased without increasing the first cell potential VSS2. One cell potential VSS2 can be raised to a high potential. Therefore, hot carriers can be prevented from being injected into the drive transistor D2 of the memory cells MCc1, MCr, and MCx, and power consumption can be reduced.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

(Appendix)
(Claim 6)
6. The well potential of the second driving transistor is set to be lower than the first cell potential when the hot carriers are injected into the second driving transistor. Semiconductor memory device.
(Claim 7)
When the hot carriers are injected into the second drive transistor of the selected cell specified by the selected row and the selected column, the word line of the selected row is set to the high level, and the word line of the unselected row is set to the low level. The first bit line of the selected column, the first bit line of the non-selected column, and the second bit line of the non-selected column are set to high level, and the second bit line of the selected column is set to the high level. 6. The semiconductor memory device according to claim 5, wherein the semiconductor memory device is set to a low level.
(Claim 8)
The source power of the first drive transistor of the first memory cell is the same as the source power of the first drive transistor of the second memory cell of the row address adjacent to the first memory cell at the same column address. The second drive transistor of the third memory cell of the row address that is shared and the source power of the second drive transistor of the first memory cell is the same column address as that of the first memory cell and is adjacent to the other. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is shared with a source power source of any one of claims 1 to 7.
(Claim 9)
7. The first cell potential control unit controls the first cell potential of the first driving transistor and the first cell potential of the second driving transistor for each row. The semiconductor memory device according to any one of the above.
(Claim 10)
When the hot carriers are injected into the second drive transistor of the selected cell specified by the selected row and the selected column, the word line of the selected row is set to the high level, and the word line of the unselected row is set to the low level. The first bit line of the selected column, the first bit line of the non-selected column, and the second bit line of the non-selected column are set to high level, and the second bit line of the selected column is set to the high level. The semiconductor memory device according to claim 9, wherein the semiconductor memory device is set to a low level.
(Claim 11)
11. The first cell potential control unit makes the first cell potential of the second driving transistor in a selected row higher than the first cell potential of the second driving transistor in a non-selected row. The semiconductor memory device described in 1.
(Claim 12)
7. The device according to claim 1, further comprising a second cell potential control unit that controls the second cell potential of the first load transistor and the second cell potential of the second load transistor for each column. The semiconductor memory device according to any one of the above.
(Claim 13)
When the hot carriers are injected into the second drive transistor of the selected cell specified by the selected row and the selected column, the word line of the selected row is set to the high level, and the word line of the unselected row is set to the low level. And the first bit line of the selected column is set to a high level, the second bit line of the selected column, the first bit line of the non-selected column, and the second bit line of the non-selected column, The semiconductor memory device according to claim 11, wherein is set at a low level.
(Claim 14)
The second cell potential control unit sets the second cell potential of the first and second load transistors of the non-selected column to be lower than the second cell potential of the first and second load transistors of the selected column. The semiconductor memory device according to claim 13.
(Claim 15)
The first driving transistor and the first load transistor are connected in series to form a first CMOS inverter, and the second driving transistor and the second load transistor are connected in series to each other. Thus, a second CMOS inverter is configured, and a flip-flop is configured by cross-coupling outputs and inputs of the first CMOS inverter and the second CMOS inverter with each other. The semiconductor memory device according to claim 1.
(Claim 16)
A first wiring that is arranged in parallel to the word line and sets a first cell potential of the first driving transistor;
16. The semiconductor memory according to claim 1, further comprising: a second wiring that is arranged in parallel to the word line and sets a first cell potential of the second driving transistor. 17. apparatus.
(Claim 17)
17. The semiconductor device according to claim 1, further comprising a third wiring that is arranged in parallel to the first and second bit lines and sets a second cell potential of the first and second storage nodes. 2. A semiconductor memory device according to claim 1.

  MC memory cell, 1 memory cell array, 2 timing control unit, 3 row decoder, 4 word line driver, 5 column decoder, 6 column selector, 7 read / write circuit, 8, 9 first cell potential control unit, 10 second cell Potential control unit, blt, blt_0 to blt_k, blc, blc_0 to blc_k bit line, wl, wl_0 to wl_m word line, L1, L2 load transistor, D1, D2 drive transistor, F1, F2 transmission transistor, SW1, SW2, SW11 to SW14 switch, H1, H2 wiring

Claims (5)

In a semiconductor memory device in which memory cells provided with a first storage node and a second storage node in which data are stored complementarily are arranged in a matrix in the row direction and the column direction,
A word line for selecting the memory cell for each row;
First and second bit lines for selecting the memory cells for each column;
A first load transistor that pulls up the potential of the first storage node based on the potential of the second storage node;
A first drive transistor that pulls down the potential of the first storage node based on the potential of the second storage node;
A second load transistor for pulling up the potential of the second storage node based on the potential of the first storage node;
A second drive transistor for pulling down the potential of the second storage node based on the potential of the first storage node;
A first transmission transistor that connects the first storage node and the first bit line based on the potential of the word line;
A second transmission transistor for connecting the second storage node and the second bit line based on the potential of the word line;
A first cell potential controller that individually controls a first cell potential of the first driving transistor and a first cell potential of the second driving transistor;
Assuming that the second driving transistor has a lower threshold value than the first driving transistor, the first cell potential control unit may inject hot carriers into the second driving transistor. Controlling the first cell potential;
When hot carriers are injected into the second drive transistor, '1' is stored in the first storage node, and '0' is stored in the second storage node. A semiconductor memory device. In a semiconductor memory device in which memory cells provided with a first storage node and a second storage node in which data are stored complementarily are arranged in a matrix in the row direction and the column direction,
A word line for selecting the memory cell for each row;
First and second bit lines for selecting the memory cells for each column;
A first load transistor that pulls up the potential of the first storage node based on the potential of the second storage node;
A first drive transistor that pulls down the potential of the first storage node based on the potential of the second storage node;
A second load transistor for pulling up the potential of the second storage node based on the potential of the first storage node;
A second drive transistor for pulling down the potential of the second storage node based on the potential of the first storage node;
A first transmission transistor that connects the first storage node and the first bit line based on the potential of the word line;
A second transmission transistor for connecting the second storage node and the second bit line based on the potential of the word line;
A semiconductor memory device comprising: a first cell potential control unit that individually controls a first cell potential of the first driving transistor and a first cell potential of the second driving transistor.   Assuming that the second driving transistor has a lower threshold value than the first driving transistor, the first cell potential control unit may inject hot carriers into the second driving transistor. The semiconductor memory device according to claim 1, wherein the first cell potential is controlled.   When hot carriers are injected into the second drive transistor, '1' is stored in the first storage node, and '0' is stored in the second storage node. The semiconductor memory device according to claim 3.   The first cell potential controller may be higher than the first cell potential of the first drive transistor, the second cell potential of the first load transistor, and the second cell potential of the second load transistor. 5. The semiconductor memory device according to claim 4, wherein the first cell potential of the second drive transistor is controlled.

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