JPH0498857A - Semiconductor device package - Google Patents

Semiconductor device package

Info

Publication number
JPH0498857A
JPH0498857A JP2216137A JP21613790A JPH0498857A JP H0498857 A JPH0498857 A JP H0498857A JP 2216137 A JP2216137 A JP 2216137A JP 21613790 A JP21613790 A JP 21613790A JP H0498857 A JPH0498857 A JP H0498857A
Authority
JP
Japan
Prior art keywords
semiconductor device
leads
lead
frame
device package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2216137A
Other languages
Japanese (ja)
Inventor
Kazuhiro Miyamoto
和広 宮本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Kyushu Ltd
Original Assignee
NEC Kyushu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Kyushu Ltd filed Critical NEC Kyushu Ltd
Priority to JP2216137A priority Critical patent/JPH0498857A/en
Publication of JPH0498857A publication Critical patent/JPH0498857A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To improve a semiconductor device in stability of ground potential by a method wherein a semiconductor device package is provided with leads and suspension pins bonded to the upper end face of the side wall of a ceramic case, where the suspension pin and the adjacent lead are formed into one piece in such a manner that they are partially connected together. CONSTITUTION:An amorphous or crystalline glass layer 2 is formed on the upper end face of the side wall of a ceramic case 1 where a die pad is provided at its center, and leads 3 and a suspension pin 4 provided as partially joined to an adjacent lead 3a are bonded to the glass layer 2 to form a semiconductor device package. In succession, a semiconductor chip 5 is mounted on the die pad, and the electrodes 6 of the semiconductor chip 5 are connected to the leads 3 and 3a with metal fine wires 7 respectively. At this point, a power supply wire or a grounding wire is connected to the lead 3a, whereby a semiconductor device can be lessened in resistance and inductance. Next, the leads 3 and 3a are cut off from the frame 8 of a lead frame, and the ceramic case 1 is supported at the frame 8 only by the suspension 4. By this setup, a semiconductor device can be lessened in resistance and inductance and improved in stability of power supply and ground potential.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置用パッケージに関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a package for a semiconductor device.

〔従来の技術〕[Conventional technology]

従来の半導体装置用パッケージは、第２図（ａ）に示す
ように、内側中央部に素子載置部を設けたセラミック容
器１の側壁部上端面にガラス層２を介してリード３及び
吊りピン４を枠８で支持したリードフレームを接合して
パッケージを構成し、第２図（ｂ）に示すように、素子
載置部に半導体チップ５をマウントし、半導体チップ上
のｔ極６とリード３との間を金属細線７で電気的に接続
し、リード３及び吊りピン４を枠８より切離していた。As shown in FIG. 2(a), a conventional semiconductor device package has leads 3 and hanging pins placed on the upper end surface of the side wall of a ceramic container 1, which has an element mounting section in the center of the inside, through a glass layer 2. A package is constructed by joining a lead frame 4 supported by a frame 8, and as shown in FIG. The lead 3 and the hanging pin 4 were separated from the frame 8 by electrically connecting with the lead 3 using a thin metal wire 7.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の半導体装置用パッケージは、リードがい
ずれも同じ太さを有しているため電源や接地線に接続し
た場合、抵抗やインダクタンスが大きく、このため電位
変動が大きくなるという欠点があった。The conventional semiconductor device package described above had the disadvantage that all the leads had the same thickness, so when connected to a power supply or ground line, the resistance and inductance were large, resulting in large potential fluctuations. .

〔課題を解決するための手段〕[Means to solve the problem]

本発明の半導体装置用パッケージは、セラミック容器の
側壁部上端面にガラス層を介して接合したリード及び吊
りピンを有する半導体装置用パッケージにおいて、前記
吊りピンが隣接する前記リードの少くとも一部を接続し
て一体化されて構成される。The semiconductor device package of the present invention has a lead and a hanging pin that are bonded to the upper end surface of a side wall of a ceramic container via a glass layer, in which the hanging pin connects at least a portion of the adjacent lead. Connected and integrated.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説゛明する。 Next, the present invention will be explained with reference to the drawings.

第１図（ａ）、（ｂ）は本発明の一実施例の製造方法を
説明するための工程順に示したパ・ンケージの平面図で
ある。FIGS. 1(a) and 1(b) are plan views of a package shown in the order of steps for explaining a manufacturing method according to an embodiment of the present invention.

第１図（ａ）に示すように、内側中央部に素子載置部を
設けたセラミック容器１の側壁部上端面に非結晶性また
は結晶性のガラス層２を形成し、ガラス層２にリード３
及び隣接するり−ド３ａと一部を接続して設けた吊りビ
ン４を接合して半導体装置用パッケージを構成する。As shown in FIG. 1(a), an amorphous or crystalline glass layer 2 is formed on the upper end surface of the side wall of a ceramic container 1 having an element mounting portion provided at the center of the inner side. 3
A hanging bottle 4, which is partially connected to an adjacent board 3a, is joined to form a semiconductor device package.

次に、第１図（ｂ）に示すように、素子載置部に半導体
チップ５をマウントし、半導体チップ５の電極６とリー
ド３．３ａとをそれぞれ金属細線７で接続する。ここで
、リード３ａには電源又は接地線を接続することにより
、抵抗やインダクタンスを減少させることができる。次
に、リード３．３ａをリードフレームの枠８より切離し
て吊りビン４のみでセラミック容器１を枠８に支持する
。Next, as shown in FIG. 1(b), the semiconductor chip 5 is mounted on the element mounting portion, and the electrodes 6 of the semiconductor chip 5 and the leads 3.3a are connected with thin metal wires 7, respectively. Here, resistance and inductance can be reduced by connecting a power supply or ground line to the lead 3a. Next, the lead 3.3a is separated from the frame 8 of the lead frame, and the ceramic container 1 is supported on the frame 8 using only the hanging bottle 4.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、吊りビンと、吊りビンに
隣接するリードを接続して一体化した太いリードに電源
又は接地線を接続することにより、抵抗及びインダクタ
ンスを低減して電源又は接地電位の安定性を向上させる
事ができるという効果を有する。As explained above, the present invention reduces resistance and inductance by connecting a power supply or ground wire to a thick lead that is integrated by connecting a hanging bottle and a lead adjacent to the hanging bottle, thereby reducing the power supply or ground potential. This has the effect of improving the stability of

【図面の簡単な説明】[Brief explanation of drawings]

第１図（ａ）、（ｂ）は本発明の一実施例の製造方法を
説明するための工程順に示したパッケージの部分平面図
、第２図（ａ）、（ｂ）は従来の半導体装置用パッケー
ジの製造方法を説明するための工程順に示したパッケー
ジの部分平面図である。 ｌ・・・セラミック容器、２・・・ガラス層、３，３ａ
・・・リード、４・・・吊りビン、５・・・半導体チッ
プ、６・・・電極、７・・・金属細線、８・・・枠。FIGS. 1(a) and (b) are partial plan views of a package shown in order of steps for explaining the manufacturing method of an embodiment of the present invention, and FIGS. 2(a) and (b) are partial plan views of a conventional semiconductor device. FIG. 3 is a partial plan view of a package shown in order of steps for explaining a method for manufacturing a package for use in the manufacturing of electronic devices. l... Ceramic container, 2... Glass layer, 3, 3a
...Lead, 4...Hanging bottle, 5...Semiconductor chip, 6...Electrode, 7...Thin metal wire, 8...Frame.

Claims (1)

【特許請求の範囲】[Claims] 　セラミック容器の側壁部上端面にガラス層を介して接
合したリード及び吊りピンを有する半導体装置用パッケ
ージにおいて、前記吊りピンが隣接する前記リードの少
くとも一部を接続して一体化されていることを特徴とす
る半導体装置用パッケージ。In a semiconductor device package having leads and hanging pins bonded to the upper end surface of a side wall of a ceramic container via a glass layer, the hanging pins are integrated by connecting at least a part of the adjacent leads. A semiconductor device package featuring:
JP2216137A 1990-08-16 1990-08-16 Semiconductor device package Pending JPH0498857A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2216137A JPH0498857A (en) 1990-08-16 1990-08-16 Semiconductor device package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2216137A JPH0498857A (en) 1990-08-16 1990-08-16 Semiconductor device package

Publications (1)

Publication Number Publication Date
JPH0498857A true JPH0498857A (en) 1992-03-31

Family

ID=16683849

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2216137A Pending JPH0498857A (en) 1990-08-16 1990-08-16 Semiconductor device package

Country Status (1)

Country Link
JP (1) JPH0498857A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0855949A (en) * 1994-08-16 1996-02-27 Nec Kyushu Ltd Flat package

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0855949A (en) * 1994-08-16 1996-02-27 Nec Kyushu Ltd Flat package

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