JPH0495299A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To effectively utilize the memory by constituting the device so that data to which reliability of a high level is requested is allowed to pass through an error correcting circuit, other data is not allowed to pass through the error correcting circuit and a main bit memory and a parity memory are used as store places of the data. CONSTITUTION:The device is provided with a selecting circuit 1 for transferring input data DT1 to an output terminal in accordance with a level of a mode control signal ECC and a selection control signal AN, a main bit memory 2 for storing he data by a write control signal WE and reading out the stored data in accordance with a read-out control signal RE, and a parity bit memory 3 for storing the data and reading out the data in the same way. Also, this device is provided with a selecting/error correcting circuit 4 for executing an error correction processing to the data from the memories 2, 3 at the time when the mode control signal ECC is in an active level, and selecting and outputting the data from the memories 2, 3 at the time when the mode control signal is in a non-active level. In such a way, the main bit memory 2 and the parity bit memory 3 can be used as mere store places of data, and the memory can be utilized effectively.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and particularly to a semiconductor memory device equipped with an error correction circuit.

[Prior Art] Conventionally, this type of semiconductor memory device has an input side that performs error correction logic processing on input data DTI and outputs main bits and parity bits, as shown in FIG. an error correction logic circuit 5c, a main bit memory 2B which stores main bits according to a write control signal WE during a write operation, and reads stored data according to a read control signal RE during a read operation; , a parity bit memory 3B which stores a parity bit in accordance with a write control signal WE, and reads stored data in accordance with a read control signal RE during a read operation, a main bit memory 2s, and data from a parity bit memory 3B. The configuration includes an error correction logic circuit 5D on the output side which performs error correction logic processing on the output side and outputs error corrected output data DT○.

[Problem to be solved by the invention]

In the conventional semiconductor memory device described above, the input data DTI always passes through the error correction logic circuit 5C to the main bit memory 2.
Since the data stored in the main bit memory 2B and the parity bit memory 3B are outputted via the error correction logic circuit 5D, the reliability is very high. When storing data that does not require high accuracy and does not require error correction processing, the parity bit memory 3D cannot be used simply as a data storage location, and the memory cannot be used effectively.

An object of the present invention is to provide a semiconductor memory device that allows a parity bit memory to be used simply as a data storage location, thereby making effective use of the memory! Our goal is to provide the following.

[Means to solve the problem]

A semiconductor memory device according to a first aspect of the invention includes a selection circuit that includes first and second output terminals and transmits input data to the first and second output terminals according to the levels of a mode control signal and a selection control signal. a main bit memory that stores data from a first output terminal of the selection circuit during a write operation and reads stored data during a read operation; and a main bit memory that stores data from a first output terminal of the selection circuit during a write operation; a parity bit memory for storing data and reading out the stored data during a read operation; and a parity bit memory for performing error correction processing on data from the main bit memory and parity bit memory when the mode control signal is at an active level. and a selection/error correction circuit that selects and outputs data from the main bit memory and the parity bit memory according to the level of the selection control signal when the mode control signal is at an inactive level. There is.

A semiconductor memory device according to a second invention includes first to third output terminals, transmits input data to the first output terminal when the mode control signal is at an active level, and transmits input data to the first output terminal when the mode control signal is at an inactive level. a first selection circuit that transmits data to the second and third output terminals in accordance with the level of the selection control signal when the signal is at the level; and a predetermined error in data from the first output terminal of the first selection circuit. a first error correction logic circuit that performs correction logic processing and outputs a main bit and a parity bit, and during a write operation;
If the mode control signal is at an active level, the main bit is stored; if the mode control signal is at an inactive level, the data from the second output terminal of the first selection circuit is stored, and the stored data is used during a read operation. a main bit memory for reading; a first data output switching circuit for inputting data from the third output terminal of the first selection circuit and outputting this data in units of predetermined bits; a parity bit memory that stores the parity bit when the control signal is at an active level, stores data from the first data output switching circuit when the control signal is at an inactive level, and reads out the stored data during a read operation; , a second error correction logic circuit which performs predetermined error correction logic processing on the data from the main bit memory and the parity bit memory; a second data output switching circuit that outputs data in units; a second data output switching circuit that outputs data from the second error correction logic circuit when the mode control signal is at an active level; and a selection control circuit that outputs data from the second error correction logic circuit when the mode control signal is at an inactive level; and a second selection circuit that selects and outputs data from the main bit memory and the second data output switching circuit according to the level of the signal.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the first invention.

This embodiment has first and second output terminals, and outputs input data DTI according to the levels of the mode control signal ECC and the selection control signal AN (A9 is the most significant bit of the address signal).
a selection circuit 1 that transmits a signal to first and second output terminals;
Stores data from the first output terminal of , and during read operation,
A main bit memory 2 reads stored data according to a read control signal RE, and also stores data from the second output terminal of the selection circuit 1 during a write operation, and similarly stores data from the second output terminal of the selection circuit 1 during a read operation. When the mode control signal ECC is at active level, error correction processing is performed on the data from the main hit memory 2 and parity bit memory 3, and when the mode control signal ECC is at the inactive level, it is output. a selection/error correction circuit 4 that selects and outputs data from the main bit memory 2 and the parity bit memory 3 according to the level of the selection control signal AN;
The structure has the following.

FIGS. 2 and 3 are circuit diagrams showing specific examples of the selection circuit 1 and selection/error correction circuit of this embodiment, respectively.

Next, the operation of this embodiment will be explained.

First, a case where the mode control signal FCC is not in the inactive (high level) error correction mode will be described.

In the selection circuit 1, since the mode control signal FCC is at a high level, the selection control signal AN, which is the most significant bit of the address signal, passes through the NA and ND gates NAGINAG2 and is transmitted to the transfer gates TG1 and TG2. . Therefore, the input data DT■ is distributed to the first output terminal (main bit memory 2 side) and the second output terminal (parity bit memory 3 side) according to the level of the selection control signal AN.

The main bit memory 2 and the parity bit memory 3 each write the data distributed by the selection circuit 1.
It is stored according to E and read according to read control signal RE.

In the selection/error correction circuit 4, since the mode control signal FCC is at a high level, the selection control signal As is applied to the NAND gate NAG3. Pass through NAG4 and transfer gate TG
3 to TG6, and when the selection control signal AN is at a low level, the transfer gates TG3. TG6 is on, transfer gate TG4. TG5 is turned off, data from main bit memory 2 is output via NOR gate N0GI and inverter IVI, and when selection control signal AN is at high level, data from parity bit memory 3 is output.

Thus main bit memory 2 and parity bit memory 3
can equally be used simply as a data storage location.

When the mode control signal ECC is in the low level error correction mode, the selection circuit 1 selects the NAND gates NAGI, NAG
The two outputs are both turned on, and one input data DTI is simultaneously output to the first and second output terminals.

These output data are stored in the main bit memory 2 and parity bit memory 3 and read out.

In the selection/error correction circuit 4, NAND gates NAG3.
Since the outputs of NAG4 both become high level, transfer gates TG3. TG4 is on, transfer gate T
G5. TG6 is turned off, and the data from main bit memory 2 and parity bit memory 3 becomes NOR game) NO
The signal is input to GI, where it undergoes NOR logic processing and is output via inverter IVI.

Generally, a main bit memory 2 and a parity bit memory 3
Since most of the data errors are defects that change from "1" to "0", the errors can be corrected by passing the data through the NOR gate N0G1.

FIG. 4 is a block diagram showing an embodiment of the second invention.

This embodiment has first to third output terminals, and transmits 8-bit input data DTI to the first output terminal when the mode control signal ECC is at an active level.
The first selection circuit 1^ transmits data to the second and third output terminals according to the selection control signal AN level when the signal is inactive level, and the data from the first output terminal of the first selection circuit l^. An error correction logic circuit 5A on the input side performs error correction logic processing on the input side and outputs 8 main bits and 4 parity bits, and a mode control signal E during write operation.
If CC is at an active level, the main bit is stored; if it is inactive, data from the second output terminal of the first selection circuit IA is stored, and the stored data is read in units of 8 bits during a read operation. The main bit memory 2^ which is read by the input terminal, and the data output switching circuit 6A on the input side which inputs data from the third output terminal of the first selection circuit IA and outputs this data in units of 4 bits, , mode control signal FCC
A parity bit memory stores the parity bit when it is at an active level, stores data from the data output switching circuit 6A when it is at an inactive level, and reads out the stored data in units of 4 bits during a read operation. 3A, an error correction logic circuit 5B on the output side that performs error correction logic processing on the output side for data from the main bit memory 2A and the parity bit memory 3A, and outputs 8-bit data; a data output switching circuit 6B on the output side that inputs data in 4-bit units and outputs this data in 8-bit units; and outputs data from the error correction logic circuit 5B when the mode control signal ECC is at an active level;
A second circuit that selects and outputs data from the main bit memory 2A and data output switching circuit 6B in accordance with the level of the selection control signal AN when the mode control signal ECC is at an inactive level.
selection circuit IB, data output switching circuits 6^, 6a, and an address shift circuit 7 and address increment circuit 8 that control data input/output of the parity bit memory 3A.
The structure has the following.

In this embodiment, when the mode control signal ECC is at the active level, input data DTI is stored in the main bit memory 2A and parity bit memory 3A through the error correction logic circuit 5A on the input side. The data read from the parity bit memory 3A is outputted through the error correction logic circuit 5B on the output side, and when the mode control signal ECC is at an inactive level, the input data DTI is not passed through the error correction logic circuit 5A. The data is stored in the main bit memory 2A and the parity bit memory 3^, and the data successively output from the main bit memory 2A and the parity bit memory 3^ is output without passing through the error correction logic circuit 5B. and mode control signal ECC
When the inactive level is 7, the parity bit memory 3A, which inputs and outputs data in 4-bit units, has the advantage of storing input data DTI in 8-bit units and outputting it in 8-bit units. . Furthermore, when data that requires a higher degree of reliability is mixed, it is desirable to apply this second invention.

〔Effect of the invention〕

As explained above, in the present invention, data that requires a high degree of reliability is set in an error correction mode and passes through an error correction circuit, and data that does not require a high degree of reliability is passed through an error correction circuit. By configuring the main bit memory and parity memory as mere storage locations for data, it is possible to obtain high reliability for data that requires a high degree of reliability. This has the effect of increasing storage capacity for data that is not required.

FIG. 4 is a block diagram showing an embodiment of the second invention, and FIG. 5 is a block diagram showing an example of a conventional semiconductor memory device.

1.1A, 1B...selection circuit, 2.2A, 2B...
・Main bit memory, 3.3A, 3a... Parity bit memory, 4... Selection/error correction circuit, A~5°... Error correction logic circuit, 6A, 6B... Data output switching Circuit, 7...Address shift circuit, 8...Address increment circuit, IVI...Inverter, N
AGl-NAG4...NAND gate, NOG 1.
・N○R gate, TGI to TG6...Transfer.

Claims (1)

[Scope of Claims] 1, first and second output terminals, and input data is transmitted to the first output terminal according to the levels of the mode control signal and the selection control signal.
and a main bit memory that stores data from the first output terminal of the selection circuit during a write operation and reads out the stored data during a read operation; When the mode control signal is at an active level, a parity bit memory stores data from the second output terminal of the selection circuit and reads out the stored data during a read operation; Data from the bit memory is subjected to error correction processing and output, and when the mode control signal is at an inactive level, data from the main bit memory and parity bit memory is selected and output according to the level of the selection control signal. 1. A semiconductor memory device comprising a selection/error correction circuit. 2. comprising first to third output terminals, transmitting input data to the first output terminal when the mode control signal is at an active level; and transmitting input data to the first output terminal when the mode control signal is at an inactive level; A first selection circuit transmits the data to the second and third output terminals in accordance with the above, and predetermined error correction logic processing is performed on the data from the first output terminal of the first selection circuit, and the main bit and a first error correction logic circuit that outputs a parity bit; and a second error correction logic circuit of the first selection circuit that stores the main bit when the mode control signal is at an active level and stores the main bit when the mode control signal is at an inactive level during a write operation; a main bit memory that stores data from the output terminal of the circuit and reads out the stored data during a read operation; and a main bit memory that inputs data from the third output terminal of the first selection circuit and inputs the data to a predetermined bit. a first data output switching circuit that outputs data in units; and during a write operation, if the mode control signal is at an active level, the parity bit is stored; if the mode control signal is at an inactive level, the parity bit is stored; A parity bit memory that stores data and reads out the stored data during a read operation, and a second error that performs predetermined error correction logic processing on the data from the main bit memory and parity bit memory and outputs the data. a correction logic circuit; a second data output switching circuit that inputs data from the parity bit memory and outputs the data in predetermined bit units; and a second error correction circuit when the mode control signal is at an active level. a second data output switching circuit that outputs data from the logic circuit, and selects and outputs data from the main bit memory and the second data output switching circuit according to the level of the selection control signal when the mode control signal is at an inactive level; 1. A semiconductor memory device comprising: two selection circuits.