JPH0494151A - Parallel wiring treatment for integrated circuit - Google Patents

Abstract

PURPOSE:To shorten the time required for wiring by determining parallelly a detailed route for each of a plurality of nets which has a schematic route not crossed by any other schematic route on a chip, for a master CPU and a plurality of slave CPU's. CONSTITUTION:Using a master 2, a schematic route 11 is determined for a group of terminals which require wiring, for example, terminals 12-14. The same operation is done for the other groups of terminals which require wiring to determine schematic routes 7-10. Nextly, detailed routes 15 in the global routes are parallelly alloted to slave CPU's 3 respectively. Here, let's assume there are four sets of slave CPU's 3. Since the global routes 7-10 have no intersection with each other, the detailed routes 15 of these global routes are alloted to four sets of slave CPU's 3 to be processed parallelly and the detailed route 15 is determined for the global route 10. After the detailed route is determined for the global route 7, the schematic route 11 is alloted to the same slave CPU 3 as was used for determining the detailed route for the global route 7 and is processed on that slave CPU 3 since it has no intersection with any one of the global routes 8-10.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a parallel wiring processing method for integrated circuits, and in particular to a two-step wiring processing of general wiring and detailed wiring using an electronic computer having a plurality of arithmetic units. The present invention relates to a wiring processing method for integrated circuits.

[Conventional technology]

Conventionally, wiring processing for integrated circuits has been widely performed automatically by electronic computers, but as the scale of integrated circuits has increased, the calculation time has increased. In particular, the amount of data for detailed wiring compared to general wiring has increased enormously, and the calculation time has increased rapidly. Furthermore, advances in integrated circuits and electronic computers have lowered the cost of electronic computers, and general-purpose computers that perform multiple processes in parallel to increase speed have appeared, making it easier to use parallel computing to automate the design of integrated circuits. It has become.

Conventionally, most automatic wiring processing has been performed by an electronic computer having one arithmetic unit, and a two-step wiring method has been adopted in which a general wiring route is determined and then a detailed wiring route is determined within the general route. In this two-stage wiring as well, detailed wiring within the general wiring is performed sequentially. Further, as a conventional method for parallelizing wiring, for example, there is an example in which wavefront propagation using a maze method using Lee's algorithm is performed in parallel. This method takes advantage of the parallelism of processing within the algorithm, and is specifically described in Information Processing Society of Japan Transactions (Vol. 27 No.
, 6 pp. 639-6471986).

[Problem to be solved by the invention]

The above-described conventional parallel wiring processing method for integrated circuits has a drawback that even when parallel processing is performed, the proportion of processing that is performed in parallel is small, and the wiring processing takes too much time.

An object of the present invention is to provide a parallel wiring method for integrated circuits that can shorten the wiring time.

[Means to solve the problem]

A parallel wiring processing method for an integrated circuit according to the present invention includes an electronic computer including a master CPU and a plurality of slave CPUs capable of processing in parallel, and the master CPU determines a rough wiring route on a chip in response to a wiring request. However, after that, the slave CPL' performs two-stage wiring to obtain detailed wiring of the wiring request within the general wiring route, and the master CPU and a plurality of slave CPUs are instructed to intersect the general wiring routes on the chip. The present invention is configured to calculate the detailed routes of a plurality of wirings having no part in parallel.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an electronic computer equipped with a plurality of storage areas and a plurality of CPUs for explaining one embodiment of the present invention.

As shown in FIG. 1, the entire system of this embodiment consists of a master CPU 2 and a plurality of slave CPUs 3.
U has local storage area 1. Further, each CPU has a common storage area 4 via a bus router, and this common storage area 4 stores all wiring requests and the rough wiring routes determined by the master CPU 2. The master CPU 2 determines a rough wiring route, manages subsequent processing, and instructs the slave CPU 3 to wire within the rough wiring route. On the other hand, slave CPU3 has local storage area 1,
Alternatively, the common storage area 4 is used to process the detailed wiring 15 within the general wiring route. In other words, in the parallel wiring method of this embodiment, the master CPU 2, which is one arithmetic unit, performs overall control and management. The slave CPUs 3, which are a plurality of other arithmetic units, execute detailed wiring of wirings that do not have intersections between the respective rough wirings in parallel. Note that the design data is shared by each CPU.

First, for each wiring request, the master CPU 2 calculates an approximate wiring route on the chip, that is, a rough wiring route. The slave CPU 3 searches and processes detailed wiring routes in parallel.

At this time, since the detailed wiring route is searched within the general wiring route where the general wiring route has an intersection, the slave CPU 3 can process completely independently from the other slave CPs and U 3, increasing parallelism. There is.

- When the main wiring is completed only in the slave CPU 3, the master CPU 2 assigns to the slave CPU 3 a wiring that does not have an intersection between the wiring currently being processed and the general wiring, and continues this process until all the wiring is completed.

FIG. 2 is a processing flow diagram of the computer in FIG. 1.

As shown in Figure 2, for each wiring request, the master CPU
In step 2, a rough wiring route on the chip is determined, and when all the wiring routes are completed, the process ends. Next, if there is any unrouted wiring, select a wiring that does not have an intersection between the wiring currently being processed by the slave CPU 3 and the general wiring route, and have the slave CPU 3 search for a detailed wiring route within that general wiring route. do. This allocation is performed until there are no free slave CPUs 3 left, and once the detailed wiring being processed is completed, the next allocation operation is repeated.

FIG. 3 is a schematic diagram of a chip in which a specific wiring route is determined using the computer shown in FIG. 1.

As shown in FIG. 3, first, using the master 2, a rough wiring route 11 is determined for terminals with a wiring request, eg, 12 to 14. Similar operations are performed for other wiring request terminals to obtain approximate wiring routes 7 to 10. Next, the detailed wiring 15 within the general wiring route is allocated to each slave CPU 3 in parallel. Now, let's consider a case where there are four slave CPUs 3. Then, since the general wiring routes 7 to 10 do not have intersections, these detailed wiring routes 15 are assigned to the four slave CPUs 3 and processed in parallel, and the general wiring routes 10 are processed in parallel.
Detailed wiring 15 is determined for .

Next, when the detailed wiring of the general wiring route 7 is completed, since the general wiring route 11 does not have any intersection with any of the general wiring routes 8 to 10, the same slave CPU 3 that calculated the detailed route in the general wiring route 7 Make an assignment to process. This is done for all wiring requests.

〔Effect of the invention〕

As explained above, the integrated circuit parallel wiring processing method of the present invention has the effect of reducing the time required for wiring by processing the wiring of the general wiring route without intersections in parallel. .

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a computer equipped with a plurality of storage areas and a CPU for explaining an embodiment of the present invention, FIG. 2 is a processing flow diagram of FIG. 1, and FIG. 3 is similar to FIG. FIG. 3 is a schematic diagram of a chip in which a specific wiring route is determined using the electronic computer shown in FIG. 1... Local storage area, 2... Master CPU, 3
...Slave CPU, 4...Common storage area, 5...
- Bus, 6... Chip, 7-11... General wiring route, 12-14... Terminal, 15... Detailed wiring.

Claims (1)

[Scope of Claims] 1. An electronic computer including a master CPU and a plurality of slave CPUs capable of processing in parallel;
U determines a rough wiring route on the chip for the wiring request, and then the slave CPU performs two-stage wiring to obtain detailed wiring for the wiring request within the rough wiring route, and the slave CPU 1. A parallel wiring processing method for an integrated circuit, characterized in that a CPU calculates in parallel detailed routes of a plurality of wirings that do not have intersections of the general wiring routes on a chip. 2. The integrated circuit parallel wiring processing method according to claim 1, wherein the master CPU and the slave CPU each have a local storage area.