JPH0493060A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0493060A JPH0493060A JP20990590A JP20990590A JPH0493060A JP H0493060 A JPH0493060 A JP H0493060A JP 20990590 A JP20990590 A JP 20990590A JP 20990590 A JP20990590 A JP 20990590A JP H0493060 A JPH0493060 A JP H0493060A
- Authority
- JP
- Japan
- Prior art keywords
- ceramic substrate
- electrode
- reference potential
- wiring
- terminating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 43
- 239000000919 ceramic Substances 0.000 claims abstract description 34
- 239000000758 substrate Substances 0.000 claims abstract description 34
- 239000002184 metal Substances 0.000 claims abstract description 13
- 239000010409 thin film Substances 0.000 claims 1
- 230000010354 integration Effects 0.000 abstract description 5
- 238000004806 packaging method and process Methods 0.000 abstract 1
- 239000006187 pill Substances 0.000 abstract 1
- 238000000034 method Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 235000011962 puddings Nutrition 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関し、特にＥＣＬ回路を含む半導
体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device including an ECL circuit.
従来、この種の半導体装置は、回路構成の制約により受
端側の入力端に終端抵抗を設ける必要がある。Conventionally, this type of semiconductor device requires a terminating resistor to be provided at the input end on the receiving end side due to restrictions on the circuit configuration.
第４図は従来の半導体装置の第１の例とこの半導体装置
の終端抵抗の取付は方法を説明するための断面側面図で
ある。FIG. 4 is a cross-sectional side view for explaining a first example of a conventional semiconductor device and a method for attaching a terminating resistor to this semiconductor device.
この第］の例の半導体装Ｊ １００ Ａは、容器の一部
を形成するセラミック基板ＩＡと、このセラミック基板
１Ａの容器内側の所定の位置に搭載された半導体回路部
２と、セラミック基板ＩＡに突出して設けられ、半導体
回路部２への入力信号を外部から取込むための入力信号
用の外部リードピン４Ｂと、この外部リードピン４ｎと
接続しセラミック基板１Ａの容器内側の所定の位置に形
成された内部電極１１−Ａと、この内部電極１］、Ａと
半導体回路部２の対応する電極とを接続する金属細線３
とを有する構成となっている。The semiconductor device J 100A of this second example includes a ceramic substrate IA forming a part of a container, a semiconductor circuit section 2 mounted on the ceramic substrate 1A at a predetermined position inside the container, and a ceramic substrate IA forming a part of the container. An input signal external lead pin 4B is provided to protrude and is used to take in an input signal to the semiconductor circuit section 2 from the outside, and an external lead pin 4B is connected to this external lead pin 4n and is formed at a predetermined position inside the container of the ceramic substrate 1A. The internal electrode 11-A and the internal electrode 1], the thin metal wire 3 connecting A and the corresponding electrode of the semiconductor circuit section 2
The structure has the following.
この半導体装置１００Ａは、これ自身に終端抵抗を取付
けることができないのて、この半導体装置１００Ａを実
装するプリント基板２００に、入力信号用の外部リード
ピン４Ｂと接続するプリント配線２０１を利用して終端
抵抗５Ｂを取付けるようになっている。Since this semiconductor device 100A cannot attach a terminating resistor to itself, a terminating resistor is installed on a printed circuit board 200 on which this semiconductor device 100A is mounted using a printed wiring 201 connected to an external lead pin 4B for input signals. 5B is to be installed.
第５図は従来の半導体装置の第２の例とこの半導体装置
の終端抵抗の取付方法を説明するための断面側面図であ
る。FIG. 5 is a cross-sectional side view for explaining a second example of a conventional semiconductor device and a method of attaching a terminating resistor to this semiconductor device.
この第２の例の半導体装置１００ｃもこれ自身に終端抵
抗を取付けるところがないか、内部電極１１Ｂと分岐接
続する外部リードピン４ｃが設けられており、この外部
リードピン４゜を利用してプリント基板２００Ａに終端
抵抗５Ｂを取付けるようになっている。The semiconductor device 100c of this second example also has no place for attaching a terminating resistor, and is provided with an external lead pin 4c that is branched and connected to the internal electrode 11B. A terminating resistor 5B is to be installed.
上述した従来の半導体装置は、第１の例においては、内
部電極１． ］、 Ａと入力信号用の外部リードピン４
Ｂとが１対１に接続され、半導体装置自身に終端抵抗を
取付けるところがなく、この外部リードピン４Ｂと接続
する実装用のプリント基板２００のプリン１へ配線２０
１を利用してプリン１一基板２００に取付けるようにな
っているので、半導体回路部２の高速化、高集積化に伴
い、終端抵抗５ｎから半導体回路部２の入力端の電極ま
での距離か使用波長に対して無視てきなくなり、この距
離か使用波長の１／４以」−になると信号線路がスタブ
構造となるため、特性インピーダンスの整合不良、入力
信号の伝搬不良を発生ずるという欠点かある。In the first example, the conventional semiconductor device described above has internal electrodes 1. ], A and external lead pin 4 for input signal
B is connected one-to-one, there is no place to attach a terminating resistor to the semiconductor device itself, and the wiring 20 is connected to the printed circuit board 1 of the mounting printed circuit board 200 connected to this external lead pin 4B.
1 is used to attach the printer 1 to the substrate 200. As the semiconductor circuit section 2 becomes faster and more highly integrated, the distance from the terminating resistor 5n to the electrode at the input end of the semiconductor circuit section 2 increases. If the wavelength used is no longer ignored, and if the distance exceeds 1/4 of the wavelength used, the signal line becomes a stub structure, which may cause poor matching of characteristic impedance and poor propagation of the input signal. .
また、第２の例においては、内部電極１１Ｂと分岐接続
する外部リードピン４゜を備えた構造となっているので
、特性インピータンスの整合不良、入力信号の伝搬不良
は生じないが、外部り−ドピン４ｃが増加するために高
集積化が困難であるという欠点がある。In addition, in the second example, since the structure includes an external lead pin 4° that is branched and connected to the internal electrode 11B, there will be no characteristic impedance matching failure or input signal propagation failure; There is a drawback that high integration is difficult due to the increase in doping pins 4c.
また、何れの半導体装置１００Ａ、１００ｃにおいても
、実装用のプリン１〜基板２００，２００Ａに終端抵抗
５Ｂを取付けるようになっているのて、実装用のプリン
ト基板の面積が増大するという欠点かある。In addition, in both semiconductor devices 100A and 100c, since the termination resistor 5B is attached to the printed circuit board 1 to the printed circuit board 200, 200A for mounting, there is a drawback that the area of the printed circuit board for mounting increases. .
本発明の目的は、特性インピータンスの整合不良、入力
信号の伝搬不良の発生を防止すると共に高集積化か容易
となり、しかも実装用のプリン１一基板の面積を縮小す
ることができる半導体装置を提供することにある。An object of the present invention is to provide a semiconductor device that can prevent the occurrence of characteristic impedance matching failures and input signal propagation failures, facilitate high integration, and reduce the area of the printed circuit board 1 for mounting. It is about providing.
本発明の半導体装置は、容器の一部を形成するセラミッ
ク基板と、このセラミック基板の容器内側の所定の位置
に搭載された半導体回路部と、前記セラミック基板に突
出して設けられ半導体回路部への入力信号を外部から取
込むための入力信号用の外部リードピンと、この外部り
一１〜ピンと接続し前記セラミック基板の容器内側の所
定の位置に形成された内部電極と、この内部電極と油泥
半導体回路部の対応する電極とを接続する金属細線と、
前記内部電極の金属細線接続部から最短使用波長の１／
４以内の部分と接続し前記セラミック基板の表面の所定
の位置に形成された終端配線と、前記セラミック基板に
突出して設けられ外部の基準電位点と接続するための基
準電位用の外部リートビンと、この外部リードピンと接
続し前記セラミック基板の表面の前記終端配線と隣接し
て形成された基準電位電極と、この基準電位電極と前記
終端配線との間に接続された終端抵抗とを有している。A semiconductor device of the present invention includes a ceramic substrate forming a part of a container, a semiconductor circuit section mounted on the ceramic substrate at a predetermined position inside the container, and a semiconductor circuit section provided protruding from the ceramic substrate. an external lead pin for an input signal for taking in an input signal from the outside; an internal electrode connected to this external lead pin and formed at a predetermined position inside the container of the ceramic substrate; A thin metal wire connecting the corresponding electrode of the circuit section,
1/1 of the shortest wavelength used from the thin metal wire connection part of the internal electrode.
a termination wiring formed at a predetermined position on the surface of the ceramic substrate and connected to a portion within 4; an external Rietbin for a reference potential provided protruding from the ceramic substrate for connection to an external reference potential point; A reference potential electrode connected to the external lead pin and formed adjacent to the termination wiring on the surface of the ceramic substrate, and a termination resistor connected between the reference potential electrode and the termination wiring. .
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第１図（ａ、）、（ｂ）はそれぞれ本発明の第１の実施
例を示す部分断面斜視図及び拡大断面側面図である。FIGS. 1(a) and 1(b) are a partially sectional perspective view and an enlarged sectional side view showing a first embodiment of the present invention, respectively.
この実施例は、容器の−・部を形成するセラミック基板
１と、このセラミック基板１の容器内側の所定の位置に
搭載された半導体回路部２と、セラミック基板１に突出
して設（つられ半導体回路部２への入力信号を外部から
取込むための複数の久方信号用の外部り−Ｉ・ピン４Ｂ
と、これら各外部リードピン４Ｂとそれぞれ対応して接
続しセラミック基板１の容器内側の所定の位置に形成さ
れた複数の内部電極１１と、これら各内部電極］］と半
導体回路部２の対応する電極とを接続する複数の金属細
線３と、各内部電極］１の金属細線接続部から最短使用
波長の１−７４以内の部分とそれぞれ対応して接続しセ
ラミック基板１の表面の所定の位置にそれぞれ形成され
た複数の終端配線１３と、セラミック基板］に突出して
設けられ外部の基準電位点と接続するための基準電位用
の外部リードピン４八と、この外部リードピン４Ａと接
続しセラミック基板］の表面の周辺部に各終端配線１３
と隣接して形成された基準電位電極１２と、この基準電
位電極１２と各終端配線１３との間にそれぞれ接続され
た複数のチップ抵抗の終端抵抗５とを有する構造となっ
ている。This embodiment includes a ceramic substrate 1 forming a part of the container, a semiconductor circuit section 2 mounted on the ceramic substrate 1 at a predetermined position inside the container, and a semiconductor circuit section 2 protruding from the ceramic substrate 1 (suspended). External I/pin 4B for multiple long signals to take in input signals to section 2 from the outside.
, a plurality of internal electrodes 11 formed at predetermined positions inside the container of the ceramic substrate 1 and correspondingly connected to each of these external lead pins 4B, and corresponding electrodes of the semiconductor circuit section 2. A plurality of thin metal wires 3 connecting the inner electrodes 1 and 2 are connected in correspondence with the portions within 1-74 of the shortest wavelength used from the thin metal wire connection portion of the internal electrodes 1, and are respectively connected to predetermined positions on the surface of the ceramic substrate 1. The plurality of termination wirings 13 formed, external lead pins 48 for reference potential protruding from the ceramic substrate for connection to an external reference potential point, and the surface of the ceramic substrate connected to the external lead pins 4A. Each termination wiring 13 is placed around the periphery of
The structure includes a reference potential electrode 12 formed adjacent to the reference potential electrode 12 and a plurality of terminal resistors 5 of chip resistors connected between the reference potential electrode 12 and each terminal wiring 13, respectively.
この実施例においては、終端抵抗５を接続する終端配線
１３が、内部電極１］の金属細線接続部からの距離が最
短使用波長の１／／４以内のところと接続されているの
で、特性インピータンスの整合不良や入力信号の伝搬不
良の発生を防止することができ、また半導体回路部２の
信号入力端の電極と入力信号用の外部リードピン４Ｂと
は１対１であるので、高集積化が容易となる。更にまた
、セラミック基板１の空きスペースを利用して終端抵抗
５か取付りられているので、実装用のプリント基板に終
端抵抗を取イ」ける必要がなく、実装用のプリン１〜基
板の面積を縮小することができる。In this embodiment, the terminating wire 13 that connects the terminating resistor 5 is connected within 1/4 of the shortest usage wavelength from the thin metal wire connection part of the internal electrode 1, so that the characteristic impedance It is possible to prevent the occurrence of mismatching of the transistors and poor propagation of input signals, and since the electrode at the signal input end of the semiconductor circuit section 2 and the external lead pin 4B for input signals are in a one-to-one relationship, high integration can be achieved. becomes easier. Furthermore, since the terminating resistor 5 is mounted using the empty space of the ceramic substrate 1, there is no need to remove the terminating resistor on the printed circuit board for mounting, and the area of the printed circuit board 1 for mounting is reduced. can be reduced.
第２図（ａ）、（ｂ）はそれぞれ本発明の第２の実施例
を示す部分断面斜視図及び拡大断面側面図である。FIGS. 2(a) and 2(b) are a partially sectional perspective view and an enlarged sectional side view showing a second embodiment of the present invention, respectively.
この実施例は、各終端抵抗５Ａを、セラミック基板１の
表面の各終端配線１３と基準電位電極１２との間に、真
空蒸着法又はスパッタリング法により薄ｊ摸抵抗で形成
したものである。In this embodiment, each terminating resistor 5A is formed as a thin resistor between each terminating wiring 13 and the reference potential electrode 12 on the surface of the ceramic substrate 1 by vacuum evaporation or sputtering.
この実施例においては、第１の実施例のようなチップ抵
抗取付は等の工程が不要になるという利点がある。This embodiment has the advantage that the process of attaching the chip resistor as in the first embodiment is not necessary.
第３図は本発明の第３の実施例を示す部分断面斜視図で
ある。FIG. 3 is a partially sectional perspective view showing a third embodiment of the present invention.
この実施例は、基準電位電極１２Ａが、各終端配線１３
の周囲を取囲こむようにコプレーナ−型構造に形成され
ており、各終端配線１３間のクロスドースを低減するこ
とができるという利点がある。In this embodiment, the reference potential electrode 12A is
It is formed in a coplanar structure so as to surround the periphery of the terminal wiring 13, and has the advantage that cross-dose between the respective terminal wirings 13 can be reduced.
なお、これら実施例においては、各終端配線１３をマイ
クロス１ヘリツブ構造とすることかでき、こうすること
により、更に特性インピーダンスの整合等を良くするこ
とができる。In these embodiments, each terminal wiring 13 can have a micros one-heritage structure, and by doing so, matching of characteristic impedance, etc. can be further improved.
以上説明１だように本発明は、セラミック基板の表面に
、内部電極の金属細線接続部の近くと接続する終端配線
と基準電位電極とを形成し、これら終端配線と基準電位
電極との間に終端抵抗を接続する構成とすることにより
、特性インピータンスの整合不良、入力信号の伝搬不良
の発生を防止することができ、また入力信号用の外部リ
ードピンと半導体回路部の入力端の電極とは１対］で済
むので高集積化が容易となり、しかも従来のように実装
用のプリント基板に終端抵抗を取付ける必要がないので
、実装用のプリント基板の面積を縮小することができる
効果かある。As explained in Explanation 1 above, the present invention forms a termination wiring and a reference potential electrode on the surface of a ceramic substrate to be connected to the vicinity of the thin metal wire connection part of the internal electrode, and forms a connection between the termination wiring and the reference potential electrode. By connecting a terminating resistor, it is possible to prevent characteristic impedance matching failures and input signal propagation failures, and to connect the external lead pins for input signals and the electrodes at the input end of the semiconductor circuit section. Since only one pair is required, it is easy to achieve a high level of integration, and since there is no need to attach a termination resistor to the printed circuit board for mounting as in the conventional case, the area of the printed circuit board for mounting can be reduced.
第１図（ａ）、（ｂ）はそれぞれ本発明の第１の実施例
を示す部分断面斜視図及び拡大断面側面図、第２図（ａ
）、（ｂ）はそれぞれ本発明の第２の実施例を示す部分
断面斜視図及び拡大断面側面図、第３図は本発明の第３
の実施例を示す部分断面斜視図、第４図及び第５図はそ
れぞれ従来の半導体装置の第１及び第２の例とその終端
抵抗の取付方法を説明するための断面側面図である。
１．１Ａ、ＩＢ・・・セラミック基板、２・・・半導体
回路部、３・・・金属細線、７１１Ａ〜４ｃ・・・外部
リードピン、５，５Ａ 、５Ｂ・・・終端抵抗、６．６
Ａ。
６Ｂ・・・キャップ、１１．ＩＩＡ 、］、１．８・・
・内部電極、１２．１２Ａ・・・基準電位電極、１３・
・・終端配線、１００Ａ〜１００ ｃ−半導体装置、２
００゜２００Ａ・・・プリント基板、２０１−．２０］
、Ａ・・・プリン１〜配線。FIGS. 1(a) and 1(b) are a partially sectional perspective view and an enlarged sectional side view showing a first embodiment of the present invention, and FIG.
) and (b) are a partial cross-sectional perspective view and an enlarged cross-sectional side view showing the second embodiment of the present invention, respectively, and FIG. 3 is a third embodiment of the present invention.
FIGS. 4 and 5 are partial cross-sectional perspective views showing the embodiment, and FIGS. 4 and 5 are cross-sectional side views for explaining first and second examples of conventional semiconductor devices and a method of attaching a terminating resistor, respectively. 1.1A, IB...Ceramic board, 2...Semiconductor circuit section, 3...Metal thin wire, 711A-4c...External lead pin, 5,5A, 5B...Terminal resistor, 6.6
A. 6B...Cap, 11. IIA, ], 1.8...
・Internal electrode, 12.12A...Reference potential electrode, 13・
・Terminal wiring, 100A to 100c-semiconductor device, 2
00°200A...Printed circuit board, 201-. 20]
, A... Pudding 1 ~ Wiring.
Claims (1)
ラミック基板の容器内側の所定の位置に搭載された半導
体回路部と、前記セラミック基板に突出して設けられ半
導体回路部への入力信号を外部から取込むための入力信
号用の外部リードピンと、この外部リードピンと接続し
前記セラミック基板の容器内側の所定の位置に形成され
た内部電極と、この内部電極と前記半導体回路部の対応
する電極とを接続する金属細線と、前記内部電極の金属
細線接続部から最短使用波長の１／４以内の部分と接続
し前記セラミック基板の表面の所定の位置に形成された
終端配線と、前記セラミック基板に突出して設けられ外
部の基準電位点と接続するための基準電位用の外部リー
ドピンと、この外部リードピンと接続し前記セラミック
基板の表面の前記終端配線と隣接して形成された基準電
位電極と、この基準電位電極と前記終端配線との間に接
続された終端抵抗とを有することを特徴とする半導体装
置。 ２、終端抵抗がチップ抵抗である請求項１記載の半導
体装置。 ３、終端抵抗がセラミック基板の表面の終端配線と基
準電位電極との間に形成された薄膜抵抗である請求項１
記載の半導体装置。 ４、終端配線がセラミック基板の表面に複数形成され
、基準電位電極が前記各終端配線の周囲を取囲むように
形成された請求項１記載の半導体装置。 ５、終端配線がマイクロストリップ構造である請求項
１記載の半導体装置。[Claims] 1. A ceramic substrate forming a part of the container, a semiconductor circuit section mounted on the ceramic substrate at a predetermined position inside the container, and a semiconductor circuit section provided protruding from the ceramic substrate. an external lead pin for an input signal for taking in an input signal from the outside; an internal electrode connected to the external lead pin and formed at a predetermined position inside the container of the ceramic substrate; and the internal electrode and the semiconductor circuit section. a thin metal wire that connects the corresponding electrode of the internal electrode, and a termination wiring formed at a predetermined position on the surface of the ceramic substrate and connected to a portion within 1/4 of the shortest wavelength used from the thin metal wire connection portion of the internal electrode. , a reference potential external lead pin protruding from the ceramic substrate for connection to an external reference potential point, and a reference connected to the external lead pin and formed adjacent to the termination wiring on the surface of the ceramic substrate. A semiconductor device comprising: a potential electrode; and a termination resistor connected between the reference potential electrode and the termination wiring. 2. The semiconductor device according to claim 1, wherein the terminating resistor is a chip resistor. 3. Claim 1, wherein the terminating resistor is a thin film resistor formed between the terminating wiring on the surface of the ceramic substrate and the reference potential electrode.
The semiconductor device described. 4. The semiconductor device according to claim 1, wherein a plurality of termination wirings are formed on the surface of the ceramic substrate, and a reference potential electrode is formed to surround each of the termination wirings. 5. The semiconductor device according to claim 1, wherein the termination wiring has a microstrip structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20990590A JPH0493060A (en) | 1990-08-08 | 1990-08-08 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20990590A JPH0493060A (en) | 1990-08-08 | 1990-08-08 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0493060A true JPH0493060A (en) | 1992-03-25 |
Family
ID=16580596
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20990590A Pending JPH0493060A (en) | 1990-08-08 | 1990-08-08 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0493060A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7338792B2 (en) * | 2001-07-07 | 2008-03-04 | Degussa Ag | Process for the preparation of D-pantothenic acid and/or salts thereof |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61292359A (en) * | 1985-06-20 | 1986-12-23 | Nec Corp | Integrated circuit package |
-
1990
- 1990-08-08 JP JP20990590A patent/JPH0493060A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61292359A (en) * | 1985-06-20 | 1986-12-23 | Nec Corp | Integrated circuit package |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7338792B2 (en) * | 2001-07-07 | 2008-03-04 | Degussa Ag | Process for the preparation of D-pantothenic acid and/or salts thereof |
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