JPH0746711B2 - Chip carrier - Google Patents
Chip carrierInfo
- Publication number
- JPH0746711B2 JPH0746711B2 JP61251870A JP25187086A JPH0746711B2 JP H0746711 B2 JPH0746711 B2 JP H0746711B2 JP 61251870 A JP61251870 A JP 61251870A JP 25187086 A JP25187086 A JP 25187086A JP H0746711 B2 JPH0746711 B2 JP H0746711B2
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- substrate
- chip carrier
- external
- semiconductor integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19043—Component type being a resistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体集積回路、特に超高速論理素子を搭載す
るためのチップキャリアに関する。The present invention relates to a semiconductor integrated circuit, and more particularly to a chip carrier for mounting an ultra-high speed logic device.
半導体集積回路は一般に、チップキャリアに搭載して密
閉され、各種外部回路に実装される。このチップキャリ
アには、外部回路との電気接続に必要な外部電極が取り
付けられている。Semiconductor integrated circuits are generally mounted on a chip carrier, hermetically sealed, and mounted on various external circuits. External electrodes necessary for electrical connection with an external circuit are attached to the chip carrier.
ここで従来、チップキャリア上に搭載される半導体集積
回路チップの端子電極と、チップキャリアの外部電極と
の間は、ボンディングワイヤで接続されていた。その外
部電極やボンディングワイヤ等は、外部回路に実装され
たとき、その回路中の伝送線路として、その特性インピ
ーダンスを見た場合、全く不整合であった。従ってこれ
らは、浮遊したインダクタンスおよびキャパシタンスと
なっていた。しかし、従来これは無視できる程度のもの
で、特に問題とされていなかった。Here, conventionally, the terminal electrode of the semiconductor integrated circuit chip mounted on the chip carrier and the external electrode of the chip carrier are connected by a bonding wire. The external electrodes, bonding wires, etc., when mounted on an external circuit, were completely inconsistent when the characteristic impedance of the transmission line in the circuit was observed. Therefore, these were floating inductance and capacitance. However, this has hitherto been negligible and has not been a particular problem.
ところが、半導体集積回路技術の発達、並びにGaAs（ガ
リウムヒ素）など新素子の開発により、最近の論理素子
は超高速化されてきている。従って、従来の半導体集積
回路に用いられていたような、比較的遅いスイッチング
速度の論理回路の場合には問題とならなかった、チップ
キャリアの浮遊インダクタンスやキャパシタンスが問題
となってきている。However, due to the development of semiconductor integrated circuit technology and the development of new elements such as GaAs (gallium arsenide), recent logic elements have become ultra-high speed. Therefore, stray inductance or capacitance of the chip carrier has become a problem, which has not been a problem in the case of a logic circuit having a relatively slow switching speed, which is used in the conventional semiconductor integrated circuit.
一般に、論理回路の出力端子は低インピーダンスであ
り、入力端子は高インピーダンスであり、論理回路相互
間を接続する配線基板の信号線は、論理回路の出力端子
のインピーダンスに整合がとられている。従って、超高
速論理回路の出力端子から信号パルスが出力され配線基
板の信号線を伝送線路として受端の論理回路の入力端子
まで伝送される場合、まずチップキャリアの外部電極に
至るまでのボンディングワイヤや、これと外部電極とを
結ぶ接続導体のインピーダンスの不整合により波形歪を
生じる。それが伝搬されると、受端の論理回路の入力端
子でも波形歪とインピーダンス不整合による反射を生
じ、信号遅延や誤動作、あるいは発振を起こしたりして
しまう。Generally, an output terminal of a logic circuit has a low impedance, an input terminal has a high impedance, and a signal line of a wiring board connecting the logic circuits to each other is matched with an impedance of an output terminal of the logic circuit. Therefore, when a signal pulse is output from the output terminal of the ultra-high speed logic circuit and is transmitted as a transmission line to the input terminal of the logic circuit at the receiving end, the bonding wire that reaches the external electrode of the chip carrier is first used. Also, waveform distortion occurs due to the impedance mismatch of the connection conductor connecting this and the external electrode. When it is propagated, reflection occurs due to waveform distortion and impedance mismatch even at the input terminal of the logic circuit at the receiving end, causing signal delay, malfunction, or oscillation.
本発明は、以上の点に着目してなされたもので、周辺回
路とのインピーダンスの整合性の良いチップキャリアを
提供することを目的とするものである。The present invention has been made in view of the above points, and an object thereof is to provide a chip carrier having good impedance matching with peripheral circuits.
本発明のチップキャリアは、半導体集積回路チップを載
せる基盤と、その基板に設けられて外部回路との接続を
行う外部電極と、この外部電極から上記半導体集積回路
に向かって上記基板上を延長された接続電極と、この接
続電極と上記半導体集積回路の端子電極との間を接続す
るボンディングワイヤと、上記基板に上記接続電極と電
気的に絶縁されて設けられ、その接続電極との間に所定
の特性インピーダンスを形成するグランド層と、上記特
性インピーダンスに整合する抵抗値を持つ抵抗値と、こ
の抵抗層の一端と前記接続電極との間およびこの抵抗層
の他端と前記グランド層との間をそれぞれ電気接続する
手段を設けたことを特徴とするものである。The chip carrier of the present invention includes a base on which a semiconductor integrated circuit chip is mounted, external electrodes provided on the substrate for connecting to an external circuit, and extended on the substrate from the external electrode toward the semiconductor integrated circuit. A connecting electrode, a bonding wire connecting the connecting electrode and the terminal electrode of the semiconductor integrated circuit, and a predetermined distance between the connecting electrode and the connecting electrode, which are electrically insulated from the connecting electrode. And a resistance value having a resistance value matching the characteristic impedance, between one end of the resistance layer and the connection electrode, and between the other end of the resistance layer and the ground layer. It is characterized in that means for electrically connecting each of them are provided.
本発明おいては、チップキャリアの基板に、接続電極と
電気的に絶縁されて設けられ、その接続電極との間に所
定の特性インピーダンスを形成するグランド層を設けた
ので、チップキャリア内の信号伝送線路のインピーダン
ス整合を行うことができる。In the present invention, since the substrate of the chip carrier is provided with a ground layer that is electrically insulated from the connection electrode and that forms a predetermined characteristic impedance with the connection electrode, the signal in the chip carrier is Impedance matching of the transmission line can be performed.
さらに、上記接続電極と上記グランド層との間に、スル
ーホールを介して、上記特性インピーダンスに整合する
抵抗値を持つ抵抗層を接続したので、基板を大型化する
ことなく信号伝送線路の整合終端を実現することができ
る。Further, since the resistance layer having a resistance value matching the characteristic impedance is connected between the connection electrode and the ground layer through the through hole, the matching termination of the signal transmission line can be achieved without increasing the size of the substrate. Can be realized.
〔実施例〕 次に、本発明について図面を参照して説明する。EXAMPLES Next, the present invention will be described with reference to the drawings.
第１図は、本発明のチップキャリアの一実施例を示す部
分断面図で、第２図はその外観斜視図である。FIG. 1 is a partial sectional view showing an embodiment of the chip carrier of the present invention, and FIG. 2 is an external perspective view thereof.
本発明のチップキャリアは、第２図に示すように、基板
１上に半導体集積回路チップを搭載して気密封止したも
のである。この基板１の側面には、多数の凹溝が形成さ
れ、外部回路との接続を行う外部電極２が設けられてい
る。また、基板１の上面には、半導体集積回路チップを
気密に覆う蓋３が取り付けられている。As shown in FIG. 2, the chip carrier of the present invention has a semiconductor integrated circuit chip mounted on a substrate 1 and hermetically sealed. A large number of concave grooves are formed on the side surface of the substrate 1, and an external electrode 2 for connecting to an external circuit is provided. Further, a lid 3 that hermetically covers the semiconductor integrated circuit chip is attached to the upper surface of the substrate 1.
さて、第１図の断面図に示すように、基板１は多層構造
とされ、中央の凹部に半導体集積回路チップ４が接着固
定されている。基板１の周縁部において、その最上層５
は、蓋３を接着固定するための上部絶縁層で、その下側
に、接続電極６と、中間絶縁層７と、グランド層８と、
底部絶縁層９が順に設けられている。また、底部絶縁層
８の下面には、抵抗層12が形成されている。外部電極２
は、この基板１の側面から下面に回り込むように形成さ
れた導電体層からなり、これから半導体集積回路チップ
４に向かって、接続電極６が延長されている。接続電極
６の一端は、ボンディングワイヤ10によって、半導体集
積回路チップ４の端子電極11と接続されている。グラン
ド層８は、中間絶縁層７と底部絶縁層９との間に形成さ
れた導体層である。このグランド層８と接続電極６との
間には、これらによって、実装される外部回路と整合す
る所定の特性インピーダンスが形成されている。そこ
で、特定の厚さの中間絶縁層７が設けられ、グランド層
８の面積もこれに対応するように選定されている。Now, as shown in the cross-sectional view of FIG. 1, the substrate 1 has a multi-layer structure, and the semiconductor integrated circuit chip 4 is adhesively fixed to the central recess. In the peripheral portion of the substrate 1, the uppermost layer 5
Is an upper insulating layer for adhesively fixing the lid 3, and on the lower side thereof, the connection electrode 6, the intermediate insulating layer 7, the ground layer 8,
The bottom insulating layer 9 is provided in order. A resistance layer 12 is formed on the lower surface of the bottom insulating layer 8. External electrode 2
Is composed of a conductor layer formed so as to wrap around from the side surface to the lower surface of the substrate 1, and the connection electrode 6 is extended from this to the semiconductor integrated circuit chip 4. One end of the connection electrode 6 is connected to the terminal electrode 11 of the semiconductor integrated circuit chip 4 by the bonding wire 10. The ground layer 8 is a conductor layer formed between the intermediate insulating layer 7 and the bottom insulating layer 9. A predetermined characteristic impedance matching the external circuit to be mounted is formed between the ground layer 8 and the connection electrode 6 by these. Therefore, the intermediate insulating layer 7 having a specific thickness is provided, and the area of the ground layer 8 is also selected to correspond to this.
一方、このグランド層８と、接続電極６とは、スルーホ
ール13と14を介して抵抗層12と電気接続されている。こ
の抵抗層12は、上記特性インピーダンスに整合する抵抗
値を有する抵抗体により形成されている。この抵抗層12
の両端に接続されたスルーホール13、14の抵抗値は十分
低いものとする。なお、この抵抗層12は、上部絶縁層５
の内部に埋設されていても、また、中間絶縁層７の上面
に形成されていてもよく、その他適当なスペースに形成
されていればよい。この場合、抵抗層12と接続電極６や
グランド層８の間は適当な手段で電気接続される。On the other hand, the ground layer 8 and the connection electrode 6 are electrically connected to the resistance layer 12 through the through holes 13 and 14. The resistance layer 12 is formed of a resistor having a resistance value that matches the characteristic impedance. This resistive layer 12
It is assumed that the resistance values of the through holes 13 and 14 connected to both ends of the are sufficiently low. The resistance layer 12 is the upper insulating layer 5
Of the intermediate insulating layer 7 may be buried in the inside of the above, or may be formed on the upper surface of the intermediate insulating layer 7 as long as it is formed in an appropriate space. In this case, the resistance layer 12 is electrically connected to the connection electrode 6 and the ground layer 8 by an appropriate means.
以上の構成のチップキャリアの、外部電極２を、図示し
ない外部回路の配線基板上の回路パタンに電気接続する
と、この外部回路の特性インピーダンスと、チップキャ
リアの接続電極６の特性インピーダンスが整合する。ま
た、抵抗層12は、接続電極６を特性インピーダンスで終
端する。このため、この部分でのインピーダンスミスマ
ッチによる反射波の発生等が抑制される。When the external electrode 2 of the chip carrier having the above configuration is electrically connected to a circuit pattern on a wiring board of an external circuit (not shown), the characteristic impedance of this external circuit matches the characteristic impedance of the connection electrode 6 of the chip carrier. Further, the resistance layer 12 terminates the connection electrode 6 with a characteristic impedance. Therefore, generation of a reflected wave due to impedance mismatch in this portion is suppressed.
また、抵抗層12を設けておけば、終端抵抗を外部回路に
設ける必要はない。Further, if the resistance layer 12 is provided, it is not necessary to provide the terminating resistor in the external circuit.
以上説明したように本発明は、チップキャリアの接続電
極を所定の特性インピーダンスに整合させ、さらに、基
板の所定個所に形成した終端抵抗で入力端子を整合終端
したので、波形歪や反射をなくし、信号遅延や誤動作を
なくした超高速論理回路を実現できる効果がある。As described above, the present invention matches the connection electrode of the chip carrier to a predetermined characteristic impedance, and further, the input terminal is matched and terminated by a terminating resistor formed at a predetermined portion of the substrate, thereby eliminating waveform distortion and reflection, This has the effect of realizing an ultrahigh-speed logic circuit that eliminates signal delay and malfunction.
また、基板下面に終端抵抗を設けると、その形成が容易
で、トリミング等により高精度の整合終端が形成でき
る。さらに、この抵抗は、スペースをとらず、外部回路
の簡素化を図ることもできる。Further, when a terminating resistor is provided on the lower surface of the substrate, the terminating resistor can be easily formed and a highly accurate matching terminating can be formed by trimming or the like. Furthermore, this resistor does not take up space and can also simplify the external circuit.
【図面の簡単な説明】 第１図は本発明のチップキャリアの要部断面図、第２図
は本発明のチップキャリアの外部斜視図である。 １……基板、２……外部電極、３……蓋、４……半導体
集積回路チップ、６……接続電極、８……グランド層、
10……ボンディングワイヤ、11……端子電極、12……抵
抗層、13、14……スルーホール。BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a sectional view of an essential part of a chip carrier of the present invention, and FIG. 2 is an external perspective view of the chip carrier of the present invention. 1 ... Substrate, 2 ... External electrode, 3 ... Lid, 4 ... Semiconductor integrated circuit chip, 6 ... Connection electrode, 8 ... Ground layer,
10 …… bonding wire, 11 …… terminal electrode, 12 …… resistive layer, 13,14 …… through hole.
Claims (1)
の基板に設けられて外部回路との接続を行う外部電極
と、この外部電極から前記半導体集積回路に向かって前
記基板上を延長された接続電極と、この接続電極と前記
半導体集積回路の端子電極との間を接続するボンディン
グワイヤと、前記基板に前記接続電極と電気的に絶縁さ
れて設けられ、その接続電極との間に所定の特性インピ
ーダンスを形成するグランド層と、前記特性インピーダ
ンスに整合する抵抗値を持つ抵抗層と、この抵抗層の一
端と、前記接続電極との間およびこの抵抗層の他端と、
前記グランド層との間をそれぞれ電気接続する手段とを
設けたことを特徴とするチップキャリア。1. A substrate on which a semiconductor integrated circuit chip is mounted, external electrodes provided on the substrate for connecting to an external circuit, and a connection extended from the external electrode toward the semiconductor integrated circuit on the substrate. An electrode, a bonding wire connecting the connection electrode and a terminal electrode of the semiconductor integrated circuit, and the connection electrode, which is provided on the substrate and electrically insulated from the connection electrode, have predetermined characteristics. A ground layer forming an impedance, a resistance layer having a resistance value matching the characteristic impedance, one end of the resistance layer, and between the connection electrode and the other end of the resistance layer,
A chip carrier provided with means for electrically connecting to the ground layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61251870A JPH0746711B2 (en) | 1986-10-24 | 1986-10-24 | Chip carrier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61251870A JPH0746711B2 (en) | 1986-10-24 | 1986-10-24 | Chip carrier |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63107129A JPS63107129A (en) | 1988-05-12 |
| JPH0746711B2 true JPH0746711B2 (en) | 1995-05-17 |
Family
ID=17229157
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61251870A Expired - Lifetime JPH0746711B2 (en) | 1986-10-24 | 1986-10-24 | Chip carrier |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0746711B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03195049A (en) * | 1989-12-25 | 1991-08-26 | Hitachi Ltd | Semiconductor integrated circuit device |
| JPH0574972A (en) * | 1991-09-13 | 1993-03-26 | Nippon Avionics Co Ltd | Ic package |
| JPH11177189A (en) * | 1997-12-12 | 1999-07-02 | Fujitsu Ltd | Terminal structure of wiring on printed board |
-
1986
- 1986-10-24 JP JP61251870A patent/JPH0746711B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63107129A (en) | 1988-05-12 |
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