JP2001168238A - Package for high-frequency circuit - Google Patents
Package for high-frequency circuitInfo
- Publication number
- JP2001168238A JP2001168238A JP34723499A JP34723499A JP2001168238A JP 2001168238 A JP2001168238 A JP 2001168238A JP 34723499 A JP34723499 A JP 34723499A JP 34723499 A JP34723499 A JP 34723499A JP 2001168238 A JP2001168238 A JP 2001168238A
- Authority
- JP
- Japan
- Prior art keywords
- lead
- gnd
- signal
- frequency signal
- frequency
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/4901—Structure
- H01L2224/4903—Connectors having different sizes, e.g. different diameters
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
Landscapes
- Waveguides (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、高周波信号の伝送
特性を向上した高周波回路用パッケージに関するもので
ある。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-frequency circuit package having improved high-frequency signal transmission characteristics.
【０００２】[0002]
【従来の技術】従来の高周波回路用パッケージは、例え
ば図８及び図９に示すように、チップ１０を収容したパ
ッケージ１１の両側部に高周波信号線用のリード（以下
「信号リード」という）１２とグランド線用のリード
（以下「ＧＮＤリード」という）１３を列設し、各リー
ド１２，１３を外部回路基板１４の配線パターンに接続
するようにしている。この場合、パッケージ１１の入出
力端子台１５に形成した高周波信号線１６の特性インピ
ーダンスを所定の設計値に収めるために、図５（ａ）に
示すように、高周波信号線１６の両側にＧＮＤ線１７を
並行に形成している。従って、信号リード１２に隣接し
てＧＮＤリード１３が位置している。また、各リード１
２，１３のピッチは通常２．５４ｍｍとなっている。2. Description of the Related Art As shown in FIGS. 8 and 9, for example, a conventional high-frequency circuit package has leads for high-frequency signal lines (hereinafter referred to as "signal leads") 12 on both sides of a package 11 containing a chip 10. FIG. And leads 13 for ground lines (hereinafter referred to as “GND leads”), and each lead 12, 13 is connected to a wiring pattern of an external circuit board 14. In this case, in order to keep the characteristic impedance of the high-frequency signal line 16 formed on the input / output terminal block 15 of the package 11 at a predetermined design value, as shown in FIG. 17 are formed in parallel. Therefore, the GND lead 13 is located adjacent to the signal lead 12. In addition, each lead 1
The pitch of 2, 13 is usually 2.54 mm.
【０００３】[0003]
【発明が解決しようとする課題】近年の電子機器は、高
周波化が進み、例えば１０ＧＨｚ程度の高周波信号を取
り扱う場合がある。しかし、信号の高周波化が進むに従
って、パッケージ１１と外部回路基板１４とのリード接
合部における特性インピーダンスの不整合の影響が大き
くなり、その影響で、高周波信号の反射が増加して、高
周波信号の伝送特性が悪化する。In recent years, the frequency of electronic devices has been increasing, and there are cases where high-frequency signals of, for example, about 10 GHz are handled. However, as the frequency of the signal increases, the influence of the characteristic impedance mismatch at the lead joint between the package 11 and the external circuit board 14 increases, and as a result, the reflection of the high frequency signal increases, and Transmission characteristics deteriorate.
【０００４】ところで、リード接合部における特性イン
ピーダンスの不整合は、リード１２，１３のピッチが
２．５４ｍｍと大きいことが原因と思われる。つまり、
リード１２，１３のピッチが大きいと、図５（ａ）に示
すように、リード接合部近辺におけるＧＮＤ電流の経路
が長くなるため、高周波信号線−ＧＮＤ線のループイン
ダクタンスが増加すると共に、信号リード１２とこれに
隣接するＧＮＤリード１３との間の容量結合が低下し、
これらループインダクタンスの増加と容量結合の低下に
よってリード接合部で特性インピーダンスの不整合が発
生するものと考えられる。The characteristic impedance mismatch at the lead joint is considered to be caused by the pitch of the leads 12 and 13 being as large as 2.54 mm. That is,
If the pitch of the leads 12 and 13 is large, as shown in FIG. 5A, the path of the GND current in the vicinity of the lead joint becomes longer, so that the loop inductance of the high-frequency signal line-GND line increases and the signal lead increases. 12 and the GND lead 13 adjacent thereto are reduced in capacitive coupling,
It is considered that the characteristic impedance mismatch occurs at the lead junction due to the increase in the loop inductance and the decrease in the capacitive coupling.
【０００５】本発明はこのような事情を考慮してなされ
たものであり、従ってその目的は、リード接合部におけ
る特性インピーダンスの不整合による高周波信号の反射
を少なくすることができ、高周波信号の伝送特性を向上
することができる高周波回路用パッケージを提供するこ
とにある。SUMMARY OF THE INVENTION The present invention has been made in view of such circumstances, and it is therefore an object of the present invention to reduce the reflection of a high-frequency signal due to mismatching of characteristic impedance at a lead joint, and to transmit a high-frequency signal. An object of the present invention is to provide a high-frequency circuit package that can improve characteristics.
【０００６】[0006]
【課題を解決するための手段】上記目的を達成するため
に、本発明の請求項１の高周波回路用パッケージは、高
周波信号線用のリード（信号リード）とグランド線用の
リード（ＧＮＤリード）との間隔を他のリードの間隔よ
りも狭くすることで、リード接合部近辺におけるＧＮＤ
電流の経路を短くしている。これにより、高周波信号線
−ＧＮＤ線のループインダクタンスが減少すると共に、
信号リードとこれに隣接するＧＮＤリードとの間の容量
結合が増加し、これらループインダクタンスの減少と容
量結合の増加によってリード接合部における特性インピ
ーダンスの不整合が少なくなり、高周波信号の反射が少
なくなる。In order to achieve the above object, a high frequency circuit package according to the first aspect of the present invention comprises a lead for a high frequency signal line (a signal lead) and a lead for a ground line (a GND lead). Is narrower than the distance between other leads, so that the GND near the lead joint is reduced.
The current path is shortened. This reduces the loop inductance of the high-frequency signal line-GND line, and
The capacitive coupling between the signal lead and the adjacent GND lead increases, and the reduction of the loop inductance and the increase of the capacitive coupling reduce the characteristic impedance mismatch at the lead joint and reduce the reflection of high-frequency signals. .
【０００７】更に、請求項２のように、信号リードの幅
をＧＮＤリードの幅よりも細くすると良い。このように
すれば、信号リードのパッド部の特性インピーダンスを
設計値に維持しながら、リードの間隔を狭くすることが
可能となる。Further, it is preferable that the width of the signal lead is smaller than the width of the GND lead. By doing so, it is possible to narrow the lead interval while maintaining the characteristic impedance of the pad portion of the signal lead at the design value.
【０００８】[0008]
【発明の実施の形態】以下、本発明の一実施形態を図１
〜図５に基づいて説明する。まず、図１〜図４に基づい
て高周波回路用パッケージ全体の構成を説明する。パッ
ケージ２１は、金属ベース２２上に四角枠状のメタルウ
ォール２３がろう付け等により固定され、このメタルウ
ォール２３の両側部に絶縁体製の入出力端子台２４がろ
う付け等により固定されている。入出力端子台２４に
は、高周波信号線２５とＧＮＤ線（グランド線）２６と
が導体印刷パターンで並行に形成され、これらの高周波
信号線２５とＧＮＤ線２６には、それぞれ信号リード２
７とＧＮＤリード２８がろう付け等により接合されてい
る。高周波信号線２５とＧＮＤ線２６は、パッケージ２
１内に収納されたチップ２９にボンディングワイヤ３０
によって接続されている。このパッケージ２１の信号リ
ード２７とＧＮＤリード２８は、外部回路基板３２の高
周波信号線３３とＧＮＤ線３４に接合される。尚、パッ
ケージ２１の上面開口はメタルカバー３１で封止されて
いる。DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIG.
This will be described with reference to FIG. First, the configuration of the entire high-frequency circuit package will be described with reference to FIGS. In the package 21, a square frame-shaped metal wall 23 is fixed on a metal base 22 by brazing or the like, and an input / output terminal block 24 made of an insulator is fixed to both sides of the metal wall 23 by brazing or the like. . On the input / output terminal block 24, a high-frequency signal line 25 and a GND line (ground line) 26 are formed in parallel with a conductor print pattern, and the high-frequency signal line 25 and the GND line 26 are connected to the signal leads 2 respectively.
7 and the GND lead 28 are joined by brazing or the like. The high-frequency signal line 25 and the GND line 26 are
1 and the bonding wire 30
Connected by The signal lead 27 and the GND lead 28 of the package 21 are joined to the high-frequency signal line 33 and the GND line 34 of the external circuit board 32. The upper opening of the package 21 is sealed with a metal cover 31.
【０００９】高周波信号線２５の特性インピーダンスを
所定の設計値に収めるために、図５（ｂ）に示すよう
に、高周波信号線２５の両側にＧＮＤ線２６が並行に形
成されている。従来は、図５（ａ）に示すように、信号
リード１２とこれに隣接するＧＮＤリード１３のピッチ
は２．５４ｍｍであったが、本実施形態では、図５
（ｂ）に示すように、信号リード２７とＧＮＤリード２
８との間隔を他のリードの間隔よりも狭くして、リード
２７，２８のピッチを例えば０．６〜２．０ｍｍ（本実
施形態では１ｍｍ）に設定している。更に、信号リード
２７の幅をＧＮＤリード２８の幅よりも細くして、信号
リード２７の幅を例えば０．１〜０．４ｍｍに設定して
いる（ＧＮＤリード２８の幅は例えば０．５ｍｍであ
る）。In order to keep the characteristic impedance of the high-frequency signal line 25 at a predetermined design value, GND lines 26 are formed in parallel on both sides of the high-frequency signal line 25 as shown in FIG. Conventionally, as shown in FIG. 5A, the pitch between the signal lead 12 and the GND lead 13 adjacent to the signal lead 12 is 2.54 mm.
As shown in (b), the signal lead 27 and the GND lead 2
The pitch between the leads 27 and 28 is set to, for example, 0.6 to 2.0 mm (1 mm in the present embodiment) by making the interval between the leads 8 and 8 smaller than the interval between the other leads. Further, the width of the signal lead 27 is made smaller than the width of the GND lead 28, and the width of the signal lead 27 is set to, for example, 0.1 to 0.4 mm (the width of the GND lead 28 is, for example, 0.5 mm). is there).
【００１０】前述したように、従来は、図５（ａ）に示
すように、信号リード１２とこれに隣接するＧＮＤリー
ド１３のピッチが２．５４ｍｍと大きいため、リード接
合部近辺におけるＧＮＤ電流の経路が長くなっていた。
このため、高周波信号線−ＧＮＤ線のループインダクタ
ンスが増加すると共に、信号リード１２とこれに隣接す
るＧＮＤリード１３との間の容量結合が低下し、これら
ループインダクタンスの増加と容量結合の低下によって
リード接合部で特性インピーダンスの不整合が発生し、
その影響で、高周波信号の反射が増加して、高周波信号
の伝送特性が悪化する欠点があった。As described above, conventionally, as shown in FIG. 5A, the pitch between the signal lead 12 and the GND lead 13 adjacent to the signal lead 12 is as large as 2.54 mm. The route was long.
As a result, the loop inductance of the high-frequency signal line-GND line increases, and the capacitive coupling between the signal lead 12 and the GND lead 13 adjacent thereto decreases. Characteristic impedance mismatch occurs at the junction,
Due to the influence, there is a disadvantage that the reflection of the high-frequency signal increases and the transmission characteristics of the high-frequency signal deteriorate.
【００１１】これに対し、本実施形態では、図５（ｂ）
に示すように、信号リード２７の幅をＧＮＤリード２８
の幅よりも細くすると共に、信号リード２７とＧＮＤリ
ード２８との間隔（リードピッチ）を他のリードの間隔
よりも狭くしている。信号リード２７の幅をＧＮＤリー
ド２８の幅よりも細くすれば、信号リード２７とＧＮＤ
リード２８との間隔を狭くしても、信号リード２７のパ
ッド部の特性インピーダンスを設計値に維持することが
できる。また、信号リード２７とＧＮＤリード２８との
間隔を狭くすれば、リード接合部近辺におけるＧＮＤ電
流の経路が短くなるため、高周波信号線−ＧＮＤ線のル
ープインダクタンスが減少すると共に、信号リード２７
とこれに隣接するＧＮＤリード２８との間の容量結合が
増加し、これらループインダクタンスの減少と容量結合
の増加によってリード接合部の特性インピーダンスの不
整合が少なくなり、高周波信号の反射が少なくなる。On the other hand, in the present embodiment, FIG.
As shown in the figure, the width of the signal lead 27 is
, And the interval (lead pitch) between the signal lead 27 and the GND lead 28 is narrower than the interval between the other leads. If the width of the signal lead 27 is smaller than the width of the GND lead 28, the signal lead 27 and the GND
The characteristic impedance of the pad portion of the signal lead 27 can be maintained at the design value even if the distance between the lead 28 and the lead 28 is reduced. Also, if the distance between the signal lead 27 and the GND lead 28 is reduced, the path of the GND current near the lead joint is shortened, so that the loop inductance of the high-frequency signal line-GND line is reduced and the signal lead 27 is reduced.
The capacitive coupling between the lead and the adjacent GND lead 28 increases, and the reduction of the loop inductance and the increase of the capacitive coupling reduce the mismatch of the characteristic impedance of the lead joint and reduce the reflection of the high-frequency signal.
【００１２】本発明者らは、従来構造（リードピッチ
２．５４ｍｍ）と本実施形態の構造（リードピッチ１ｍ
ｍ）について、高周波信号の反射特性と通過特性を解析
したので、その解析結果を図６及び図７に示す。この解
析結果から明らかなように、本実施形態の構造は、従来
構造と比較して、１０ＧＨｚ以上の高周波数域でも、高
周波信号の反射が大幅に少なくなり、１０ＧＨｚ以上の
高周波信号を損失少なく伝送することができる。The present inventors have compared the conventional structure (lead pitch 2.54 mm) and the structure of this embodiment (lead pitch 1 m).
For m), the reflection characteristics and the transmission characteristics of the high-frequency signal were analyzed, and the analysis results are shown in FIGS. 6 and 7. As is evident from the analysis results, the structure of the present embodiment significantly reduces the reflection of the high-frequency signal even in the high frequency range of 10 GHz or higher, and transmits the high-frequency signal of 10 GHz or higher with less loss than the conventional structure. can do.
【００１３】尚、本実施形態では、高周波信号線２５の
両側にＧＮＤ線２６を形成したが、高周波信号線２５の
片側のみにＧＮＤ線２６を形成しても良く、また、信号
リード２７の幅をＧＮＤリード２８の幅と同一としても
良い。その他、本発明は、パッケージ２１の構造を変更
しても良い等、要旨を逸脱しない範囲内で種々変更して
実施できる。In the present embodiment, the GND lines 26 are formed on both sides of the high-frequency signal line 25. However, the GND lines 26 may be formed only on one side of the high-frequency signal line 25. May be the same as the width of the GND lead 28. In addition, the present invention can be implemented with various changes without departing from the gist, for example, the structure of the package 21 may be changed.
【００１４】[0014]
【発明の効果】以上の説明から明らかなように、本発明
の請求項１では、信号リードとＧＮＤリードとの間隔を
他のリードの間隔よりも狭くしたので、リード接合部近
辺におけるＧＮＤ電流の経路を短くすることができて、
リード接合部における特性インピーダンスの不整合を少
なくすることができ、高周波信号の反射を少なくして高
周波信号の伝送特性を向上することができる。As is apparent from the above description, in the first aspect of the present invention, the distance between the signal lead and the GND lead is smaller than the distance between the other leads, so that the GND current in the vicinity of the lead joint is reduced. I can shorten the route,
The mismatch of the characteristic impedance at the lead joint can be reduced, the reflection of the high-frequency signal can be reduced, and the transmission characteristics of the high-frequency signal can be improved.
【００１５】更に、請求項２では、信号リードの幅をＧ
ＮＤリードの幅よりも細くしたので、リードの間隔を狭
くしても、信号リードのパッド部の特性インピーダンス
を設計値に維持することができる。Further, according to claim 2, the width of the signal lead is G
Since the width is smaller than the width of the ND lead, the characteristic impedance of the pad portion of the signal lead can be maintained at the design value even if the interval between the leads is narrowed.
【図１】本発明の一実施形態を示す高周波回路用パッケ
ージの平面図FIG. 1 is a plan view of a high-frequency circuit package according to an embodiment of the present invention.
【図２】本実施形態の高周波回路用パッケージの縦断面
図FIG. 2 is a longitudinal sectional view of the high-frequency circuit package according to the embodiment;
【図３】パッケージの分解斜視図FIG. 3 is an exploded perspective view of a package.
【図４】入出力端子台の拡大斜視図FIG. 4 is an enlarged perspective view of an input / output terminal block.
【図５】（ａ）は従来構造のリード接続部周辺のＧＮＤ
電流の経路を示すリード接続部周辺の拡大平面図、
（ｂ）は本実施形態のリード接続部周辺のＧＮＤ電流の
経路を示すリード接続部周辺の拡大図FIG. 5 (a) is a diagram showing the GND around the lead connection portion of the conventional structure.
An enlarged plan view around a lead connection portion showing a current path;
(B) is an enlarged view of the periphery of the lead connection part showing the path of the GND current around the lead connection part of the present embodiment.
【図６】高周波信号の反射特性の解析結果を示す図FIG. 6 is a diagram showing an analysis result of reflection characteristics of a high-frequency signal.
【図７】高周波信号の通過特性の解析結果を示す図FIG. 7 is a diagram showing an analysis result of a transmission characteristic of a high-frequency signal.
【図８】従来の高周波回路用パッケージの平面図FIG. 8 is a plan view of a conventional high-frequency circuit package.
【図９】従来の高周波回路用パッケージの縦断面図FIG. 9 is a longitudinal sectional view of a conventional high-frequency circuit package.
２１…パッケージ、２４…入出力端子台、２５…高周波
信号線、２６…ＧＮＤ線（グランド線）、２７…信号リ
ード、２８…ＧＮＤリード、２９…チップ、３２…外部
回路基板、３３…高周波信号線、３４…ＧＮＤ線。21 ... package, 24 ... input / output terminal block, 25 ... high-frequency signal line, 26 ... GND line (ground line), 27 ... signal lead, 28 ... GND lead, 29 ... chip, 32 ... external circuit board, 33 ... high-frequency signal Line, 34 ... GND line.
Claims (2)
のリードとを隣接して設けた高周波回路用パッケージに
おいて、 前記高周波信号線用のリードと前記グランド線用のリー
ドとの間隔を他のリードの間隔よりも狭くしたことを特
徴とする高周波回路用パッケージ。In a high-frequency circuit package provided with a high-frequency signal line lead and a ground line lead adjacent to each other, the distance between the high-frequency signal line lead and the ground line lead is set to another distance. A high-frequency circuit package characterized in that the distance between the leads is narrower.
グランド線用のリードの幅よりも細くしたことを特徴と
する請求項１に記載の高周波回路用パッケージ。2. The high-frequency circuit package according to claim 1, wherein the width of the lead for the high-frequency signal line is smaller than the width of the lead for the ground line.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP34723499A JP2001168238A (en) | 1999-12-07 | 1999-12-07 | Package for high-frequency circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP34723499A JP2001168238A (en) | 1999-12-07 | 1999-12-07 | Package for high-frequency circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2001168238A true JP2001168238A (en) | 2001-06-22 |
Family
ID=18388832
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP34723499A Pending JP2001168238A (en) | 1999-12-07 | 1999-12-07 | Package for high-frequency circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2001168238A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010177364A (en) * | 2009-01-28 | 2010-08-12 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor package and packaging method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0685155A (en) * | 1992-09-01 | 1994-03-25 | Nec Corp | Molded semiconductor device |
| JPH06196578A (en) * | 1992-12-24 | 1994-07-15 | Shinko Electric Ind Co Ltd | Semicnductor device |
| JPH0936617A (en) * | 1995-07-20 | 1997-02-07 | Nippon Telegr & Teleph Corp <Ntt> | High frequency module |
| JPH10107200A (en) * | 1996-10-02 | 1998-04-24 | Hitachi Ltd | Semiconductor integrated circuit device |
-
1999
- 1999-12-07 JP JP34723499A patent/JP2001168238A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0685155A (en) * | 1992-09-01 | 1994-03-25 | Nec Corp | Molded semiconductor device |
| JPH06196578A (en) * | 1992-12-24 | 1994-07-15 | Shinko Electric Ind Co Ltd | Semicnductor device |
| JPH0936617A (en) * | 1995-07-20 | 1997-02-07 | Nippon Telegr & Teleph Corp <Ntt> | High frequency module |
| JPH10107200A (en) * | 1996-10-02 | 1998-04-24 | Hitachi Ltd | Semiconductor integrated circuit device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010177364A (en) * | 2009-01-28 | 2010-08-12 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor package and packaging method thereof |
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