JP4329702B2 - High frequency device equipment - Google Patents

High frequency device equipment Download PDF

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JP4329702B2
JP4329702B2 JP2005026593A JP2005026593A JP4329702B2 JP 4329702 B2 JP4329702 B2 JP 4329702B2 JP 2005026593 A JP2005026593 A JP 2005026593A JP 2005026593 A JP2005026593 A JP 2005026593A JP 4329702 B2 JP4329702 B2 JP 4329702B2
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frequency device
signal pattern
pattern
dielectric
dielectric layer
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JP2006216686A (en
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卓男 森本
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Mitsubishi Electric Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

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Description

この発明は、高周波用パッケージに高周波帯で用いられる高周波半導体素子や高周波回路等の高周波デバイスを搭載した高周波デバイス装置に関するものである。   The present invention relates to a high frequency device device in which a high frequency device such as a high frequency semiconductor element or a high frequency circuit used in a high frequency band is mounted on a high frequency package.

従来、高周波デバイス装置には、誘電体基板の底面部に、接地パターンと信号パターンとを形成して、誘電体基板の底面部上に外部コプレーナ線路を構成し、スルーホールにより信号パターンを高周波用パッケージ内部の信号パターンと電気的に接続し、接地用スルーホールにより外部コプレーナ線路の接地パターンを高周波用パッケージ内部の接地パターンと電気的に接続して内部コプレーナ線路を構成した高周波用パッケージに高周波デバイスを搭載したものがあった（例えば、特許文献１参照）。また、各接地パターン間の経路が長いためにインダクタンス成分の増大による不整合や、外部コプレーナ線路の信号パターンと内部コプレーナ線路の接地導体パターンとの間、及び外部コプレーナ線路の信号パターンと高周波用パッケージ内部の高周波デバイスが装着された誘電体層の下面の導体層との間に存在する浮遊キャパシタンス成分による不整合を減じるために、各接地パターン間の経路の短経路化や導体の非形成部の設置などにより、不整合を抑制したものがあった（例えば、特許文献２参照）。   Conventionally, in a high-frequency device device, a ground pattern and a signal pattern are formed on the bottom surface of a dielectric substrate, and an external coplanar line is formed on the bottom surface of the dielectric substrate. A high frequency device connected to the signal pattern inside the package, and the ground pattern of the external coplanar line is electrically connected to the ground pattern inside the high frequency package through a grounding through hole to constitute the internal coplanar line. (For example, refer to Patent Document 1). In addition, due to the long path between each ground pattern, mismatch due to an increase in inductance component, between the signal pattern of the external coplanar line and the ground conductor pattern of the internal coplanar line, and between the signal pattern of the external coplanar line and the high frequency package In order to reduce mismatch due to stray capacitance components existing between the conductor layer on the lower surface of the dielectric layer where the internal high-frequency device is mounted, it is possible to shorten the path between the ground patterns and There was what suppressed mismatching by installation etc. (for example, refer to patent documents 2).

特許第２６０５５０２号公報（第１図）Japanese Patent No. 2605502 (FIG. 1)

特開２００４−２１４５８４号公報（第１図）Japanese Patent Laying-Open No. 2004-214584 (FIG. 1)

しかし、内部及び外部コプレーナ線路の接地パターンや信号パターンが近接しているために、各接地パターン間の経路の短経路化や導体の非形成部の設置などによる不整合の抑制には、限界があるという課題があった。また、コプレーナ線路のような同一面に信号パターンと接地パターンが存在する共平面型線路は、マイクロストリップ線路やトリプレート線路などの高周波線路よりも波長短縮効果が少なく、回路全体の小形化に限界があるという課題もあった。   However, because the ground patterns and signal patterns of the internal and external coplanar lines are close to each other, there is a limit to the suppression of mismatch due to the shortening of the path between the ground patterns and the installation of a non-formed portion of the conductor. There was a problem that there was. In addition, coplanar lines such as coplanar lines that have a signal pattern and a ground pattern on the same surface have less wavelength shortening effect than high-frequency lines such as microstrip lines and triplate lines, and are limited in miniaturization of the entire circuit. There was also a problem that there was.

この発明は、上記のような課題を解消するためになされたもので、信号パターンと接地パターンとの間などに生じる浮遊キャパシタンス成分が引き起こす不整合による高周波入力信号の損失が少なく、装置全体が従来よりも小型である高周波デバイス装置を提供することを目的とする。   The present invention has been made to solve the above-described problems, and the loss of the high-frequency input signal due to mismatch caused by the stray capacitance component generated between the signal pattern and the ground pattern is small. An object of the present invention is to provide a high-frequency device apparatus that is smaller than the above.

請求項１の発明に係る高周波デバイス装置は、誘電体基板と、この誘電体基板の中央表面部及び裏面部に設けられた第１接地パターンと、前記誘電体基板の一端部に設けられた第１入力信号パターンと、前記誘電体基板の他端部に設けられた第１出力信号パターンと、前記誘電体基板の中央表面部に設けられた前記第１接地パターン上に形成され、前記誘電体基板と反対側に凹部を有する第１誘電体層と、前記凹部に装着された高周波デバイスと、前記第１誘電体層上の第１入力信号パターン側に設けられ、前記高周波デバイスと電気的に接続された第２入力信号パターンと、前記第１誘電体層上の第１出力信号パターン側に設けられ、前記高周波デバイスと電気的に接続された第２出力信号パターンと、前記高周波デバイスの両側における前記第１誘電体層にそれぞれスルーホールを形成し、これらのスルーホールを介して、前記第１及び第２入力信号パターン同士及び前記第１及び第２出力信号パターン同士をそれぞれ電気的に接続する接続手段と、前記第２入力信号パターン及び前記第２出力信号パターン並びに前記第１誘電体層上に設けられ、前記高周波デバイスの表面部を開口する第２誘電体層と、この第２誘電体層上に設けられ、前記第１及び第２入力信号パターン上、並びに前記第１及び第２出力信号パターン上に配置した第２接地パターンとを備えたことを特徴とするものである。 A high-frequency device device according to a first aspect of the present invention includes a dielectric substrate, a first ground pattern provided on a central surface portion and a back surface portion of the dielectric substrate, and a first ground pattern provided on one end portion of the dielectric substrate . A first input signal pattern ; a first output signal pattern provided on the other end of the dielectric substrate; and a first ground pattern provided on a central surface portion of the dielectric substrate; A first dielectric layer having a recess on the opposite side of the substrate ; a high-frequency device mounted in the recess; and a first input signal pattern on the first dielectric layer, electrically connected to the high-frequency device A connected second input signal pattern , a second output signal pattern provided on the first output signal pattern side on the first dielectric layer and electrically connected to the high frequency device, and both sides of the high frequency device In Through holes are respectively formed in the first dielectric layer, and the first and second input signal patterns and the first and second output signal patterns are electrically connected to each other through these through holes. Connection means, a second dielectric layer provided on the second input signal pattern, the second output signal pattern, and the first dielectric layer and opening a surface portion of the high-frequency device, and the second dielectric And a second ground pattern disposed on the first and second input signal patterns and on the first and second output signal patterns.

請求項２の発明に係る高周波デバイス装置は、前記第１誘電体層は２層から構成され、少なくとも前記スルーホールの周辺部を除き、その間に第３接地パターンを設けた請求項１に記載のものである。 High-frequency device apparatus according to the invention of claim 2, wherein the first dielectric layer is composed of two layers, except at least the periphery of the through hole, according to claim 1 having a third ground pattern therebetween Is.

請求項３の発明に係る高周波デバイス装置は、前記誘電体基板の裏面部に設けられた前記第１接地パターンと前記第３接地パターンとを、前記誘電体基板及び前記第１誘電体層に形成したスルーホールを介して電気的に接続した請求項２に記載のものである。 According to a third aspect of the present invention, in the high frequency device device, the first ground pattern and the third ground pattern provided on the back surface of the dielectric substrate are formed on the dielectric substrate and the first dielectric layer. It is a thing of Claim 2 electrically connected through the made through hole .

請求項４の発明に係る高周波デバイス装置は、前記誘電体基板の中央表面部に設けられた前記第１接地パターンと前記第２接地パターンとを、前記第２入出力信号パターンの両側であって、前記第１及び第２誘電体層に形成したスルーホールを介して電気的に接続した請求項１〜３のいずれかに記載のものである。 According to a fourth aspect of the present invention, in the high frequency device device, the first ground pattern and the second ground pattern provided on the center surface portion of the dielectric substrate are arranged on both sides of the second input / output signal pattern. 4. The method according to claim 1, wherein the first and second dielectric layers are electrically connected through through holes .

以上のように、この発明によれば、第１入力信号パターン，第２入力信号パターン，第１出力信号パターン，第２出力信号パターンの線路幅・線路長や誘電体基板，第１誘電体層，第２誘電体層の比誘電率を変更することにより整合を容易に取ることができ、装着する高周波デバイスとの整合も容易な高周波デバイス装置を得ることができる。また、第１入力信号パターン，第２入力信号パターン，第１出力信号パターン，第２出力信号パターン及び第１接地パターン，第２接地パターンからトリプレート線路が構成されるので、波長短縮効果によりコプレーナ線路に比べて線路幅・線路長が短くなり小型化した高周波デバイス装置を得ることができる。
As described above, according to the present invention, the first input signal pattern, the second input signal pattern, the first output signal pattern, the line width / line length of the second output signal pattern , the dielectric substrate, and the first dielectric layer , By changing the relative dielectric constant of the second dielectric layer , matching can be easily achieved, and a high-frequency device device that can be easily matched with the high-frequency device to be mounted can be obtained . Also, since the triplate line is composed of the first input signal pattern, the second input signal pattern, the first output signal pattern, the second output signal pattern, the first ground pattern, and the second ground pattern, the coplanar is achieved by the wavelength shortening effect. Compared to the line, the line width and line length are shortened, and a miniaturized high-frequency device device can be obtained.

実施の形態１．
以下、この発明の実施の形態１について図１〜７を用いて説明する。図１は、高周波デバイス装置の回路構成図（斜視図），図２は、高周波デバイス装置の回路構成図（横方向の断面図）であり、図１及び２において、１は高周波半導体素子や高周波回路等の高周デバイス、２は高周波デバイスを装着する孔部が形成された第１誘電体層、３は第１誘電体層２の下部に設けられた誘電体基板、４は誘電体基板３の表面部に設けられた第１信号パターン、５は誘電体基板３の裏面に設けられた第１接地パターン（裏面部）、６は第１誘電体層２に設けられ、第１信号パターン４と電気的に接続されたスルーホール（信号用）、７は第１誘電体層２の表面部に設けられ、スルーホール（信号用）６と電気的に接続された第２信号パターン、８は第２信号パターン７と高周波デバイス１とを電気的に接続するワイヤボンディング等の導電性接続手段、９は第１誘電体層２上及び前記第２信号パターン７上に設けられ、高周波デバイス１の表面部を開口する第２誘電体層、１０は第２誘電体層９上に設けられ、第１信号パターン４と第２信号パターン７上に配置した第２接地パターン、１１は第１誘電体層２及び第２誘電体層９に設けられ、第１接地パターン５と第２接地パターン１０とを電気的に接続するスルーホール（接地用）、１２は高周波回路１に制御信号を送る制御信号線路、１３は高周波デバイス装置の蓋部である。図中、同一符号は、同一又は相当部分を示しそれらについての詳細な説明は省略する。 Embodiment 1 FIG.
Embodiment 1 of the present invention will be described below with reference to FIGS. FIG. 1 is a circuit configuration diagram (perspective view) of a high-frequency device device, and FIG. 2 is a circuit configuration diagram (cross-sectional view in the lateral direction) of the high-frequency device device. In FIGS. A high-frequency device such as a circuit, 2 is a first dielectric layer in which a hole for mounting a high-frequency device is formed, 3 is a dielectric substrate provided below the first dielectric layer 2, and 4 is a dielectric substrate 3. The first signal pattern 5 is provided on the front surface portion of the first dielectric layer 3, the first ground pattern (back surface portion) is provided on the rear surface of the dielectric substrate 3, and the first signal pattern 4 is provided on the first dielectric layer 2. A through hole (for signal) 7 electrically connected to the second dielectric layer 2 is provided on the surface of the first dielectric layer 2 and a second signal pattern 8 electrically connected to the through hole (for signal) 6. A wirebob for electrically connecting the second signal pattern 7 and the high-frequency device 1 Conductive connection means such as ringing, 9 is provided on the first dielectric layer 2 and the second signal pattern 7, and the second dielectric layer that opens the surface of the high-frequency device 1, 10 is the second dielectric The second ground pattern 11 provided on the layer 9 and disposed on the first signal pattern 4 and the second signal pattern 7 is provided on the first dielectric layer 2 and the second dielectric layer 9. 5 is a through hole (for grounding) that electrically connects the second ground pattern 10, 12 is a control signal line for sending a control signal to the high-frequency circuit 1, and 13 is a lid of the high-frequency device device. In the drawings, the same reference numerals denote the same or corresponding parts, and detailed descriptions thereof are omitted.

図３は、高周波デバイス装置の回路構成図であり、図３において、図３（ａ）は図２と同一であり、図３（ｂ），（ｃ），（ｄ），（ｅ），（ｆ）は、それぞれ図３（ａ）におけるＢ…Ｂ’，Ｃ…Ｃ’，Ｄ…Ｄ’，Ｅ…Ｅ’，Ｆ…Ｆ’の点線部分の断面を上方からみた高周波デバイス装置の回路構成図である。また、図４は高周波デバイス装置のトリプレート回路構成図（第１信号パターン及び第２信号パターン付近断面図）である。図４（ａ）は、高周波デバイス装置の回路構成図（縦方向の断面図）の一部で、図４（ｂ）,図４（ｃ）は、それぞれ図４（ａ）におけるＢ…Ｂ’，Ｃ…Ｃ’の点線から図４（ａ）の断面と直角方向の断面から見た高周波デバイス装置の回路構成図であり、図４において、４（ａ）は誘電体基板３の表面部に設けられた第１信号パターン、４（ｂ）は第１誘電体層２の裏面部に設けられた第１信号パターン、７（ａ）は第１誘電体層２の表面部に設けられた第２信号パターン、７（ｂ）は第２誘電体層９の裏面部に設けられた第２信号パターンはである。図中、同一符号は、同一又は相当部分を示しそれらについての詳細な説明は省略する。   3 is a circuit configuration diagram of the high-frequency device device. In FIG. 3, FIG. 3 (a) is the same as FIG. 2, and FIGS. 3 (b), (c), (d), (e), ( f) is a circuit configuration of the high-frequency device device as viewed from above the cross-sections of dotted lines B ... B ', C ... C', D ... D ', E ... E', F ... F 'in FIG. FIG. FIG. 4 is a triplate circuit configuration diagram of the high-frequency device device (a cross-sectional view in the vicinity of the first signal pattern and the second signal pattern). 4A is a part of a circuit configuration diagram (longitudinal sectional view) of the high-frequency device device, and FIGS. 4B and 4C are respectively B... B ′ in FIG. , C... C ′ is a circuit configuration diagram of the high-frequency device device viewed from a cross section perpendicular to the cross section of FIG. 4A. The first signal pattern provided, 4 (b) is the first signal pattern provided on the back surface portion of the first dielectric layer 2, and 7 (a) is the first signal pattern provided on the surface portion of the first dielectric layer 2. A two-signal pattern 7 (b) is a second signal pattern provided on the back surface of the second dielectric layer 9. In the drawings, the same reference numerals denote the same or corresponding parts, and detailed descriptions thereof are omitted.

図５は、高周波デバイス装置の反射特性図，図６は、高周波デバイス装置の誘電体基板の中央表面部に接地導体が設けられた回路構成図（信号用のスルーホールの断面図），図７は、高周波デバイス装置の誘電体基板の中央表面部に接地導体が設けられた回路構成図（接地用のスルーホールの断面図）であり、図５において、横軸は周波数、縦軸は反射係数のデシベル表示である。図６及び７において、１４は誘電体基板３の表面部に設けられた第１入出力信号パターン、１５は第１誘電体層２の表面部に設けられ、スルーホール（信号用）６と電気的に接続された第２入出力信号パターン、１６は誘電体基板の中央表面部に設けられた第１接地パターン（中央表面部）である。図中、同一符号は、同一又は相当部分を示しそれらについての詳細な説明は省略する。   FIG. 5 is a reflection characteristic diagram of the high-frequency device device, FIG. 6 is a circuit configuration diagram (cross-sectional view of a signal through hole) in which a ground conductor is provided on the central surface portion of the dielectric substrate of the high-frequency device device, and FIG. FIG. 5 is a circuit configuration diagram (a cross-sectional view of a grounding through hole) in which a ground conductor is provided on the center surface portion of a dielectric substrate of a high-frequency device device. In FIG. 5, the horizontal axis represents frequency and the vertical axis represents reflection coefficient. Is the decibel display. 6 and 7, reference numeral 14 denotes a first input / output signal pattern provided on the surface portion of the dielectric substrate 3, and reference numeral 15 denotes a first input / output signal pattern provided on the surface portion of the first dielectric layer 2. The second input / output signal pattern 16 connected in a connected manner is a first ground pattern (center surface portion) provided on the center surface portion of the dielectric substrate. In the drawings, the same reference numerals denote the same or corresponding parts, and detailed descriptions thereof are omitted.

次に動作について説明する。入力信号は、第１信号パターン４（ａ）と第１接地パターン５からなるマイクロストリップ線路から給電され、このマイクロストリップ線路は、第１信号パターン４、第１接地パターン５及び第２接地パターン１０とで構成されるトリプレート線路に接続される。マイクロストリップ線路−トリプレート線路間のインピーダンス整合の方法は、誘電体基板３の比誘電率と第１誘電体層２の比誘電率とが決定している場合、第１信号パターン４（ａ）と第１信号パターン４（ｂ）との線路（導体）幅を調整し、第１信号パターン４（ａ）と第１信号パターン４（ｂ）との線路（導体）幅が決定している場合、誘電体基板３の比誘電率と第１誘電体層２の比誘電率とを調整して行う。なお、導体の幅と誘電率との両方を調整してもよい。   Next, the operation will be described. The input signal is fed from a microstrip line composed of a first signal pattern 4 (a) and a first ground pattern 5, and the microstrip line is connected to the first signal pattern 4, the first ground pattern 5, and the second ground pattern 10. Are connected to a triplate line. In the impedance matching method between the microstrip line and the triplate line, when the relative permittivity of the dielectric substrate 3 and the relative permittivity of the first dielectric layer 2 are determined, the first signal pattern 4 (a). And the line (conductor) width between the first signal pattern 4 (b) and the line (conductor) width between the first signal pattern 4 (a) and the first signal pattern 4 (b) are determined. The dielectric constant of the dielectric substrate 3 and the relative dielectric constant of the first dielectric layer 2 are adjusted. Both the width of the conductor and the dielectric constant may be adjusted.

そして、トリプレート線路は、第１誘電体層２に設けられたスルーホール（信号用）６に電気的に接続され、そのスルーホール（信号用）６は、第２信号パターン７に電気的に接続される。第２信号パターン７は、第１接地パターン５と第２接地パターン１０とからトリプレート線路を構成し、第２信号パターン７（ａ）と第１接地パターン５からなるマイクロストリップ線路に変換され、ワイヤボンディング等の導電性接続手段８により高周波デバイス１に電気的に接続される。ここで、トリプレート線路−マイクロストリップ線路間のインピーダンス整合の方法は、上記のマイクロストリップ線路−トリプレート線路間のインピーダンス整合の方法と同様である。高周波デバイス１は、入力信号と制御信号線路１２からの制御信号により、所定の出力信号を出力する。この出力信号は、入力信号の経路と反対側の信号パターンを経由して高周波デバイス装置から出力される。また、出力信号側のインピーダンス整合も入力信号側と同様に行われている。このような構造をとることにより、図５に示すように、広帯域に渡って−２５ｄＢ以下の反射特性が得られる。   The triplate line is electrically connected to a through hole (for signal) 6 provided in the first dielectric layer 2, and the through hole (for signal) 6 is electrically connected to the second signal pattern 7. Connected. The second signal pattern 7 constitutes a triplate line from the first ground pattern 5 and the second ground pattern 10, and is converted into a microstrip line composed of the second signal pattern 7 (a) and the first ground pattern 5. It is electrically connected to the high-frequency device 1 by conductive connection means 8 such as wire bonding. Here, the impedance matching method between the triplate line and the microstrip line is the same as the above impedance matching method between the microstrip line and the triplate line. The high frequency device 1 outputs a predetermined output signal based on the input signal and the control signal from the control signal line 12. This output signal is output from the high-frequency device device via a signal pattern opposite to the path of the input signal. Also, impedance matching on the output signal side is performed in the same manner as on the input signal side. By adopting such a structure, as shown in FIG. 5, a reflection characteristic of −25 dB or less can be obtained over a wide band.

図４（ｂ）に示すトリプレート線路は、第１誘電体層２と第２誘電体層９の間に設けられ、第２信号パターン７と絶縁された接地パターン（図示せず）と第１接地パターン（裏面部）とにより構成しても良い。同じく、図４（ｃ）に示すトリプレート線路でも、図６又は７に示す誘電体基板３と第１誘電体層２との間に設けられた第１接地パターン（中央表面部）１６と第２接地パターン１０とにより構成しても良い。また、上記のトリプレート線路にインダクタやキャパシタ等の受動素子（図示せず）を装荷することにより、フィルタ等の回路をトリプレート線路内に形成して、多機能化を図ってもよい。   The triplate line shown in FIG. 4B is provided between the first dielectric layer 2 and the second dielectric layer 9 and is insulated from the second signal pattern 7 by a ground pattern (not shown) and the first dielectric layer. You may comprise by a grounding pattern (back surface part). Similarly, in the triplate line shown in FIG. 4C, the first ground pattern (center surface portion) 16 provided between the dielectric substrate 3 and the first dielectric layer 2 shown in FIG. A two-ground pattern 10 may be used. In addition, by loading a passive element (not shown) such as an inductor or a capacitor on the above-described triplate line, a circuit such as a filter may be formed in the triplate line to achieve multiple functions.

実施の形態２．
この発明の実施の形態２について図８〜１１を用いて説明する。図８は、高周波デバイス装置の誘電体基板の回路構成図（信号用のスルーホールの断面図），図９は、高周波デバイス装置の誘電体基板の回路構成図（接地用のスルーホールの断面図），図１０は、高周波デバイス装置の誘電体基板の中央表面部に接地導体が設けられた回路構成図（信号用のスルーホールの断面図），図１１は、高周波デバイス装置の誘電体基板の中央表面部に接地導体が設けられた回路構成図（接地用のスルーホールの断面図）であり、図８〜１１において、１７は２層から構成された第１誘電体層２の間に設けられ、少なくともスルーホール（信号用）６の周辺部を除いたパターンの第３接地パターンである。図中、同一符号は、同一又は相当部分を示しそれらについての詳細な説明は省略する。図８〜１１に示すように実施の形態１の高周波デバイス装置（図１〜７）における第１誘電体層を２層で形成し、その２層の間にスルーホール（信号用）６と絶縁された第３接地パターンを設けた構造でも、実施の形態１と同等の効果を示す。 Embodiment 2. FIG.
A second embodiment of the present invention will be described with reference to FIGS. 8 is a circuit configuration diagram of the dielectric substrate of the high-frequency device device (cross-sectional view of the signal through hole), and FIG. 9 is a circuit configuration diagram of the dielectric substrate of the high-frequency device device (cross-sectional view of the grounding through hole). 10 is a circuit configuration diagram (cross-sectional view of a signal through hole) provided with a ground conductor on the center surface portion of the dielectric substrate of the high-frequency device device, and FIG. 11 is a diagram of the dielectric substrate of the high-frequency device device. FIG. 11 is a circuit configuration diagram (a cross-sectional view of a grounding through hole) in which a ground conductor is provided on the central surface portion, and in FIGS. 8 to 11, 17 is provided between two first dielectric layers 2. The third ground pattern is a pattern excluding at least the periphery of the through hole (for signal) 6. In the drawings, the same reference numerals denote the same or corresponding parts, and detailed descriptions thereof are omitted. As shown in FIGS. 8 to 11, the first dielectric layer in the high-frequency device device (FIGS. 1 to 7) of the first embodiment is formed of two layers, and the through hole (for signal) 6 is insulated between the two layers. Even in the structure provided with the third ground pattern, the same effect as in the first embodiment is exhibited.

実施の形態３．
この発明の実施の形態３について図１２を用いて説明する。図１２は、高周波デバイス装置の誘電体基板の回路構成図（スルーホールの周辺図）である。図中、同一符号は、同一又は相当部分を示しそれらについての詳細な説明は省略する。実施の形態１及び２における高周波デバイス装置のスルーホール（接地用）１１を第１信号パターン４，第２信号パターン７又は第１入出力信号パターン１４，第２入出力信号パターンなどの信号パターンに沿って複数設けることにより、シールド構造が形成されて信号パターンからの不要な放射を抑えることができ、損失を小さくすることが可能である。また、他の線路との結合も抑えることができる。さらに、スルーホール（信号用）６の周辺にスルーホール（接地用）１１を集中的に設けることにより、擬似的な同軸構造（図示せず）とすることで、スルーホール（信号用）６からの不要な放射を抑えることができ、損失を小さくすることも可能である。 Embodiment 3 FIG.
A third embodiment of the present invention will be described with reference to FIG. FIG. 12 is a circuit configuration diagram of the dielectric substrate of the high-frequency device device (a peripheral view of the through hole). In the drawings, the same reference numerals denote the same or corresponding parts, and detailed descriptions thereof are omitted. The through-hole (for grounding) 11 of the high-frequency device device according to the first and second embodiments is used as a signal pattern such as a first signal pattern 4, a second signal pattern 7, or a first input / output signal pattern 14, a second input / output signal pattern. By providing a plurality along the shield, a shield structure is formed, unnecessary radiation from the signal pattern can be suppressed, and loss can be reduced. Also, coupling with other lines can be suppressed. Furthermore, by providing through holes (for grounding) 11 around the through holes (for signals) 6 in a concentrated manner, a pseudo coaxial structure (not shown) is provided, so that the through holes (for signals) 6 The unnecessary radiation can be suppressed and the loss can be reduced.

この発明の実施の形態１による高周波デバイス装置の回路構成図（斜視図）である。BRIEF DESCRIPTION OF THE DRAWINGS It is a circuit block diagram (perspective view) of the high frequency device apparatus by Embodiment 1 of this invention. この発明の実施の形態１による高周波デバイス装置の回路構成図（横方向の断面図）である。It is a circuit block diagram (cross-sectional view of a horizontal direction) of the high frequency device apparatus by Embodiment 1 of this invention. この発明の実施の形態１による断面を上方からみた高周波デバイス装置の回路構成図である。It is a circuit block diagram of the high frequency device apparatus which looked at the cross section by Embodiment 1 of this invention from upper direction. この発明の実施の形態１による高周波デバイス装置のトリプレート回路構成図（第１信号パターン及び第２信号パターン付近断面図）である。It is a triplate circuit block diagram (1st signal pattern and 2nd signal pattern vicinity sectional drawing) of the high frequency device apparatus by Embodiment 1 of this invention. この発明の実施の形態１による高周波デバイス装置の反射特性図である。It is a reflection characteristic figure of the high frequency device apparatus by Embodiment 1 of this invention. この発明の実施の形態１による高周波デバイス装置の誘電体基板の中央表面部に接地導体が設けられた回路構成図（信号用のスルーホールの断面図）である。1 is a circuit configuration diagram (a cross-sectional view of a signal through hole) in which a ground conductor is provided on a central surface portion of a dielectric substrate of a high-frequency device device according to Embodiment 1 of the present invention; この発明の実施の形態１による高周波デバイス装置の誘電体基板の中央表面部に接地導体が設けられた回路構成図（接地用のスルーホールの断面図）である。1 is a circuit configuration diagram (a cross-sectional view of a grounding through hole) in which a ground conductor is provided on a central surface portion of a dielectric substrate of a high-frequency device device according to Embodiment 1 of the present invention; この発明の実施の形態２による高周波デバイス装置の誘電体基板の回路構成図（信号用のスルーホールの断面図）である。It is a circuit block diagram (sectional drawing of the through-hole for signals) of the dielectric substrate of the high frequency device apparatus by Embodiment 2 of this invention. この発明の実施の形態２による高周波デバイス装置の誘電体基板の回路構成図（接地用のスルーホールの断面図）である。It is a circuit block diagram (sectional drawing of the through-hole for earthing | grounding) of the dielectric substrate of the high frequency device apparatus by Embodiment 2 of this invention. この発明の実施の形態２による高周波デバイス装置の誘電体基板の中央表面部に接地導体が設けられた回路構成図（信号用のスルーホールの断面図）である。FIG. 6 is a circuit configuration diagram (cross-sectional view of a signal through hole) in which a ground conductor is provided on a central surface portion of a dielectric substrate of a high-frequency device device according to Embodiment 2 of the present invention; この発明の実施の形態２による高周波デバイス装置の誘電体基板の中央表面部に接地導体が設けられた回路構成図（接地用のスルーホールの断面図）である。FIG. 6 is a circuit configuration diagram (a cross-sectional view of a grounding through hole) in which a ground conductor is provided on a central surface portion of a dielectric substrate of a high-frequency device device according to Embodiment 2 of the present invention; この発明の実施の形態３による高周波デバイス装置の誘電体基板の回路構成図（スルーホールの周辺図）である。It is a circuit block diagram (periphery figure of a through hole) of the dielectric substrate of the high frequency device apparatus by Embodiment 3 of this invention.

符号の説明Explanation of symbols

１…高周デバイス、２…第１誘電体層、３…誘電体基板、４…第１信号パターン
５…第１接地パターン（裏面部）、６…スルーホール（信号用）、７…第２信号パターン
８…導電性接続手段、９…第２誘電体層、１０…第２接地パターン
１１…スルーホール（接地用）、１２…制御信号線路、１３…蓋部
１４…第１入出力信号パターン、１５…第２入出力信号パターン
１６…第１接地パターン（中央表面部）、１７…第３接地パターン



DESCRIPTION OF SYMBOLS 1 ... High frequency device, 2 ... 1st dielectric layer, 3 ... Dielectric substrate, 4 ... 1st signal pattern 5 ... 1st grounding pattern (back surface part), 6 ... Through hole (for signals), 7 ... 2nd Signal pattern 8 ... conductive connection means, 9 ... second dielectric layer, 10 ... second ground pattern 11 ... through hole (for ground), 12 ... control signal line, 13 ... lid portion 14 ... first input / output signal pattern , 15 ... second input / output signal pattern 16 ... first ground pattern (center surface portion), 17 ... third ground pattern



Claims (4)

誘電体基板と、この誘電体基板の中央表面部及び裏面部に設けられた第１接地パターンと、前記誘電体基板の一端部に設けられた第１入力信号パターンと、前記誘電体基板の他端部に設けられた第１出力信号パターンと、前記誘電体基板の中央表面部に設けられた前記第１接地パターン上に形成され、前記誘電体基板と反対側に凹部を有する第１誘電体層と、前記凹部に装着された高周波デバイスと、前記第１誘電体層上の第１入力信号パターン側に設けられ、前記高周波デバイスと電気的に接続された第２入力信号パターンと、前記第１誘電体層上の第１出力信号パターン側に設けられ、前記高周波デバイスと電気的に接続された第２出力信号パターンと、前記高周波デバイスの両側における前記第１誘電体層にそれぞれスルーホールを形成し、これらのスルーホールを介して、前記第１及び第２入力信号パターン同士及び前記第１及び第２出力信号パターン同士をそれぞれ電気的に接続する接続手段と、前記第２入力信号パターン及び前記第２出力信号パターン並びに前記第１誘電体層上に設けられ、前記高周波デバイスの表面部を開口する第２誘電体層と、この第２誘電体層上に設けられ、前記第１及び第２入力信号パターン上、並びに前記第１及び第２出力信号パターン上に配置した第２接地パターンとを備えた高周波デバイス装置。 A dielectric substrate, a first ground pattern provided on a central surface portion and a back surface portion of the dielectric substrate, a first input signal pattern provided on one end portion of the dielectric substrate, and other dielectric substrates. A first output signal pattern provided at an end portion and a first dielectric formed on the first ground pattern provided on a central surface portion of the dielectric substrate and having a recess on the opposite side of the dielectric substrate ; A layer, a high-frequency device mounted in the recess, a second input signal pattern provided on the first input signal pattern side on the first dielectric layer and electrically connected to the high-frequency device, and the first A second output signal pattern provided on the first output signal pattern side on the first dielectric layer and electrically connected to the high frequency device, and a through hole in the first dielectric layer on both sides of the high frequency device, respectively. form And, through these through-holes, said first and second input signal patterns and between the first and the second output signal pattern with each other and connecting means for electrically connecting each of the second input signal pattern and the A second output signal pattern and a second dielectric layer provided on the first dielectric layer and opening a surface portion of the high-frequency device; and provided on the second dielectric layer, the first and second dielectric layers. A high frequency device apparatus comprising: an input signal pattern; and a second ground pattern disposed on the first and second output signal patterns. 前記第１誘電体層は２層から構成され、少なくとも前記スルーホールの周辺部を除き、その間に第３接地パターンを設けた請求項１に記載の高周波デバイス装置。 2. The high-frequency device device according to claim 1 , wherein the first dielectric layer is composed of two layers, and at least a peripheral portion of the through hole is provided, and a third ground pattern is provided therebetween. 前記誘電体基板の裏面部に設けられた前記第１接地パターンと前記第３接地パターンとを、前記誘電体基板及び前記第１誘電体層に形成したスルーホールを介して電気的に接続した請求項２に記載の高周波デバイス装置。The first ground pattern and the third ground pattern provided on the back surface of the dielectric substrate are electrically connected through a through hole formed in the dielectric substrate and the first dielectric layer. Item 5. The high-frequency device device according to Item 2. 前記誘電体基板の中央表面部に設けられた前記第１接地パターンと前記第２接地パターンとを、前記第２入出力信号パターンの両側であって、前記第１及び第２誘電体層に形成したスルーホールを介して電気的に接続した請求項１〜３のいずれかに記載の高周波デバイス装置。The first ground pattern and the second ground pattern provided on a central surface portion of the dielectric substrate are formed on both sides of the second input / output signal pattern on the first and second dielectric layers. The high-frequency device device according to claim 1, wherein the high-frequency device device is electrically connected through the through-hole.
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