JPH0491471A - Nonvolatile semiconductor storage device - Google Patents

Abstract

PURPOSE:To simplify a manufacturing method and also realize large capacity and high operation rate by providing a source through an offset region from a first gate electrode and arranging a second gate electrode in such a manner as wrapping the first gate electrode at the upper part of the first gate electrode including a side wall part. CONSTITUTION:A floating gate (a first gate electrode) 3 is formed on a Si substrate through a gate insulating film 2, moreover a photoresist layer 4 is formed covering a part of the floating gate 3 and As ion 10 is implanted on the Si substrate using the resist layer 4 and gate 3 as the mask to form impurity regions F, G. In this timing, an offset region la is formed. After removing the resist layer 4, an insulating layer 11 is formed to the entire surface of Si substrate, a side wall 5 is formed by removing the insulating film 11 with the anisotropic etching, a layer insulating film 12 and a polysilicon layer 7 are sequentially laminated to the entire surface of the Si substrate including the floating gate 3, and a polysilicon layer 7 is patterned to form a second gate electrode 7.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application This invention relates to a nonvolatile semiconductor memory device suitable for high integration.

(B) Prior art A conventional non-volatile semiconductor memory device has an N-type drain region and a source region on the surface of a P-type semiconductor substrate, and has an N-type drain region and a source region at a position offset from the source region.
A structure has been proposed in which a three-layer film structure consisting of a floating gate/an interlayer insulating film/a control gate is arranged, and a sidewall electrode formed on the three-layer structure is arranged on the offset side. With this structure, injection of electrons from the source side is achieved by applying optimal potentials to the sidewall electrode and control gate separately.

(c) Problems to be Solved by the Invention However, the above-mentioned conventional nonvolatile semiconductor memory device
Although it has the advantage that sidewalls formed in a self-controlled manner can be used for the three-layer film including the floating gate, the overall manufacturing process is extremely complicated because the sidewalls are used as electrodes. ing. In addition, since this sidewall section is also used as wiring, wiring resistance increases and signal delays occur, so it can only be used for applications where there is no problem even if it is slow.

Therefore, an object of the present invention is to provide an electrically writable and erasable nonvolatile memory characterized by injection of electrons from the source side, which is easier to manufacture than conventional techniques, and is suitable for increasing capacity and speed. It is about providing.

(d) Means and operation for solving the problems The present invention includes a semiconductor substrate, a first gate electrode disposed on the substrate, and a sidewall section disposed on the first gate electrode. , a drain formed on the semiconductor substrate and disposed in contact with the first gate electrode in a self-aligned manner; and a drain formed on the semiconductor substrate and disposed through an offset region from the first gate electrode. above the source and the first gate electrode including the sidewall portion, so as to cover the entire channel region formed between the source/drain region.
and a second gate electrode disposed so as to surround the first gate electrode.
This is a nonvolatile semiconductor memory device having a gate electrode.

That is, in this invention, in order to increase the threshold voltage of the offset part, a sidewall part formed in a self-aligned manner with respect to the first gate electrode (floating gate) is used as a thick gate oxide film for this part, When a high voltage is applied to the second gate electrode, this offset portion is made to be weakly inverted.

In addition, as the material for the first and second gate electrodes, for example,
Polysilicon and/or tungsten silicide (
WSiz), etc., it is possible to provide a nonvolatile semiconductor memory device that can realize writing from the source.

(E) Embodiment In FIG. 1(d), the nonvolatile semiconductor memory device is S
i-substrate and a floating gate (first
gate electrode) 3 and the sidewall 5 of the gate 3
and a drain 22 formed on a Si substrate and arranged so as to be in contact with the first gate electrode 3 in a self-aligned manner;
A source 21 disposed via an offset region 1a from a first gate electrode 3 formed on a semiconductor substrate;
A second gate electrode (polysilicon layer) 7 is disposed above the gate electrode 3 to cover the entire channel region 1a, lb between the source/drain regions and to wrap around the first gate electrode 3. and becomes the lord.

A method for manufacturing a nonvolatile semiconductor memory device will be described below with reference to FIG.

First, as shown in FIG. 1(a), a polysilicon layer is laminated on the entire surface of the Si substrate 1 with a gate insulating film 2 interposed therebetween.
A floating gate (first gate electrode) 3 is formed by photolithography and etching, and further, on the Si substrate,
A photoresist layer 4 is formed covering a part of the floating gate 3, and using the resist layer and the gate 3 as a mask, Si is deposited.
As ions IO are implanted onto the substrate to form impurity regions F and G.

At this time, an offset region 1a is formed.

After removing the resist layer 4, an insulating film 11 of 5 iOz is formed on the entire surface of the Si substrate 1 using the CVD method [see FIG.
b) Reference.

Subsequently, the insulating film 11 is removed by anisotropic etching, leaving only the sidewalls of the floating gate 3 to form the sidewalls 5 [see FIG. 1(c)].

Next, as shown in FIG. 1(d), an interlayer insulating film 12 of, for example, SiO* and a polysilicon layer 7 are sequentially laminated over the entire surface of the Si substrate including the floating gate 3. In addition,
21 and 22 are the source and drain, respectively.

Furthermore, an ONO film or other well-known insulating film may be used as the interlayer insulating film.

Thereafter, the polysilicon layer 7 is patterned to form the second gate electrode 7.

(i) Readout of the device created in this way, (i
The operations of i) writing and (iii) erasing will be explained.

(i) When reading, source 21 is 5 volts, drain 2
2 is set to 0 volts, and 18 volts is applied to the second gate electrode 7.

(ii) When writing, swap the source/drain,
The source 21 is set to 0 volts, the drain 22 is set to 5 volts, and 18 volts is applied to the second gate electrode 7. This potential of 18 volts is such that the potential of the floating gate 3 becomes twice Vo due to capacitive coupling.

(iii) When erasing, set the source 2I to open, the drain 22 to about 15 volts, and the second gate electrode 7 to O volts, thereby drawing electrons from the floating gate to the drain by F/N tunneling. done by.

(F) Effects of the Invention As described above, according to the present invention, the floating gate has a sidewall insulating film structure on the sidewall, and the source/drain portions are asymmetrical (the drain is self-aligned with respect to the floating gate). The second gate electrode is a non-volatile electrode that wraps around the floating gate to cover the entire channel region between the source/drain regions. This enables writing to be performed by injecting electrons from the source, which was difficult to manufacture because conventionally the sidewalls were used as electrodes, and because the sidewalls were used as wiring. This eliminates the disadvantage that wiring resistance increases and signal delays occur, so it can only be used for applications where there is no problem even if it is slow.

[Brief explanation of the drawing]

FIG. 1 is a manufacturing process explanatory diagram for explaining one embodiment of the present invention. 1...Si substrate, 1a...offset area, la, lb...channel area, 3...
...First gate electrode, 7...Second gate electrode, 21...Source, 22...Drain.

Claims (1)

[Claims] 1. A semiconductor substrate, a first gate electrode disposed on the substrate, a sidewall section disposed on the first gate electrode, and a sidewall section disposed on the semiconductor substrate and disposed on the first gate electrode. a drain disposed so as to be in contact with the semiconductor substrate in a self-aligned manner; a source formed on the semiconductor substrate and disposed via an offset region from the first gate electrode; and a first gate electrode including a sidewall portion. A nonvolatile semiconductor memory device comprising a second gate electrode disposed above so as to cover the entire channel region formed between the source/drain regions and to wrap around the first gate electrode.