JPH0491444A - Mounting method for semiconductor element - Google Patents
Mounting method for semiconductor elementInfo
- Publication number
- JPH0491444A JPH0491444A JP2203971A JP20397190A JPH0491444A JP H0491444 A JPH0491444 A JP H0491444A JP 2203971 A JP2203971 A JP 2203971A JP 20397190 A JP20397190 A JP 20397190A JP H0491444 A JPH0491444 A JP H0491444A
- Authority
- JP
- Japan
- Prior art keywords
- adhesive
- electrode
- transferring
- conductive filler
- semiconductor element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 36
- 238000000034 method Methods 0.000 title claims abstract description 29
- 239000000853 adhesive Substances 0.000 claims abstract description 58
- 230000001070 adhesive effect Effects 0.000 claims abstract description 58
- 239000011231 conductive filler Substances 0.000 claims abstract description 34
- 239000012790 adhesive layer Substances 0.000 claims abstract description 12
- 239000002245 particle Substances 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims description 22
- 239000010410 layer Substances 0.000 abstract description 7
- 239000000945 filler Substances 0.000 abstract description 4
- 230000000694 effects Effects 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 238000002161 passivation Methods 0.000 description 2
- 239000011295 pitch Substances 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は、回路基板上への半導体素子、つまり、集積回
路（以下、ＩＣという）の実装方法に関するものである
。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method of mounting a semiconductor element, that is, an integrated circuit (hereinafter referred to as IC) on a circuit board.
（従来の技術）
従来、このような分野の技術としては、例えば特開昭６
２１４４１４２号に記載されるようなものがあった。(Prior art) Conventionally, as a technology in this field, for example, Japanese Patent Application Laid-open No. 6
There was one described in No. 2144142.
第４図はかかる従来の半導体素子の実装断面図である。FIG. 4 is a cross-sectional view of such a conventional semiconductor device.
この図に示すように、１はＩＣチップとの電気的接続を
とるためのＩＴＯ電極２が形成されたガラス基板、３は
ＩＣチップとガラス基板１とを固定接着するための接着
剤、４はＩＣチップとＩＴＯ電極２との電気的接続に寄
与し接着剤中に含まれる導電性フィラーであり、ここで
、接着剤３と導電性フィラー４とで、異方性導電接着剤
５を構成している。６はＩＣチップ、７はＩＣチップ６
上に形成されたＡＩ！、電極、８はＡ２電極上に形成さ
れたＡｕバンプ、９はＩＣチップ上の回路配線を、例え
ば湿度等から保護し、また外部との電気的接触を防ぐた
めの絶縁層である。As shown in this figure, 1 is a glass substrate on which an ITO electrode 2 is formed for electrical connection with the IC chip, 3 is an adhesive for fixing the IC chip and the glass substrate 1, and 4 is an adhesive. It is a conductive filler contained in the adhesive that contributes to the electrical connection between the IC chip and the ITO electrode 2, and here, the adhesive 3 and the conductive filler 4 constitute the anisotropic conductive adhesive 5. ing. 6 is IC chip, 7 is IC chip 6
AI formed above! , electrodes, 8 is an Au bump formed on the A2 electrode, and 9 is an insulating layer for protecting the circuit wiring on the IC chip from, for example, humidity and preventing electrical contact with the outside.
以上のような半導体素子の実装工程を第３図を参照しな
がら説明する。The mounting process of the semiconductor element as described above will be explained with reference to FIG.
まず、第３図（ａ）に示すように、ガラス基板からなる
回路基板１上に異方性導電接着剤５を形成する。通常こ
の工程は、予め所定の分散量で分散された導電性フィラ
ー４を含んだ異方性導電接着剤５を回路基板１上に仮接
着させる。First, as shown in FIG. 3(a), an anisotropic conductive adhesive 5 is formed on a circuit board 1 made of a glass substrate. Usually, in this step, an anisotropic conductive adhesive 5 containing a conductive filler 4 dispersed in a predetermined amount in advance is temporarily bonded onto the circuit board 1.
次に、第３図（ｂ）に示すように、回路基板１上へＡｕ
バンプ８が形成されたＩＣチップ６を位置合わせする。Next, as shown in FIG. 3(b), the Au layer is placed on the circuit board 1.
The IC chip 6 on which the bumps 8 are formed is aligned.
次に、第１図（Ｃ）に示すように、ＩＣチップ６をツー
ルにて加熱圧着し、工程が完了する。Next, as shown in FIG. 1(C), the IC chip 6 is heat-pressed using a tool to complete the process.
（発明が解決しようとする課題）
しかしながら、上記従来の半導体素子の実装工程では微
細なＩＣチップ６の電極の接続において、電気的接続が
行なわれたか否かは異方性導電接着剤５中に分散さ・れ
る導電性フィラー４の分散量に左右されると言う問題点
があった。(Problem to be Solved by the Invention) However, in the conventional semiconductor element mounting process described above, in connecting the electrodes of the minute IC chip 6, it is difficult to determine whether electrical connection has been made in the anisotropic conductive adhesive 5. There is a problem in that it depends on the amount of conductive filler 4 to be dispersed.
本発明は、上記問題点を除去し、導電性フィラーを介し
て電気的接続を行う半導体素子の実装方法において、電
気的接続不良を無くし、電気的接続の信頼性に優れた半
導体素子の実装方法を提供することを目的とする。The present invention eliminates the above-mentioned problems, eliminates electrical connection failures in a semiconductor device mounting method in which electrical connections are made via a conductive filler, and provides excellent electrical connection reliability. The purpose is to provide
（課題を解決するための手段）
本発明゛は、上記目的を達成するために、回路基板への
導電性フィラーを介した半導体素子の実装方法において
、接着剤層を接着剤１次転写用基板に形成する工程と、
該形成された接着剤層を接着剤２次基板の突起電極上の
みに転写する接着剤１次転写工程と、該突起電極上のみ
に転写された接着剤層を半導体素子の電極上のみに転写
する接着剤２次転写工程と、該半導体素子の電極上のみ
に該電極幅より小さい粒径を有する導電性フィラーを転
写する工程と、該導電性フィラーを回路基板の電極に接
続する工程とを施すようにしたものである。(Means for Solving the Problems) In order to achieve the above object, the present invention provides a method for mounting a semiconductor element onto a circuit board via a conductive filler, in which an adhesive layer is attached to a substrate for adhesive primary transfer. a step of forming the
an adhesive primary transfer step in which the formed adhesive layer is transferred only onto the protruding electrodes of the adhesive secondary substrate; and an adhesive layer transferred only onto the protruding electrodes is transferred only onto the electrodes of the semiconductor element. a secondary adhesive transfer step, a step of transferring a conductive filler having a particle size smaller than the width of the electrode only onto the electrode of the semiconductor element, and a step of connecting the conductive filler to the electrode of the circuit board. It was designed to be implemented.
（作用）
本発明によれば、上記のように構成したので、導電性フ
ィラーを介して電気的接続を行う回路基板上の半導体素
子の実装方法において、半導体素子の電極のみに接着剤
を転写し、接着剤１次及び接着剤２次転写工程を経て、
導電性フィラーの半導体素子の電極部への転写工程を有
することにより、半導体素子の電極部と回路基板電極間
での導電性フィラーの逸脱による電気的接続不良をなく
すことができる。(Function) According to the present invention, as configured as described above, in a method for mounting a semiconductor element on a circuit board in which electrical connection is made through a conductive filler, an adhesive is transferred only to the electrodes of the semiconductor element. , through the adhesive primary and adhesive secondary transfer processes,
By including the step of transferring the conductive filler to the electrode portion of the semiconductor element, it is possible to eliminate electrical connection failure due to deviation of the conductive filler between the electrode portion of the semiconductor element and the circuit board electrode.
（実施例）
以下、本発明の実施例について図面を参照しながら詳細
に説明する。(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.
第１図は本発明の実施例を示す半導体素子の実装工程断
面図である。FIG. 1 is a sectional view of a semiconductor element mounting process showing an embodiment of the present invention.
まず、第１図（ａ）に示すように、接着剤１次転写用基
板１１上に、例えば紫外線を照射することにより硬化す
る紫外線硬化型接着剤１２を、印刷法により形成する。First, as shown in FIG. 1(a), an ultraviolet curable adhesive 12 that is cured by, for example, irradiation with ultraviolet rays is formed on the adhesive primary transfer substrate 11 by a printing method.
次いで、第１図（ｂ）に示すように、接着剤１次転写用
基板ｌｌ上に突起電極１４付き接着剤２次転写用基板１
３を載置する。ここで、紫外線硬化型接着剤１２の膜厚
は、予めＩＣチップ電極と同様の電極サイズ、ピッチに
て形成された接着剤２次転写用基板１３の突起電極１４
の突起電極高さよりも薄くする。Next, as shown in FIG. 1(b), an adhesive secondary transfer substrate 1 with protruding electrodes 14 is placed on the adhesive primary transfer substrate ll.
Place 3. Here, the film thickness of the ultraviolet curable adhesive 12 is determined by the thickness of the protruding electrodes 14 of the adhesive secondary transfer substrate 13, which are formed in advance with the same electrode size and pitch as the IC chip electrodes.
Make it thinner than the height of the protruding electrode.
次に、第１図（ｃ）に示すように、紫外線硬化型接着剤
１２が形成された接着剤１次転写用基板１１に接着剤２
次転写用基板１３を押し当て、これを引き上げると、接
着剤２次転写用基板１３の突起電極１４のみに紫外線硬
化型接着剤１２が転写される。Next, as shown in FIG. 1(c), the adhesive 2 is applied to the adhesive primary transfer substrate 11 on which the ultraviolet curing adhesive 12 is formed.
When the next transfer substrate 13 is pressed and pulled up, the ultraviolet curing adhesive 12 is transferred only to the protruding electrodes 14 of the adhesive secondary transfer substrate 13.
この後、第１図（ｄ）に示すように、ＩＣチップ１５の
ＡＩ！、電極１６と接着剤２次転写用基板１３の突起電
極１４を周知の方法にて位置合わせし、ＩＣチップ１５
をフェースダウンで押し当てる。尚、１７は絶縁層であ
る。After this, as shown in FIG. 1(d), the AI of the IC chip 15! , the electrode 16 and the protruding electrode 14 of the adhesive secondary transfer substrate 13 are aligned using a well-known method, and the IC chip 15 is
Press it face down. Note that 17 is an insulating layer.
次に、第１図（ｅ）に示すように、これを引き上げると
、ＩＣチップ１５のＡｌ電極１６のみに紫外線硬化型接
着剤１２が転写される。Next, as shown in FIG. 1(e), when this is pulled up, the ultraviolet curing adhesive 12 is transferred only to the Al electrode 16 of the IC chip 15.
次に、第１図（ｆ）に示すように、紫外線硬化型接着剤
１２が転写されたＩＣチップ１５をスキージ等で均一化
された導電性フィラー１９が配置されているトレイ１８
に押し当てる。Next, as shown in FIG. 1(f), the IC chip 15 onto which the ultraviolet curable adhesive 12 has been transferred is placed on a tray 18 on which a conductive filler 19 made uniform with a squeegee or the like is placed.
press against.
次に、第１図（ｇ）に示すように、これを引き上げると
、ＩＣチップ１５のＡｌ電極１６のみに導電性フィラー
１９が設けられる。Next, as shown in FIG. 1(g), when this is pulled up, the conductive filler 19 is provided only on the Al electrode 16 of the IC chip 15.
なお、この時の導電性フィラー１９の粒径はＩＣチップ
１５のＡｌ電極１６の幅より小さい粒径が゛望ましい。Note that the particle size of the conductive filler 19 at this time is preferably smaller than the width of the Al electrode 16 of the IC chip 15.
以上で導電性フィラー転写工程が完了する。The conductive filler transfer process is thus completed.
一方、第１図（ｈ）に示すように、ＩＴＯ電極２１が形
成された回路基板２０上のＩＣチップが接続される部分
に印刷法により、導電性フィラー転写工程で使用した接
着剤と同様の紫外線硬化型接着剤２２を配置する。この
時の膜厚は導電性フィラー１９の粒径と同じかわずかに
厚い厚さが望ましい。On the other hand, as shown in FIG. 1(h), an adhesive similar to that used in the conductive filler transfer process is applied to the part of the circuit board 20 on which the ITO electrode 21 is formed, to which the IC chip is connected, by a printing method. An ultraviolet curing adhesive 22 is placed. The film thickness at this time is preferably the same as or slightly thicker than the particle size of the conductive filler 19.
最後に、第１図（ｉ）に示すように、導電性フィラー１
９が転写されたＩＣチップ１５と回路基板２０とを周知
の方法にて位置合わせし、加圧すると共に回路基板側の
光源２３から紫外線を照射することにより、半導体素子
の実装工程が完了する。Finally, as shown in FIG. 1(i), conductive filler 1
The IC chip 15 onto which 9 has been transferred and the circuit board 20 are aligned using a well-known method, pressure is applied, and ultraviolet rays are irradiated from the light source 23 on the circuit board side, thereby completing the semiconductor element mounting process.
このように構成することにより、第２図に示すように、
導電性フィラー１９を介して回路基板２０へＩＣチップ
１５を実装することができる。With this configuration, as shown in Figure 2,
The IC chip 15 can be mounted on the circuit board 20 via the conductive filler 19.
また、この時に使用する接着剤は、本実施例以外にも、
例えば熱を加えると硬化する熱硬化形の接着剤等を用い
ても同様の効果を奏することができる。この時の接着剤
の硬化方法は使用する接着剤に適した物を用いればよい
。In addition to this example, the adhesive used at this time is
For example, the same effect can be achieved by using a thermosetting adhesive that hardens when heat is applied. At this time, a method suitable for the adhesive used may be used for curing the adhesive.
更に、導電性フィラーの粒径をより微細化することによ
り微細ピッチ、微細電極の接続が可能となる。Furthermore, by making the particle size of the conductive filler finer, it becomes possible to connect fine pitches and fine electrodes.
上記工程で使用した、接着剤１次転写基板、接着剤２次
転写基板は洗浄することにより再利用が可能である。The adhesive primary transfer substrate and adhesive secondary transfer substrate used in the above steps can be reused by cleaning.
なお、本発明は上記実施例に限定されるものではなく、
本発明の趣旨に基づいて種々の変形が可能であり、これ
らを本発明の範囲から排除するものではない。Note that the present invention is not limited to the above embodiments,
Various modifications are possible based on the spirit of the present invention, and these are not excluded from the scope of the present invention.
（発明の効果）
以上、詳細に説明したように、本発明によれば、次のよ
うな効果を奏することができる。(Effects of the Invention) As described above in detail, according to the present invention, the following effects can be achieved.
導電性フィラーを介して電気的接続を行う回路基板上の
半導体素子の実装方法において、半導体素子の電極のみ
に接着剤を転写し、接着剤１次及び接着剤２次転写工程
を経て、導電性フィラーの半導体素子の電極部への転写
工程を有することにより、半導体素子の電極部と回路基
板電極間での導電性フィラーの逸脱による電気的接続不
良を無くすことができる。In a method for mounting a semiconductor element on a circuit board that makes electrical connection through a conductive filler, an adhesive is transferred only to the electrodes of the semiconductor element, and through an adhesive primary and adhesive secondary transfer process, conductive By including the step of transferring the filler to the electrode portion of the semiconductor element, it is possible to eliminate electrical connection failure due to deviation of the conductive filler between the electrode portion of the semiconductor element and the circuit board electrode.
また、半導体素子の電極部のみに接着剤を転写し、導電
性フィラーを配置するようにしているため、従来のよう
に半導体素子内に突起電極がない場合には導電性フィラ
ーにより、パッシベーションクラックを生じるといった
不具合を生じることはなくなる。つまり、本発明によれ
ば、半導体素子の電極部のみに導電性フィラーを配置す
るようにしているため、パッシベーション膜にダメージ
を与えることなく接続を行うことができる。In addition, since the adhesive is transferred only to the electrodes of the semiconductor element and the conductive filler is placed, the conductive filler prevents passivation cracks when there is no protruding electrode inside the semiconductor element as in the past. This problem will no longer occur. That is, according to the present invention, since the conductive filler is arranged only in the electrode portion of the semiconductor element, connection can be made without damaging the passivation film.
また、接着剤２次転写基板を用いることにより、突起電
極のない半導体素子の場合において、導電性フィラーを
介した半導体素子の実装を確実に行うことができる。Further, by using the adhesive secondary transfer substrate, even in the case of a semiconductor element without a protruding electrode, the semiconductor element can be reliably mounted via a conductive filler.
第１図は本発明の実施例を示す半導体素子の実装工程断
面図、第２図は本発明を適用して得られる半導体素子の
実装断面図、第３図は従来の半導体素子の実装工程断面
図、第４図はその半導体素子の実装断面図である。
１１・・・接着剤１次転写用基板、１２．２２・・・紫
外線硬化型接着剤、１３・・・接着剤２次転写用基板、
１４・・突起電極、１５・・・Ｉｃチップ、１６・・・
Ａ！電極、１７・・・絶線層、１８・・・トレイ、１９
・・・導電性フィラー、２０・・・回路基板、２１・・
・ＩＴＯ電極、２３・・・光源。
特許出願人 沖電気工業株式会社FIG. 1 is a sectional view of a mounting process of a semiconductor element showing an embodiment of the present invention, FIG. 2 is a sectional view of a mounting process of a semiconductor element obtained by applying the present invention, and FIG. 3 is a sectional view of a conventional mounting process of a semiconductor element. FIG. 4 is a sectional view of the semiconductor element mounted therein. 11... Adhesive primary transfer substrate, 12.22... Ultraviolet curable adhesive, 13... Adhesive secondary transfer substrate,
14... Projection electrode, 15... Ic chip, 16...
A! Electrode, 17... Disconnected layer, 18... Tray, 19
... Conductive filler, 20... Circuit board, 21...
- ITO electrode, 23... light source. Patent applicant Oki Electric Industry Co., Ltd.
Claims (3)
の実装方法において、 （ａ）接着剤層を接着剤１次転写用基板に形成する工程
と、 （ｂ）該形成された接着剤層を接着剤２次基板の突起電
極上のみに転写する接着剤１次転写工程と、 （ｃ）該突起電極上のみに転写された接着剤層を半導体
素子の電極上のみに転写する接着剤２次転写工程と、 （ｄ）該半導体素子の電極上のみに該電極幅より小さい
粒径を有する導電性フィラーを転写する工程と、 （ｅ）該導電性フィラーを回路基板の電極に接続する工
程とを施すことを特徴とする半導体素子の実装方法。(1) A method for mounting a semiconductor element on a circuit board via a conductive filler, which includes: (a) forming an adhesive layer on a substrate for adhesive primary transfer; (b) the formed adhesive layer (c) an adhesive primary transfer step in which the adhesive layer is transferred only onto the protruding electrodes of the adhesive secondary substrate; and (c) an adhesive 2 in which the adhesive layer transferred only on the protruding electrodes is transferred only onto the electrodes of the semiconductor element. (d) Transferring a conductive filler having a particle size smaller than the width of the electrode only onto the electrode of the semiconductor element; (e) Connecting the conductive filler to the electrode of the circuit board. A method for mounting a semiconductor device, characterized by performing the following steps.
工程において、接着剤層の厚さを接着剤２次基板の突起
電極の高さよりも薄い膜厚で形成することを特徴とする
請求項１記載の半導体素子の実装方法。(2) In the step of forming the adhesive layer on the adhesive primary transfer substrate, the thickness of the adhesive layer is formed to be thinner than the height of the protruding electrodes of the adhesive secondary substrate. 2. The method of mounting a semiconductor device according to claim 1.
を、導電性フィラーの粒径と同じか、わずかに厚くする
ことを特徴とする請求項１記載の半導体素子の実装方法
。(3) The method for mounting a semiconductor device according to claim 1, wherein the thickness of the adhesive layer in the adhesive secondary transfer step is equal to or slightly thicker than the particle size of the conductive filler.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2203971A JP2596633B2 (en) | 1990-08-02 | 1990-08-02 | Semiconductor element mounting method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2203971A JP2596633B2 (en) | 1990-08-02 | 1990-08-02 | Semiconductor element mounting method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0491444A true JPH0491444A (en) | 1992-03-24 |
| JP2596633B2 JP2596633B2 (en) | 1997-04-02 |
Family
ID=16482667
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2203971A Expired - Fee Related JP2596633B2 (en) | 1990-08-02 | 1990-08-02 | Semiconductor element mounting method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2596633B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6482676B2 (en) | 1997-01-09 | 2002-11-19 | Fujitsu Limited | Method of mounting semiconductor chip part on substrate |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01227444A (en) * | 1988-03-07 | 1989-09-11 | Sharp Corp | Connection structure |
-
1990
- 1990-08-02 JP JP2203971A patent/JP2596633B2/en not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01227444A (en) * | 1988-03-07 | 1989-09-11 | Sharp Corp | Connection structure |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6482676B2 (en) | 1997-01-09 | 2002-11-19 | Fujitsu Limited | Method of mounting semiconductor chip part on substrate |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2596633B2 (en) | 1997-04-02 |
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