JPH0491445A - Mounting method for semiconductor element - Google Patents
Mounting method for semiconductor elementInfo
- Publication number
- JPH0491445A JPH0491445A JP2203972A JP20397290A JPH0491445A JP H0491445 A JPH0491445 A JP H0491445A JP 2203972 A JP2203972 A JP 2203972A JP 20397290 A JP20397290 A JP 20397290A JP H0491445 A JPH0491445 A JP H0491445A
- Authority
- JP
- Japan
- Prior art keywords
- adhesive
- conductive filler
- semiconductor element
- mounting
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 36
- 238000000034 method Methods 0.000 title claims abstract description 31
- 239000000853 adhesive Substances 0.000 claims abstract description 40
- 230000001070 adhesive effect Effects 0.000 claims abstract description 40
- 239000011231 conductive filler Substances 0.000 claims abstract description 35
- 239000002245 particle Substances 0.000 claims description 5
- 239000000945 filler Substances 0.000 abstract 6
- 239000000758 substrate Substances 0.000 description 7
- 230000000694 effects Effects 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000011295 pitch Substances 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は、回路基板上への半導体素子、つまり、集積回
路（以下、ＩＣという）の実装方法に関するものである
。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method of mounting a semiconductor element, that is, an integrated circuit (hereinafter referred to as IC) on a circuit board.
（従来の技術）
従来、このような分野の技術としては、例えば特開昭６
２−２４４１４２号に記載されるようなものがあった。(Prior art) Conventionally, as a technology in this field, for example, Japanese Patent Application Laid-open No. 6
There was one described in No. 2-244142.
第４図はかかる従来の半導体素子の実装断面図である。FIG. 4 is a cross-sectional view of such a conventional semiconductor device.
この図に示すように、１はＩＣチップとの電気的接続を
とるためのＩＴＯ電極２が形成されたガラス基板、３は
ＩＣチップとガラス基板１とを固定接着するための接着
剤、４はＩＣチップとＩＴＯ電極２との電気的接続に寄
与し接着剤中に含まれる導電性フィラーであり、ここで
、接着剤３と導電性フィラー４とで、異方性導電接着剤
５を構成している。６はＩＣチップ、７はＩＣチップ６
上に形成されたＡｎ電極、８はＡｎ電極上に形成された
Ａｕバンブ、９はＩＣチップ上の回路配線を、例えば湿
度等から保護し、また外部との電気的接触を防ぐための
絶縁層である。As shown in this figure, 1 is a glass substrate on which an ITO electrode 2 is formed for electrical connection with the IC chip, 3 is an adhesive for fixing the IC chip and the glass substrate 1, and 4 is an adhesive. It is a conductive filler contained in the adhesive that contributes to the electrical connection between the IC chip and the ITO electrode 2, and here, the adhesive 3 and the conductive filler 4 constitute the anisotropic conductive adhesive 5. ing. 6 is IC chip, 7 is IC chip 6
An electrode formed on the top, 8 an Au bump formed on the An electrode, 9 an insulating layer for protecting the circuit wiring on the IC chip from humidity, etc., and also for preventing electrical contact with the outside. It is.
以上のような半導体素子の実装工程を第３図を参照しな
がら説明する。The mounting process of the semiconductor element as described above will be explained with reference to FIG.
まず、第３図（ａ）に示すように、ガラス基板からなる
回路基板ｌ上に異方性導電接着剤５を形成する０通常こ
の工程は、予め所定の分散量で分散された導電性フィラ
ー４を含んだ異方性導電接着剤５を回路基板１上に仮接
着させる。First, as shown in FIG. 3(a), an anisotropic conductive adhesive 5 is formed on a circuit board 1 made of a glass substrate. Normally, this process involves using a conductive filler dispersed in a predetermined amount in advance. An anisotropic conductive adhesive 5 containing 4 is temporarily bonded onto the circuit board 1.
次に、第３図（ｂ）に示すように、回路基板１上へＡｕ
バンプ８が形成されたＩＣチップ６を位置合わせする。Next, as shown in FIG. 3(b), the Au layer is placed on the circuit board 1.
The IC chip 6 on which the bumps 8 are formed is aligned.
次に、第３図（ｃ）に示すように、ＩＣチップ６をツー
ルにて加熱圧着し工程が完了する。Next, as shown in FIG. 3(c), the IC chip 6 is heat-pressed using a tool to complete the process.
（発明が解決しようとする課題）
しかしながら、上記従来の半導体素子の実装工程では微
細なＩＣチップ６の電極の接続において、電気的接続が
行なわれたか否かは異方性導電接着剤５中に分散される
導電性フィラー４の分散量に左右されると言う問題点が
あった。(Problem to be Solved by the Invention) However, in the conventional semiconductor element mounting process described above, in connecting the electrodes of the minute IC chip 6, it is difficult to determine whether electrical connection has been made in the anisotropic conductive adhesive 5. There is a problem in that it depends on the amount of conductive filler 4 dispersed.
本発明は、上記問題点を除去し、導電性フィラーを介し
て電気的接続を行う半導体素子の実装方法において、電
気的接続不良をなくし、電気的接続の信幀性に優れた半
導体素子の実装方法を提供することを目的とする。The present invention eliminates the above-mentioned problems, eliminates electrical connection defects in a semiconductor device mounting method in which electrical connections are made via a conductive filler, and provides semiconductor device mounting with excellent electrical connection reliability. The purpose is to provide a method.
（課題を解決するための手段）
本発明は、上記目的を達成するために、回路基板への導
電性フィラーを介した半導体素子の実装方法において、
半導体素子の電極のみに接着剤を形成する接着剤転写工
程と、該接着剤が形成された電極のみに導電性フィラー
を転写する工程と、該導電性フィラーを介して回路基板
へ実装する工程とを施すようにしたものである。(Means for Solving the Problems) In order to achieve the above object, the present invention provides a method for mounting a semiconductor element onto a circuit board via a conductive filler.
An adhesive transfer step of forming an adhesive only on the electrodes of a semiconductor element, a step of transferring a conductive filler only to the electrodes on which the adhesive has been formed, and a step of mounting onto a circuit board via the conductive filler. It was designed to do this.
（作用）
本発明によれば、上記のように構成したので、導電性フ
ィラーを介して電気的接続を行う回路基板上の半導体素
子の実装方法において、導電性フィラーの半導体素子の
電極部への転写工程を有することにより、導電性フィラ
ーを半導体素子の電極部に集中することができ、半導体
素子の電極部と回路基板の電極間での導電性フィラーの
逸脱による電気的接続不良を無くすことができる。(Function) According to the present invention, as configured as described above, in a method for mounting a semiconductor element on a circuit board in which electrical connection is made via a conductive filler, the conductive filler is attached to the electrode portion of the semiconductor element. By having a transfer process, the conductive filler can be concentrated on the electrode part of the semiconductor element, and it is possible to eliminate electrical connection failure due to deviation of the conductive filler between the electrode part of the semiconductor element and the electrode of the circuit board. can.
（実施例）
以下、本発明の実施例について図面を参照しながら詳細
に説明する。(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.
第１図は本発明の実施例を示す半導体素子の実装工程断
面図である。FIG. 1 is a sectional view of a semiconductor element mounting process showing an embodiment of the present invention.
まず、第１図（ａ）に示すように、接着剤転写用基板１
１上に、例えば紫外線を照射することにより硬化する紫
外線硬化型接着剤１２を印刷法により形成する。First, as shown in FIG. 1(a), an adhesive transfer substrate 1
1, an ultraviolet curable adhesive 12 that is cured by irradiation with ultraviolet light is formed by a printing method, for example.
次いで、第１図（ｂ）に示すように、この接着剤転写用
基板ｌｌ上にＩＣチップ１３をフェースダウンで押し当
てる。ここで、紫外線硬化型接着剤１２の膜厚は、接着
剤転写用基板ｌｌ上にＩＣチップ１３のＡ ｕ ノ？ン
プ１５の高さよりも薄い膜厚にて配置する。Next, as shown in FIG. 1(b), the IC chip 13 is pressed face down onto this adhesive transfer substrate ll. Here, the film thickness of the ultraviolet curable adhesive 12 is the thickness of the IC chip 13 on the adhesive transfer substrate ll. The film thickness is thinner than the height of the pump 15.
なお、１４はＡＩ！、電極、１６は絶縁層である。In addition, 14 is AI! , electrodes, and 16 are insulating layers.
次に、第１図（ｃ）に示すように、ＩＣチップ１３を引
き上げると、ＩＣチップ１３のＡｕバンプ１５のみに紫
外線硬化型接着剤１２が転写される。Next, as shown in FIG. 1(c), when the IC chip 13 is pulled up, the ultraviolet curing adhesive 12 is transferred only to the Au bumps 15 of the IC chip 13.
この後、第１図（ｄ）に示すように、紫外線硬化型接着
剤１２が転写されたＩＣチップ１３をスキージ等で均一
化された導電性フィラー１８が配置されているトレイ１
７に押し当てる。Thereafter, as shown in FIG. 1(d), the IC chip 13 onto which the ultraviolet curable adhesive 12 has been transferred is placed on a tray 1 on which a uniform conductive filler 18 is placed using a squeegee or the like.
Press it on 7.
次に、第１図（ｅ）に示すように、これを引き上げると
、ＩＣチップ１３のＡｕバンプ１５のみに導電性フィラ
ー１８が設けられる。なお、この時の導電性フィラー１
８の粒径はＡｕバンプ１５の高さよりも小さい粒径が望
ましい。Next, as shown in FIG. 1(e), when this is pulled up, the conductive filler 18 is provided only on the Au bumps 15 of the IC chip 13. In addition, at this time, conductive filler 1
It is desirable that the particle size of No. 8 is smaller than the height of the Au bump 15.
以上で導電性フィラー転写工程が完了する。The conductive filler transfer process is thus completed.
一方、第１図（ｆ）に示すように、ＩＴＯ電極２１が形
成された回路基板２０上のＩＣチップが接続される部分
に印刷法により、導電性フィラー転写工程で使用した接
着剤と同様の紫外線硬化型接着剤２２を配置する。この
時の膜厚は、Ａｕバンプ高さと導電性フィラー粒径の和
と同じか、わずかに厚い厚さが望ましい。On the other hand, as shown in FIG. 1(f), an adhesive similar to the one used in the conductive filler transfer process is applied to the part of the circuit board 20 on which the ITO electrode 21 is formed, to which the IC chip is connected, by a printing method. An ultraviolet curing adhesive 22 is placed. The film thickness at this time is preferably the same as the sum of the Au bump height and the conductive filler particle size, or slightly thicker.
最後に、第１図（ｇ）に示すように、導電性フィラー１
８が転写されたＩＣチップ１３と回路基板２０とを周知
の方法にて位置合わせし、加圧すると共に回路基板側の
光源２３から紫外線を照射することにより、半導体素子
の実装工程が完了する。Finally, as shown in FIG. 1(g), conductive filler 1
The IC chip 13 onto which 8 has been transferred and the circuit board 20 are aligned using a well-known method, pressure is applied, and ultraviolet rays are irradiated from the light source 23 on the circuit board side, thereby completing the semiconductor element mounting process.
このように構成することにより、第２図に示すように、
導電性フィラー１８を介して確実な電気的接続を行うこ
とができる回路基板２０への半導体素子１３の実装を行
うことができる。With this configuration, as shown in Figure 2,
The semiconductor element 13 can be mounted on the circuit board 20 with a reliable electrical connection via the conductive filler 18.
また、この時に使用する接着剤は、本実施例以外にも、
例えば熱を加えると硬化する熱硬化形の接着剤等を用い
ても同様の効果を奏することができる。この時の接着剤
の硬化方法は使用する接着剤に適した物を用いればよい
。In addition to this example, the adhesive used at this time is
For example, the same effect can be achieved by using a thermosetting adhesive that hardens when heat is applied. At this time, a method suitable for the adhesive used may be used for curing the adhesive.
更に、導電性フィラーの粒径をより微細化することによ
り微細ピッチ、微細電極の接続が可能となる。Furthermore, by making the particle size of the conductive filler finer, it becomes possible to connect fine pitches and fine electrodes.
なお、本発明は上記実施例に限定されるものではなく、
本発明の趣旨に菟づいて種々の変形が可能であり、これ
らを本発明の範囲から排除するものではない。Note that the present invention is not limited to the above embodiments,
Various modifications can be made within the spirit of the present invention, and these are not excluded from the scope of the present invention.
（発明の効果）
以上、詳細に説明したように、本発明によれば、次のよ
うな効果を奏することができる。(Effects of the Invention) As described above in detail, according to the present invention, the following effects can be achieved.
導電性フィラーを介して電気的接続を行う回路基板上の
半導体素子の実装方法において、導電性フィラーの半導
体素子の電極部への転写工程を有することにより、導電
性フィラーを半導体素子の電極部に集中することができ
、半導体素子の電極部と回路基板の電極間での導電性フ
ィラーの逸脱による電気的接続不良をなくすことができ
る。In a method for mounting a semiconductor element on a circuit board in which electrical connection is made via a conductive filler, the conductive filler can be transferred to the electrode part of the semiconductor element by including a step of transferring the conductive filler to the electrode part of the semiconductor element. It is possible to eliminate electrical connection defects due to deviation of the conductive filler between the electrode portion of the semiconductor element and the electrode of the circuit board.
第１図は本発明の実施例を示す半導体素子の実装工程断
面図、第２図は本発明にかかる半導体素子の実装断面図
、第３図は従来の半導体素子の実装工程断面図、第４図
は従来の半導体素子の実装断面図である。
１１・・・接着剤転写用基板、１２・・・紫外線硬化型
接着剤、１３・・・ＩＣチップ、１４・・・Ａｆｆｉ電
極、１５・・・Ａｕバンプ、１６・・・絶縁層、１７・
・・トレイ、１８・・・導電性フィラー、２０・・・回
路基板、２１・・・ＩＴＯ電極、２３・・・光源。
特許出願人 沖電気工業株式会社
代理人 弁理士 清 水 守（外１名）ｌ′ｒ）寸
鴇
＼ ＼ ＼
知
し、FIG. 1 is a cross-sectional view of a mounting process of a semiconductor element showing an embodiment of the present invention, FIG. 2 is a cross-sectional view of a mounting process of a semiconductor element according to the present invention, FIG. 3 is a cross-sectional view of a conventional semiconductor element mounting process, and FIG. The figure is a cross-sectional view of a conventional semiconductor device. DESCRIPTION OF SYMBOLS 11... Adhesive transfer substrate, 12... Ultraviolet curing adhesive, 13... IC chip, 14... Affi electrode, 15... Au bump, 16... Insulating layer, 17...
...Tray, 18... Conductive filler, 20... Circuit board, 21... ITO electrode, 23... Light source. Patent Applicant: Oki Electric Industry Co., Ltd. Agent: Patent Attorney: Mamoru Shimizu (1 other person) l'r) Suntoki \ \ \ \ Chishi,
Claims (4)
の実装方法において、 （ａ）半導体素子の電極のみに接着剤を形成する接着剤
転写工程と、 （ｂ）該接着剤が形成された電極のみに導電性フィラー
を転写する工程と、 （ｃ）該導電性フィラーを介して回路基板へ実装する工
程とを施すことを特徴とする半導体素子の実装方法。(1) A method for mounting a semiconductor element on a circuit board via a conductive filler, which includes (a) an adhesive transfer step of forming an adhesive only on the electrodes of the semiconductor element, and (b) a step in which the adhesive is formed. A method for mounting a semiconductor device, comprising: transferring a conductive filler only to an electrode; and (c) mounting the conductive filler onto a circuit board via the conductive filler.
導体素子の電極の高さよりも薄い膜厚にしたことを特徴
とする請求項１記載の半導体素子の実装方法。(2) The method for mounting a semiconductor device according to claim 1, wherein in the adhesive transfer step, the thickness of the adhesive is made thinner than the height of the electrode of the semiconductor device.
フィラー粒径を、半導体素子の電極の高さよりも小さい
粒径にしたことを特徴とする請求項１記載の半導体素子
の実装方法。(3) The method for mounting a semiconductor device according to claim 1, wherein in the step of transferring the conductive filler, the particle size of the conductive filler is made smaller than the height of the electrode of the semiconductor device.
、接着剤の膜厚を、半導体素子の電極の高さと導電性フ
ィラーの粒径の和と同じか、わずかに厚い厚さにするこ
とを特徴とする請求項１記載の半導体素子の実装方法。(4) In the process of mounting the semiconductor element on the circuit board, the film thickness of the adhesive should be equal to or slightly thicker than the sum of the height of the electrode of the semiconductor element and the particle size of the conductive filler. A method for mounting a semiconductor device according to claim 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2203972A JPH0491445A (en) | 1990-08-02 | 1990-08-02 | Mounting method for semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2203972A JPH0491445A (en) | 1990-08-02 | 1990-08-02 | Mounting method for semiconductor element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0491445A true JPH0491445A (en) | 1992-03-24 |
Family
ID=16482683
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2203972A Pending JPH0491445A (en) | 1990-08-02 | 1990-08-02 | Mounting method for semiconductor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0491445A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6482676B2 (en) | 1997-01-09 | 2002-11-19 | Fujitsu Limited | Method of mounting semiconductor chip part on substrate |
-
1990
- 1990-08-02 JP JP2203972A patent/JPH0491445A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6482676B2 (en) | 1997-01-09 | 2002-11-19 | Fujitsu Limited | Method of mounting semiconductor chip part on substrate |
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