JPH0488753A - Clamping circuit - Google Patents

Abstract

PURPOSE:To clamp an input signal with high accuracy by clamping once an input signal, integrating it to produce a clamp level signal and using a differential amplifier means to add/subtract the clamp level signal to/from the input signal thereby sending an output signal. CONSTITUTION:A clamp pulse P and a clamp level E inputted are used to clamp an input video signal VIN to the clamp level E in a timing of the clamp pulse P and a clamp video signal VC obtained as a result is sent to an integration device 13. The integration device 13 integrates the signal VC to eliminate effectively a produced undesired high frequency component by means of a capacitor and the resulting signal is used as a clamp level signal VC1 and inputted to an inverting input terminal of a differential amplifier 11. Thus, the differential amplifier 11 adds/subtracts the signal VC1 to/from the signal VIN and then the DC component of the signal VIN is recovered based on the signal VC1 to send an output video signal VOUT1. Thus, a capacitor is not inserted in series with the signal line for the signals VIN and VOUT1 in this way, then the signal VOUT1 resulting from clamping the signal VIN is obtained with high accuracy.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a clamp circuit, and is applicable to, for example, DC reproduction (hereinafter referred to as a clamp) of a video signal in a television receiver or a MUSE decoder. [Technology] Conventionally, in television receivers, MUSE decoders, etc., a clamp circuit is used to clamp the pedestal level of a received video signal.

That is, as shown in FIG. 3, the lamp circuit 1 has a capacitor C1 connected in series to the signal line L1, and a DC signal (so-called clamp level E) is applied to the output side of the capacitor C1 through a switch 2. It is configured by a power supply 3 to be supplied.

In practice, the switch 2 of this clamp circuit 1 is controlled on/off by a clamp pulse P generated based on a horizontal synchronizing signal separated from the video signal, thereby controlling the DC level across the capacitor C1 to control the input video signal. VIN
output video signal VOU by clamping the pedestal level of
T can be transmitted.

[Problems to be Solved by the Invention] However, in the clamp circuit 1 having such a configuration, the capacitor C1 is inserted in series with the signal line L1, and the performance of the capacitor C1, such as leakage current and frequency characteristics, directly affects the clamp characteristics. Therefore, there was a problem in that noise generated by the capacitor C1 was mixed into the output video signal VOUT.

In addition to this, in order to maintain the charge charged in the capacitor C1, the input impedance of the downstream stage of the clamp circuit 1 is selected to a high value, and for this reason, the switch 2
In this case, it was not possible to avoid the possibility that switching noise would occur.

The present invention has been made in consideration of the above points, and aims to solve the conventional problems at once and propose a clamp circuit that can clamp input signals with high precision.

[Means for Solving the Problems] In order to solve the problems, the present invention provides clamp level signal generation means for clamping an input signal and integrating the clamping result to generate a clamp level signal; A differential amplification means is provided which receives a clamp level signal, adds and subtracts the clamp level signal from the input signal, and outputs an output signal obtained by clamping the input signal.

[Function] The clamp level signal generating means once clamps and integrates the input signal to generate a clamp level signal, and the differential amplifying means 11 adds and subtracts the clamp level signal from the input signal to send out an output signal. By doing so, it is possible to clamp the output signal while preventing noise from being mixed into the output signal, and thus the input signal can be clamped with high precision.

Embodiment Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

In FIG. 1, in which parts corresponding to those in FIG. 3 are given the same reference numerals, 10 indicates a clamp circuit based on this embodiment G as a whole, and a clamp section 12 and an integrator 13 constitute a clamp level generating means. It's 0.

The input video signal VIN (FIG. 2(A)) is input to the differential amplifier 11.
It is input to the non-inverting input terminal of , and is also input to the clamp section 12 .

This clamp section 12 has the same configuration as the conventional clamp circuit 1 (FIG. 3), and has an input clamp pulse P (
2 (B)) and a clamp level (e.g. feed pan/nk level) E, the input video signal VIN is clamped to the clamp level E at the timing of the clamp pulse P, and the resulting clamped video signal VC is integrated. Device 1] is sent.

The integrator 13 integrates the clamped video signal VC, effectively removes unnecessary high-frequency components such as noise components and switching noise components generated by the capacitor C1 (see FIG. 3), and transfers this to the clamp circuit J. Signal VC1 (Figure 2 (C))
The signal is inputted to the inverting input terminal of the differential amplifier 11 as a signal.

As a result, the differential amplifier 11 adds or subtracts the clamp level signal VCI from the input video signal VIN, thus converting the DC component of the input video signal VIN into the clamp level signal VCI.
The output video signal V is reproduced, that is, clamped, based on
OtJT1 (FIG. 2(D)) can be sent.

In this way, in the case of this clamp circuit 10, since a capacitor is not inserted in series between the signal lines of the input video signal VIN and the output video signal VOUT1, the performance of the capacitor such as leakage current and frequency characteristics does not depend on the performance of the capacitor. , an output video signal VOtJTl can be obtained by clamping the input video signal IN with high accuracy.

According to the above configuration, the input video signal is once clamped and integrated to generate a clamp level signal, and the clamp level signal is added or subtracted from the input video signal, thereby clamping the input video signal with high precision. A clamp circuit that can send out an output video signal can be realized.

In the above-described embodiments, the present invention is applied to a television receiver or a MUSE decoder, but the present invention is not limited to this, and can be applied to clamping a video signal in other video signal processing systems such as a video tape recorder. Can be widely applied to

Incidentally, in the case of the clamp circuit of this embodiment, the input video signal can be clamped with high precision, which is useful for video tape recorders in which the minute signal level of the input signal can have a large effect on the reproduced image through subsequent signal processing. It is most suitable for application in video signal processing circuits.

Further, in the above-described embodiments, the present invention is applied to the case of clamping a video signal, but the present invention is not limited to this, but in short, the present invention can be widely applied and suitable when obtaining an output signal by clamping various input signals. It is something.

Effects of the Invention As described above, according to the present invention, an input signal is once clamped and integrated to generate a clamp level signal, and the clamp level signal is added or subtracted from the input signal, thereby providing a simple With this configuration, it is possible to realize a clamp circuit that can clamp input signals with high precision.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the clamp circuit according to the present invention, FIG. 2 is a timing chart for explaining its operation, and FIG. 3 is a connection diagram showing a conventional clamp circuit. 1.10... Clamp circuit, 2... Switch, 3... Power supply, 11... Differential amplifier, 12... Clamp section , 13...
Integrator.

Claims (1)

[Claims] Clamp level signal generating means for clamping an input signal and integrating the clamp result to generate a clamp level signal; the input signal and the clamp level signal are input;
A clamp circuit comprising differential amplification means for adding and subtracting the clamp level signal from the input signal and outputting an output signal obtained by clamping the input signal.