JPH0488534A - Memory access controller - Google Patents

Abstract

PURPOSE:To perform the pre-reading of effective data and to perform fast readout processing by providing a control means which controls the transfer of held pre-read data to an access request means. CONSTITUTION:When a read cycle for memory is started from a request device 2 that becomes the access request means, a difference detector 15 detects address difference from the request device 2 by monitoring a read address requested almost simultaneously sequentially. The adder 17 of an arithmetic means predicts the next read address from the address difference. A data register 21 that is a holding means holds the data pre-read from the memory based on a computed address. The control means controls the transfer of the pre-read data held in the data register 21 when the next read access for image memory 3 is performed from the request device 2.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory access control device that controls read access to memory instructed by a host.

[Conventional technology 1] Conventionally, in this type of memory controller, when a read request for data is made from a host (mainly a CPU, DMAC, etc.) requesting to read data stored at a specific address in the memory, the request becomes effective immediately. Instead of outputting valid data, valid data is output after a certain amount of time has passed. During this certain period of time, from the perspective of the host that made the data read request, it becomes a waiting time, which affects the processing speed.

In general, read requests to memory are often made to consecutive addresses, and various methods have been used to improve the processing speed regarding memory access.

For example, "1" is added to the address where the data read request was made.
The contents of the memory indicated by the address consecutive to the requested address are pre-read in advance, and the next time a data read request is made, if the read-requested address and the address of the pre-read data are equal. , the prefetched data is returned to the data request destination as memory data without waiting time.

[Problem to be Solved by the Invention 1] However, when the data has a data structure that is concentrated in a specific area, such as image data, for example,
Assuming image data (2) to be displayed on the display as shown in the figure, the read addresses for the image data (2) are not all consecutive.

FIG. 5 is a schematic diagram showing a memory map of the image memory for the image data (1) shown in FIG.

As can be seen from this figure, the image data ■ is stored in a bitmap with a one-to-one correspondence between the data for the display and the data on the memory, and when the image data ■ is read continuously, the corresponding read address is It becomes a data structure with characteristics that change with a certain difference.

Therefore, with conventional read-ahead access processing that is effective only for consecutive addresses, it is not possible to read the image data at high speed as described above, and there is a problem in that the image data processing efficiency is significantly reduced. .

This invention was made to solve the above problems, and focuses on the structure of data in which read addresses are periodically stored with a certain difference, and the read cycle for data stored in memory is It is an object of the present invention to provide a memory access control device that can read and process data in a memory having a specific data structure at high speed by monitoring read addresses requested during the process and predicting an optimal read-ahead address.

[Means to solve the problem]

The memory access control device according to the present invention includes a pressure detection means for sequentially monitoring read addresses requested one after another by an access requesting means and detecting an address difference, and a pressure detection means for detecting an address difference by sequentially monitoring read addresses requested one after another by an access requesting means; a calculation means for predicting and calculating the next read address; a holding means for holding the pre-read data read ahead from the memory based on the address calculated by the calculation means; and a next read access to the memory requested by the access request means. and control means for sequentially comparing the read address calculated by the calculation means with the address requested by the access request means and controlling the transfer of the pre-read data held in the holding means to the access request means. It is something.

[Operation] In the present invention, when a read cycle for the memory is started by the access requesting means, the detection means sequentially monitors read addresses successively requested by the access requesting means and detects an address difference. Based on the detected address difference, a calculation means predicts and calculates the next read address based on the address difference. The holding means holds the pre-read data pre-read from the memory based on the calculated address, and at the time of the next read access to the memory requested by the access requesting means, the control means uses the calculated next read address and the access. It is possible to control the transfer of the preread data held in the holding means to the access requesting means by sequentially comparing the addresses requested by the requesting means, and to transfer the preread data as data requested by the access requesting means. do.

[Embodiment 1] FIG. 1 is a block diagram illustrating the configuration of a memory access control device showing an embodiment of the present invention. Reference numeral 1 denotes a memory access controller, and numeral 1 denotes a memory access controller that performs an access request to read data from the image memory 3. A requesting device 2 (which serves as a requesting means)
For example, DMAC.

It accepts memory accesses from the image memory 3 (MPU, etc.) via an address line L1, and returns image data read from the image memory 3 via a data line L2.

A selector 11 writes a requested read address while sequentially selecting either the address register 13 or the address register 14 based on a switching control signal sent from the control section 12. address register 1
3 or the address register 14 holds the two most recent read addresses in sequence by the selector 11. 15 is a difference detector which functions as a detection means, and when the read address held in the address register 13 or the address register 14 is valid, it detects the old address data from the new address data based on each address data. The difference address is detected by subtraction, and the difference address is output to the adder 17. 16 is a selector which selects the newer read address from either the address register 13 or the address register 14 based on the selection control signal sent from the control unit 12, and sequentially selects the new read address from the adder. Send on 17th. The control unit 12 has a selector 11 . Difference detector 15, selector 1
6, address register 13.1
4. Manage the validity of the address data stored in 4 and which address data is stored with new address data.
Select that state with selector 11. Difference detector 15. Selector 1
6 will be notified. 17 is an adder that adds the difference between the addresses output from the difference detector 15 and the address data output from the selector 16; Reference numeral 18 denotes a memory access control unit which, if the data output from the adder 17 is valid, controls the pre-reading process of the data to the image memory 3 using the data as address data, and the pre-read image data is stored in the data register 21. Ru.

19 is a comparator that compares and determines the address at which the requesting device 2 made a read request to the image memory 3 with the pre-read address outputted from the adder 17 and read ahead into the image memory 3, and sends the result to the memory. The access control unit 18 and selector 20 are notified. In addition to the above-mentioned prefetch control, the memory access control unit 18 notifies the comparator 19 that the result of the comparison judgment is the address and data of the read request currently being made by the requesting device 2 to the image memory 3. If the prefetched address is different,
Data is also read from the image memory 3 regarding the address of the read request requested by the requesting device 2 to the image memory 3.

As a result, the data output from the image memory 3 is input to the selector 20. If the result notified by the comparator 19 indicates that the address of the read request currently made by the requesting device 2 to the image memory 3 is equal to the address at which the data was read ahead, the selector 20 selects ,
Switching is performed to return the pre-read data stored in the data register 21 to the requesting device 2, or the result of the data read performed by the memory access control unit 18 from the image memory 3. L3 is an address line that indicates the address of a read request made to the image memory 3. L4 is a data line that outputs data read in response to a read request to the data register 21 or selector 20.

In the memory access control device configured as described above, when a read cycle is started from the requesting device 2 serving as the access requesting device to the rememory (in this embodiment, the image memory 3), the detection device (in this embodiment, the difference detector 15
) sequentially monitors the read addresses requested one after another from the requesting device 2 and detects an address difference. Based on the detected address difference, a calculation means (in this embodiment, the calculator 17) predicts and calculates the next read address based on the address difference. Then, the holding means (data selector 21 in this embodiment) holds the pre-read data pre-read from the memory based on the calculated address, and controls the data at the time of the next read access to the image memory 3 requested by the requesting device 2. Means (in this embodiment, it is composed of a memory access control unit 18, a comparator 19, a selector 20, etc.)
The data register 21 sequentially compares the calculated next read address with the address requested by the requesting device 2.
It controls the transfer of the pre-read data held in the request device 2 to the access requesting means, and transfers the pre-read data as data requested by the requesting device 2.

Next, data processing operations in the memory access control device according to the present invention will be explained with reference to FIGS. 2 and 3.

FIG. 2 is a schematic diagram illustrating a data processing state between the memory access controller 1 and the requesting device 2 shown in FIG. 1, and the horizontal axis indicates time.

In the figure, TO, T2. T4 indicates a read timing, and indicates that the requesting device 2 is reading data from the image memory 3 during this time. Tl, T3. T5 indicates pre-read processing timing, read timing To,
T2. Data corresponding to the differential address is stored in the data register 21 using free time that does not conflict with T4.

Note that read timing To, T2. T4 is requesting device 2
Indicates the shortest time for read processing performed by
o, T2. At T'4, the time required to make the data in the image memory 3 valid is added.

FIG. 3 is a flowchart illustrating an example of a memory access processing procedure according to the present invention. In addition, (1) to (7
) indicates each step.

First, it is determined whether the requesting device 2 has made a data read request to the image memory 3 (1). If a read request has been made, the validity of the data stored in the address registers 13 and 14 (for example, If the requesting device 2 has never made a read request to the image memory 3 or has made a read request only - times, the address register 13 is stored in one or both of the address registers 13 and 14. If the data stored in the address register 13 and the address register 14 are valid, the comparison judgment result notified by the comparator 19 is checked (2), and the comparator 19 The result of the comparison is indicated by the output of the adder 17, and the address at which the data was pre-fetched to the image memory 3 and the address at which the requesting device 2 is currently making a read request to the image memory 3. indicates equality, proceed to step (3), otherwise proceed to step (
Proceed to 4).

In other words, the contents of the address registers 13 and 14 are both valid, and the address at which the data was prefetched to the image memory 3 is equal to the address at which the requesting device 2 is currently issuing a read request to the image memory 3. 2) If YES, the requesting device 2 assumes that the pre-read data is correct as a result of the current read request to the image memory 3, and sends the data stored in the data register 21 to the requesting device 2. Return 3), proceed to step (5) and after, and if No, the pre-read data is invalidated and the memory access control unit 18 executes the read request that the requesting device 2 is currently making to the image memory 3. 4) and sends the result back to the requesting device 2.

Next, the address of the read request requested by the requesting device 2 to the image memory 3 is stored in either the address register 13 or the address register 14 (5). Note that the selection of the address register 13 or 14 to be stored is determined by the control unit. 12, the new address is stored in the register holding the older address data.

Next, determine the validity of the data stored in the address registers 13 and 14. 6) If no, return to step (1), and if YES, that is, both data are valid, the control unit 12 will notify you. According to the contents, an address difference is detected based on the data stored in the address register 13 and the address register 14, an address for pre-reading is generated for the image memory 3, and the pre-reading is performed by the memory access control unit 18. , store the result in the data register 21 (7)
When the series of processing is completed, return to step (1).

In the above embodiment, two address registers 13.1
4, and by holding the addresses of the last two read requests to the image memory 3 in each address register 13 and 14, detection of the difference and holding the address to be read ahead is achieved, but the present invention is not limited to this. However, other configurations may be used.

Further, in the above embodiment, a case has been described in which the requesting device 2 that makes a read request to the image memory 3 and the memory access controller 1 are configured independently, but the configuration is not limited to such a configuration, and for example, Image memory 3
The configuration may be incorporated into a device that makes a read request to a device.

[Effects of the Invention] As explained above, the present invention includes a detecting means for detecting an address difference by sequentially monitoring read addresses requested one after another by an access requesting means, and an address difference detected by the detecting means. a calculation means for predicting and calculating the next read address based on the calculation means; a holding means for holding the preread data read ahead from the memory based on the address calculated by the calculation means; and a calculation means for predicting the next read address based on the address calculated by the calculation means; During read access,
Since the control means is provided to sequentially compare the read address calculated by the calculation means and the address requested by the access request means and control the transfer of the pre-read data held in the holding means to the access request means, When performing a read cycle on a memory in which consecutive accesses are made not to consecutive addresses but to addresses with a certain difference, data valid for the access requesting means can be read in advance. Therefore, it is possible to read and process data in memory having a specific data structure at high speed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram explaining the configuration of a memory access control device showing an embodiment of the present invention, and FIG. 2 is a schematic diagram explaining the data processing state between the memory access controller and the requesting device shown in FIG. 3 is a flowchart explaining an example of the memory access processing procedure according to the present invention, FIG. 4 is a schematic diagram explaining the structure of image data for display, and FIG. 5 is an image of the image shown in FIG. 4. FIG. 3 is a schematic diagram showing a memory map of an image memory for data. In the figure, 1 is a memory access controller, 2 is a requesting device, 3 is an image memory, 11, 16.20 is a selector, 12
is a control unit, 13.14 is an address register, 15 is a difference detector, 17 is an adder, 18 is a memory access control unit,
19 is a comparator, and 21 is a data selector. Figure 2 and Figure 4

Claims (1)

[Claims] A memory comprising: access requesting means for requesting the memory to read data; and access control means for transferring data read from the memory to the access requesting means based on a read address from the access requesting means. The access control device includes a detection means for sequentially monitoring read addresses requested one after another by the access request means and detecting an address difference, and a detection means for detecting an address difference detected by the detection means, and a detection means for determining the next read address based on the address difference detected by the detection means. a calculation means for performing a predictive calculation; a holding means for holding pre-read data pre-read from the memory based on the address calculated by the calculation means; and upon the next read access to the memory requested by the access request means; control means for sequentially comparing the read address calculated by the calculation means and the address requested by the access request means to control the transfer of the pre-read data held in the holding means to the access request means; A memory access control device comprising: