JP2000194595A - Microprocessor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a microprocessor which facilitates the use of the fast access mode of a semiconductor storage device. SOLUTION: An increment circuit 130 adds a specific value to the address signal 190 outputted from an address register 120. When the addition value reaches a value corresponding to the page size of a DRAM to which the microprocessor 100 is connected, a carry signal 180 is outputted. The carry signal is inputted to a selector 205, selected according to the indication of a control circuit 170, and outputted to the outside as a page exceeding signal 201 through a register 210. From the page exceeding signal, a memory controller connected to the microprocessor judges that the address signal has exceeded the page range of the DRAM. For sequential access within one page, the fast access mode of the DRAM is used.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor, and more particularly to a DRAM having a high-speed access mode.
The present invention relates to a microprocessor applied to a memory system including

[0002]

2. Description of the Related Art Conventionally, a microprocessor applied to a memory system including a DRAM having a high-speed access mode such as a page mode is disclosed in, for example, the following document.

[0003] ARM7TDMI Data Shee
t: Advanced RISC Machines (ARM)

As described in this document, in the conventional microprocessor, in addition to the address signal and various transfer control signals, the currently output address signal has a fixed value in the previously output address signal. A sequential access display signal (hereinafter, referred to as "SEQ signal") indicating that the signals are added and sequentially updated is output.

Usually, a microprocessor outputs an address signal for command reading, data reading, or writing. For example, when the instruction reading is executed sequentially, the output address signal is obtained by adding a fixed value to the previously output address signal. This addition is performed by an increment circuit provided in the microprocessor as shown in the above-mentioned document. On the other hand, in the case of a branch instruction or data access, the ALU (Ari
The result of the arithmetic operation in the "thmatic and Logic Unit" is output as an address signal.

FIG. 9 shows a conventional microprocessor 1. The selector 3 outputs one of the output signal of the increment circuit 5 and the output signal of the ALU 7 to the control circuit 9.
Select according to the instructions. The control circuit 9 decodes an instruction from an instruction register (hereinafter, referred to as “IR”) 15 and controls the selector 3. The signal selected by the selector 3 is output to the outside as an address signal 21 via the register 9.

A program counter (hereinafter, referred to as “PC”) 13 stores one of an output signal of the increment circuit 5 and an output signal of the ALU 7. The ALU 7 calculates one of the output signal of the PC 13 and the output signal of the general-purpose register and the displacement / immediate value, and outputs the calculation result to the selector 3 and the PC 13.

Here, a memory system including a general DRAM will be described with reference to FIG.

[0009] The microprocessor 1 supplies an address signal 21 and a memory access control signal 25 to a memory controller 31. The control circuit 9 provided in the microprocessor 1 outputs the SEQ signal 23 to the outside of the microprocessor 1,
The EQ signal 23 enables the memory controller 31 to determine whether the address signal 21 is sequential. Note that predetermined data 27 is transmitted between the microprocessor 1 and the memory controller 31.

The memory controller 31 has an address signal 41 based on an address signal 21 from the microprocessor 1 and a RAS (Row Address Strobe).
e) 45, and CAS (Column Addresses)
s Strobe) 47 is supplied to the DRAM 51. Then, these address signals 41, RAS45, C
Based on AS47, the memory controller 31 and DR
Predetermined data 45 is transmitted between the AMs 51.

If the address signal 21 is sequential,
The memory controller 31 determines that the access to the DRAM 51 can be performed in the high-speed access mode such as the page mode.

[0012]

[Problems to be Solved by the Invention] However, SEQ
It is possible to judge from the signal that the address update is performed sequentially, but whether or not the currently output address signal indicates the same page as the address signal output immediately before in the DRAM 51 is determined. That is, it has been difficult to determine whether the row address has changed.

In this regard, conventionally, the memory controller 31 includes a comparator for comparing the current address signal with the immediately preceding address signal, and detects an excess of pages in accessing the DRAM 51. However, the memory controller 31 includes the comparator. The size of the controller 31 has increased.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to display that address signals are sequentially updated and to access a semiconductor storage device such as a DRAM. It is an object of the present invention to provide a microprocessor capable of facilitating the use of the high-speed access mode in the semiconductor memory device by displaying that the number does not exceed one page.

[0015]

According to a first aspect of the present invention, there is provided an increment circuit for updating an address signal by adding a predetermined value to control a memory device. A microprocessor is provided that provides updated address signals to the memory controller. The microprocessor generates a carry signal which becomes active when a predetermined bit of the address signal updated by the increment circuit becomes active. .

With this configuration, the microprocessor can supply the carry signal to the memory controller. Then, the memory controller can determine whether the access to the memory device based on the address signal exceeds the memory area (page) set in the memory device. In the case of sequential access within one page, for example, the speed of memory access is increased by using a page mode.

According to a second aspect of the present invention, there is provided an increment circuit for updating an address signal by adding a predetermined value, and the updated address signal is transmitted to a memory controller for controlling a memory device. A supplying microprocessor is provided. In addition, the microprocessor is configured to provide a predetermined one of the address signals updated by the increment circuit.
It is characterized in that a carry signal that becomes active when all lower bits of the bit become active is generated.

According to this configuration, the microprocessor can supply the carry signal to the memory controller. Then, the memory controller can determine whether the access to the memory device based on the address signal exceeds the memory area (page) set in the memory device. In addition, it is possible to detect the page excess immediately before the access exceeds the page (for example, one clock before).

According to a third aspect of the present invention, when a predetermined bit is selected according to the page size of the memory device, the excess of the access in the memory device is detected directly from the carry signal. It becomes possible.

According to a fourth aspect of the present invention, by providing a register for storing data corresponding to the page size of the memory device and selecting a predetermined one bit based on the data, the register set in the memory device is provided. This makes it possible to flexibly respond to the size of the memory area (page) that is present, thereby improving the versatility of the microprocessor.

According to a fifth aspect of the present invention, it is preferable that the microprocessor outputs an address state signal which becomes active when the address signal is sequentially updated and the carry signal is inactive. According to this, for example, the microprocessor can determine whether or not accesses in the memory device are sequentially performed only by detecting the address state signal. It is easy to judge that the data is for one of the memory boundaries set in.

[0022]

BRIEF DESCRIPTION OF THE DRAWINGS FIG.
Preferred embodiments of a microprocessor according to the present invention will be described in detail. In the following explanation,
For components having almost the same function and configuration,
By assigning the same reference numerals, duplicate description will be omitted.

(First Embodiment) FIG. 1 shows a microprocessor 100 according to a first embodiment of the present invention.

The address register 120 holds an externally output address signal 190, and the increment circuit 130 sets a fixed value (here, "1") for the content stored in the address register 120. Is added to generate the next output address signal.

The selector 140 is provided for the increment circuit 1
Either the output signal of the ALU 30 or the output signal of the ALU 150 is selected and supplied to the address register 120.

The ALU 150 calculates the displacement / immediate value of either the output signal of the PC 160 holding the address of the instruction being executed or the output signal of the general-purpose register, and outputs a branch destination address or a data address. It is.

The control circuit 170 decodes the instruction from the IR 175 and instructs the selector 140 to select either the output signal of the increment circuit 130 or the output signal of the ALU 150. Also, the control circuit 170
The output signal of the increment circuit 130 is the address signal 1
When the signal is output as 90, an SEQ signal 200 indicating that the address signal 190 is sequentially updated is output. The SEQ signal 200 allows a device connected to the microprocessor 100, for example, a memory controller, to determine that the address signal 190 output from the microprocessor 100 has been sequentially updated.

The increment circuit 130 adds a predetermined value (here, "1") to the address signal 190 output from the address register 120. The result of this addition is stored in D
When a value corresponding to the page size of the RAM is reached, a carry signal 180 is output. The carry signal 180 is input to the selector 205, selected according to the instruction of the control circuit 170, and output to the outside as the page excess signal 201 via the register 210. This page excess signal 2
01, the memory controller connected to the microprocessor 100 transmits the address signal 190 to the DRAM
It is possible to determine that the page range has been exceeded. When instructing the selector 140 to select the output signal of the increment circuit 130, the control circuit 170 instructs the selector 205 to select the carry signal 180, and instructs the selector 140 to select the output signal of the ALU 150. Is selected, the selector 205
To select the fixed value “0”.

The operation of the microprocessor 100 having the above configuration according to the first embodiment will be described.

When the branch instruction is executed, the ALU 150
The branch destination address is calculated based on the output signal of the PC 160, the output signal of the general-purpose register, and the displacement / immediate value. The control circuit 170 controls the selector 140 and the ALU 150
Is stored in the address register 120. When the branch destination address signal is output as the address signal 190, the control circuit 17
Since 0 indicates that the address signals 190 are not sequential, the SEQ signal 200 is output as “0”.

Since the SEQ signal 200 is "0", the memory controller connected to the microprocessor 100 determines that the address signal 190 does not indicate a sequential access to the DRAM. And D
The memory controller outputs the row address to the DRAM without using the page mode in the RAM.

When the instructions are sequentially executed after the branch instruction, the control circuit 170 selects the output signal of the increment circuit 130 by the selector 140, and sequentially updates the contents of the address register 120. Further, the control circuit 170 selects the carry signal 180 corresponding to a specific bit position of the signal output from the increment circuit 130 by the selector 205 and stores it in the register 210.

As described above, the carry signal 180 is determined according to the page size of the DRAM controlled by the memory controller connected to the microprocessor 100. For example, if the microprocessor 100 is 3
When the DRAM is 2 bits wide and the DRAM is 1 byte wide and the page size is 1024 bits, the increment circuit 130
(Least Signifif) of the calculation result in
12th bit from the carry bit) is the carry signal 18
It is set to 0. During a period in which the carry signal 180 is not output, it means that a predetermined page is accessed in the DRAM.

As shown in FIG. 2, access is started from a certain address in a predetermined page (here, addresses 0100 to 01FF), and the address continuously increases in one direction, for example, as in the case of instruction fetch. When an access is made, an address at the page boundary (here, 0
Until the address exceeds 1FF, access is within one page.

Since the page size of the DRAM is specified by a power of two, whether or not the access has exceeded this boundary address can be determined by monitoring only predetermined bits corresponding to the page size. It is possible.

If a branch instruction or other data access occurs during continuous access, the control circuit 170 determines that the access is non-continuous and the SEQ signal 200
Is set to "0" to request the memory controller to start a new access from the row address.

When the output signal of the increment circuit 130 is selected by the selector 140 and is output as the address signal 190, the control circuit 170 outputs the SEQ signal 200 as "1" and sends it to the externally provided memory controller. On the other hand, access to the DRAM is performed sequentially.

When the addition signal is repeated in the increment circuit 130 and the carry signal 180 becomes "1", the carry signal 180 is output together with the address signal 190 as the page excess signal 201.

Here, the timing of the address signal 190, the SEQ signal 200, and the page excess signal 201 will be described with reference to FIG. SEQ signal 200 is "
1 ”and the page excess signal 201 is“ 0 ”during the DRA
At M, sequential access within a predetermined page is being executed.

The memory controller connected to the microprocessor 100 detects the SEQ signal 200 and the page excess signal 201, and determines whether the access in the DRAM is sequential and whether the access is within one page. Judge. If it is a sequential access and it is determined that the access has exceeded the page, a new row address is input to the DRAM. If it is determined that the access is sequential and is within one page, only the column address is input to the DRAM, and the high-speed page mode is used.

As described above, according to the microprocessor 100 according to the first embodiment of the present invention, one bit of the operation result in the increment circuit 130 is output to the outside as the page excess signal 201. D
Excessive pages during sequential access to the RAM can be easily detected. As a result, the memory controller connected to the microprocessor 100
It is possible to easily determine whether or not the high-speed page mode can be used for the access to, and the speeding up and efficiency of the memory system can be realized.

(Second Embodiment) FIG. 4 shows a microprocessor 300 according to a second embodiment of the present invention. The microprocessor 300 is different from the microprocessor 100 according to the first embodiment in that a page size designation register 321 and a carry signal selector 32 are provided.
2 has an added configuration.

By controlling the carry signal selector 322, the page size designation register 321 outputs a plurality of carry signals 330-1 output from the increment circuit 130 in accordance with the page size of the DRAM connected to the microprocessor 300. , 330-2, and 330-3. These carry signals 330-1, 330-2,
Reference numeral 330-3 corresponds to a separate bit position of the signal output from the increment circuit 130. Then, for example, when the carry signal 330-1 is selected, the carry signal 330-1 is input to the selector 205.

According to the microprocessor 300 according to the second embodiment configured as described above, the same effects as those of the microprocessor 100 according to the first embodiment can be obtained, and the following further effects can be obtained. can get.

The microprocessor 300 includes a page size designation register 321 and carries signals 330-1 and 330-3.
Since it is possible to select one of 30-2 and 330-3, it is possible to output a page excess signal 201 according to the page size of the connected DRAM. That is, the microprocessor 300 is highly versatile and can be adapted to DRAMs having various page sizes.

(Third Embodiment) FIG. 5 shows a microprocessor 400 according to a third embodiment of the present invention. The microprocessor 400 has a configuration in which the selector 205 and the register 210 are deleted and a logical operation unit 410 is added to the microprocessor 300 according to the second embodiment.

The logical operation unit 410 is provided with the carry signal selector 3
22, the carry signals 330-1, 330-
2, 330-3, and a logical operation of the SEQ signal 200 output from the control circuit 170.
An in-page signal 420 is output as an address state signal indicating whether access to the RAM is within one page.

Next, the operation of the microprocessor 400 according to the third embodiment will be specifically described with reference to FIG.

If access to the DRAM is sequential and a carry occurs in a bit position corresponding to the page size of the DRAM in the addition result in the increment circuit 130, for example, a carry signal 330-1 corresponding to the bit position Is given to the logical operation unit 410.

The logical operation unit 410 comprises a carry signal 330-1 that is active (for example, “1”) and an SEQ signal 2
00 is logically operated. Here, when the access to the DRAM is sequential, the SEQ signal 200 is active (for example, “1”), but is inactive (by logical operation with the carry signal 330-1 that is active). For example, an in-page signal 420 of “0”) is generated. On the other hand, when the in-page signal 420 is active (for example, “1”), it means that the access to the DRAM is performed sequentially within one page.

As described above, according to the microprocessor 400 according to the third embodiment, the externally provided memory controller detects only the in-page signal 420, so that in accessing the DRAM, the high-speed page It is possible to determine whether the mode can be used. Therefore, the circuit configuration of the DRAM access control is simplified.

Further, conventionally, the memory controller was provided with a comparator, and the address was compared between the current access and the immediately preceding access to the DRAM. However, the microprocessor 40 according to the third embodiment has
According to 0, it is possible to eliminate the comparator provided for the memory controller for address comparison, and the circuit scale of the memory controller is reduced. Further, it is possible to shorten the memory operation time that has been delayed by the address comparison.

(Fourth Embodiment) FIG. 7 shows a microprocessor 500 according to a fourth embodiment of the present invention. The microprocessor 500 has a configuration in which a carry look-ahead circuit 510 is added to the microprocessor 100 according to the first embodiment.

The carry look-ahead circuit 510 is constituted by an all- "1" detection circuit having a bit width corresponding to one page of a DRAM controlled by a memory controller connected to the microprocessor 500. It stores the result. In the all- "1" detection circuit provided in the carry look-ahead circuit 510, when all the bits corresponding to one page become "1" (immediately before carry), the carry look-ahead circuit 510 outputs the signal immediately before carry. The signal 520 is supplied to the selector 205.

In the microprocessor 100 according to the first embodiment, when a carry occurs in the operation result of the increment circuit 130, the selector 205 selects the carry signal 180 output from the increment circuit 130, and Microprocessor 100 via 210
Is output as a page excess signal 201 to the outside.
The page excess signal 201 indicates that an access page excess has occurred in the DRAM.

On the other hand, in the microprocessor 500 according to the fourth embodiment, the selector 205 outputs from the carry look-ahead circuit 510 one clock before a carry occurs in the operation result of the increment circuit 130. The immediately preceding carry signal 520 is selected and output to the outside of the microprocessor 500 via the register 210 as the just before page excess signal 530. This page immediately before signal 5
Numeral 30 indicates in advance that an access over page in the DRAM will occur.

As shown in FIG.
When 30 changes to active (for example, “1”),
The next addition in the increment circuit 130 causes a carry. And the microprocessor 5
The memory controller provided outside the 00 can detect that the access to the DRAM will exceed the page in the next clock by detecting the signal 530 just before the page excess.

The page excess signal 201 in the microprocessors 100 and 300 according to the first and second embodiments.
Is output immediately after the access to the DRAM exceeds one page, whereas the immediately before page excess signal 530 in the microprocessor 500 according to the fourth embodiment is a signal corresponding to the last address of one page. Output when there is access.

As described above, according to the microprocessor 500 of the fourth embodiment, it is possible to detect in advance in the DRAM that the next access after the access to one page is transferred to another page. Become. In the memory system, it is extremely important to determine the operation of the next cycle in advance in order to increase the speed. In this regard, according to the microprocessor 500 according to the fourth embodiment, only by adding a simple circuit,
Since it is possible to predict the page excess in DRAM access, it is possible to minimize the increase in cost while
Higher speed will be realized.

Although the preferred embodiments of the present invention have been described with reference to the accompanying drawings, the present invention is not limited to such examples. It is clear that a person skilled in the art can conceive various changes or modifications within the scope of the technical idea described in the claims, and those modifications naturally fall within the technical scope of the present invention. It is understood to belong.

For example, in the microprocessor 300 according to the second embodiment, the increment circuit 13
0 is three carry signals 330-1, 330-2, 330
However, the present invention is not limited to this, and it is possible to increase or decrease the carry signal according to the size of one page of the DRAM.

In the microprocessor 500 according to the fourth embodiment, the bit width of the register forming the look-ahead circuit 510 is set according to the size of one page of the DRAM. It is also possible to reduce the bit width of the register that constitutes the carry look-ahead circuit 510 in order to advance the timing of predicting an access page excess.

[0063]

As described above, according to the present invention,
In a memory system including a memory device, it is possible to easily use a high-speed access mode while minimizing an increase in circuit scale.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a microprocessor according to a first embodiment of the present invention.

FIG. 2 is a memory map showing contents of a memory access based on an address signal output from the microprocessor of FIG. 1;

FIG. 3 is a timing chart showing an operation of the microprocessor of FIG. 1;

FIG. 4 is a block diagram illustrating a configuration of a microprocessor according to a second embodiment of the present invention.

FIG. 5 is a block diagram illustrating a configuration of a microprocessor according to a third embodiment of the present invention.

FIG. 6 is a timing chart showing the operation of the microprocessor of FIG. 5;

FIG. 7 is a block diagram illustrating a configuration of a microprocessor according to a fourth embodiment of the present invention.

FIG. 8 is a timing chart showing an operation of the microprocessor of FIG. 7;

FIG. 9 is a block diagram illustrating a configuration of a conventional microprocessor.

FIG. 10 is a block diagram showing a configuration of a general memory system.

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 microprocessor 130 increment circuit 180 carry signal 190 address signal 200 SEQ signal 201 page excess signal 321 page size designation register 330-1 carry signal 322 carry signal selector 410 logical operation unit 510 carry look ahead circuit 520 carry immediately preceding signal 530 Signal before page excess

Claims (5)

[Claims] 1. A microprocessor, comprising: an increment circuit for updating an address signal by adding a predetermined value; and supplying the updated address signal to a memory controller for controlling a memory device, the microprocessor comprising: A microprocessor which generates a carry signal which becomes active when a predetermined bit of said address signal updated by a circuit becomes active. 2. A microprocessor, comprising: an increment circuit for updating an address signal by adding a predetermined value, wherein the microprocessor supplies the updated address signal to a memory controller that controls a memory device. A microprocessor which generates a carry signal which becomes active when all lower bits of a predetermined one bit of said address signal updated by a circuit become active. 3. The microprocessor according to claim 1, wherein the predetermined one bit is selected according to a page size of the memory device. 4. A method according to claim 1, wherein data corresponding to a page size of said memory device is stored, and said predetermined one is stored based on said data.
3. The microprocessor according to claim 1, further comprising a register for selecting a bit. 5. An address state signal which is updated when the address signal is sequentially updated and becomes active when the carry signal is inactive. Or the microprocessor according to 4.