JPH0487650U - - Google Patents
Info
- Publication number
- JPH0487650U JPH0487650U JP13021090U JP13021090U JPH0487650U JP H0487650 U JPH0487650 U JP H0487650U JP 13021090 U JP13021090 U JP 13021090U JP 13021090 U JP13021090 U JP 13021090U JP H0487650 U JPH0487650 U JP H0487650U
- Authority
- JP
- Japan
- Prior art keywords
- interlayer insulating
- insulating film
- wiring
- film
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 2
- 239000010408 film Substances 0.000 claims 8
- 239000011229 interlayer Substances 0.000 claims 7
- 239000002184 metal Substances 0.000 claims 2
- 239000010409 thin film Substances 0.000 claims 2
- 238000005530 etching Methods 0.000 claims 1
- 239000000463 material Substances 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Drying Of Semiconductors (AREA)
Description
第１図はこの考案の一実施例である半導体装置
の断面図、第２図ａ〜ｃは第１図の半導体装置の
製造工程を示す断面図、第３図は従来の半導体装
置の製造工程を示す断面図である。
図において、１は単結晶シリコン基板、３はポ
リシリコン配線、４は厚い酸化膜、９はアルミ配
線、１０は薄い窒化膜を示す。なお、図中、同一
符号は同一、又は相当部分を示す。
FIG. 1 is a sectional view of a semiconductor device which is an embodiment of this invention, FIGS. 2 a to c are sectional views showing the manufacturing process of the semiconductor device of FIG. 1, and FIG. 3 is a conventional manufacturing process of the semiconductor device. FIG. In the figure, 1 is a single crystal silicon substrate, 3 is a polysilicon wiring, 4 is a thick oxide film, 9 is an aluminum wiring, and 10 is a thin nitride film. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.
Claims (1)
された多結晶半導体配線と、この多結晶半導体配
線上に上記第１の層間絶縁膜よりも厚い第２の層
間絶縁膜を介して形成された金属薄膜配線と、こ
の金属薄膜配線を電気的に接続するために上記第
２の層間絶縁膜に開孔領域を形成した半導体装置
において、上記第１の層間絶縁膜が上記第２の層
間絶縁膜よりもエツチングレートの小さい材質よ
りなることを特徴とする半導体装置。 A polycrystalline semiconductor wiring formed on a semiconductor substrate via a first interlayer insulating film, and a second interlayer insulating film formed on the polycrystalline semiconductor wiring via a second interlayer insulating film thicker than the first interlayer insulating film. In the semiconductor device, an opening region is formed in the second interlayer insulating film to electrically connect the metal thin film wiring and the metal thin film wiring, wherein the first interlayer insulating film is connected to the second interlayer insulating film. A semiconductor device characterized by being made of a material with a lower etching rate than a film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13021090U JPH0487650U (en) | 1990-11-30 | 1990-11-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13021090U JPH0487650U (en) | 1990-11-30 | 1990-11-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0487650U true JPH0487650U (en) | 1992-07-30 |
Family
ID=31877568
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13021090U Pending JPH0487650U (en) | 1990-11-30 | 1990-11-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0487650U (en) |
-
1990
- 1990-11-30 JP JP13021090U patent/JPH0487650U/ja active Pending
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