JPH0487375A - Semiconductor integrated circuit device and its manufacture - Google Patents

Abstract

PURPOSE:To improve the electric properties of a memory cell so as to highly integrate it by providing a fanwise incline, at the end in the direction of gate width, for the gate electrode for information accumulation, in a device whose memory cells are constituted of field effect transistors. CONSTITUTION:A gate electrode 14 for information accumulation is provided extending onto a field insulating film 5, from a first gate insulating film 7. The electrode 14 is constituted of a conductive film 9 and an incline 13, which are formed by different processes. The incline 13 is connected in a self-alignment manner to the end of a film on the film 5. For the incline 13, in the shape of the fan unfolded toward a sub strate, the conductive film 9 and the incline 13 are constituted of, for example, polysilicon films, and for the purpose of reducing the resistance value, n-type impurities are introduced or diffused. The gate electrode for information accumulation enlarges by the amount of the incline 13, and the writing and erasing properties of a memory cell improve. The interval between the memory cells becomes smaller than the resolu tion limit of a photoresist film by the amount that the incline 13 is provided, and the interval in the gate width direction of gate electrode for information accumulation can be made small.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device and a method for manufacturing the same, and in particular, a technique that is effective when applied to a semiconductor integrated circuit device having an EPROM or EEPROM and a method for manufacturing the same. It is related to.

[Conventional technology]

EEPROM (EEPROM) whose memory cell is composed of one field effect transistor
rasableProgrammable Read
Semiconductor integrated circuit devices having a memory (Only Memory) are used. This type of semiconductor integrated circuit device is described in, for example, Japanese Unexamined Patent Publication No. 35551/1983.

The memory cells are arranged at intersections between data lines and word lines in the memory cell array. A field effect transistor constituting this memory cell is provided on an element formation surface (hereinafter referred to as the main surface) of a semiconductor substrate within a region defined by a field insulating film.

The field effect transistor mainly includes a first gate insulating film, a gate electrode for information storage (floating gate electrode), a second gate insulating film, a gate electrode for control (control gate electrode), a source region, and a train region. It is composed of each of the following.

The first gate insulating film is provided on the main surface of the semiconductor substrate.6 The information storage gate electrode is provided extending from above the first gate insulating film onto the field insulating film. It's getting worse. This information storage gate electrode is
The first layer conductive film is made of, for example, a polycrystalline silicon film. In this polycrystalline silicon film, for the purpose of reducing the resistance value,
Impurities are introduced or diffused. The second gate insulating film is made of, for example, a silicon oxide film formed by thermally oxidizing the polycrystalline silicon film that constitutes the information storage gate electrode. The control gate electrode is provided on the information storage gate electrode with the second gate insulating film interposed therebetween. This control gate electrode is composed of a second conductive film, such as a polycrystalline silicon film or a laminated film of a polycrystalline silicon film and a silicide metal film.

The drain region of this field effect transistor is connected to the data line, the control gate electrode to the word line, and the source region to the source line. The source region is formed by introducing impurities into the main surface of the semiconductor substrate by ion implantation.

The source line is formed of a semiconductor region provided on the main surface of the semiconductor substrate. This semiconductor region and the source region are formed in the same ion implantation process. Therefore, this source line and the source region are integrally constructed.

Next, a method for manufacturing the semiconductor integrated circuit device will be briefly explained.

First, a thick field insulating film is formed on the main surface of a non-active region of a semiconductor substrate.

Next, a first gate insulating film is formed on the main surface of the active region of the semiconductor substrate in the memory cell formation region.

Next, a polycrystalline silicon film constituting a first conductive film is deposited on the first gate insulating film. Impurities are introduced or diffused into this polycrystalline silicon film during or after film deposition. Thereafter, this first conductive film is patterned by anisotropic etching. The reason why this patterning step is performed by anisotropic etching is to improve the processing dimensional accuracy. Therefore, the end of the first conductive film is processed vertically, and a steep stepped portion is formed at the end of the first conductive film. In this patterning step, only the gate width direction (channel width direction) of the information storage gate electrode is patterned.

In this patterning step, the surface of the field insulating film and the main surface of the semiconductor substrate exposed from the first conductive film are over-etched. In this patterning step, the interval between the first conductive films, that is, the interval in the gate width direction of the information storage electrode, is determined by the resolution limit of the photoresist film used as an etching mask.

Next, the polycrystalline silicon film constituting the first conductive film is thermally oxidized to form a second gate insulating film composed of a silicon oxide film. Before this thermal oxidation step, cleaning is performed and the field insulating film exposed from the first conductive film is also etched. As a result, at the end of the first conductive film on the field insulating film (the end in the gate width direction of the information storage gate electrode), the field is wrapped around under the first conductive film. The insulating film will be etched.

In addition, when the second gate insulating film is formed by thermal oxidation, the deposition rate of the silicon oxide film formed on the field insulating film and the silicon oxide film formed on the polycrystalline silicon film into which impurities have been introduced are This is different from the film deposition rate. That is, the silicon oxide film formed on the polycrystalline silicon film is thicker than the silicon oxide film formed on the field insulating film. Therefore, due to the difference in film formation speed and the formation of a steep step at the end of the first conductive film, an overhanging silicon oxide film is formed at the end of the first conductive film. Put it away. Furthermore, the field insulating film is over-etched during patterning of the first conductive film, and the field insulating film is etched in a shape that wraps under the information storage electrode in the cleaning process. The degree of overhang becomes even greater.

Next, a second conductive film is deposited on the second gate insulating film. After this, apply this second conductive film.

Patterning is performed using anisotropic etching to form control gate electrodes. The reason why this patterning is performed by anisotropic etching is to improve the processing dimensional accuracy. At this time, using this control gate electrode as a mask,
The conductive film is patterned to form a gate electrode for information storage. That is, each of the information storage gate electrode and the control gate electrode is formed by so-called overlapping cutting. However, as described above, since the second gate insulating film is formed in an overhang shape at the end of the information storage electrode, the second conductive film that has entered the overhang part is overlapped with the second gate insulating film. It is difficult to remove it in the cutting process, and the second conductive film that has entered the overhang portion remains. As a result, a short circuit occurs between the control gate electrodes.
There is a problem with doing so. In order to prevent this short circuit between the control gate electrodes, the technique described in the above-mentioned publication performs isotropic etching using an etching mask of a predetermined shape after the overlapping cutting process, and the overhang is removed by side etching. The second conductive film remaining in the portion is removed.

Next, a source region and a drain region are formed on the main surface of the active region of the semiconductor substrate. This source region is formed by introducing impurities into the main surface of the semiconductor substrate, for example, by ion implantation. Furthermore, in the ion implantation step for forming the source region, a semiconductor region constituting the source line is also formed at the same time. After this, annealing is performed to activate the introduced impurities. Thereafter, the semiconductor integrated circuit device is completed by forming an interlayer insulating film, wiring, etc.

[Problem to be solved by the invention]

As a result of studying the above-described semiconductor integrated circuit device and its manufacturing method, the inventor found the following problems.

In the conventional technique, the second etching remaining in the overhang portion is removed by side etching during isotropic etching.
The conductive film is removed. For this reason, the dimensions of the information storage gate electrode and the control gate electrode are determined by the amount of side etching, resulting in a problem of lowered processing dimensional accuracy and deterioration of the electrical characteristics of the memory cell.

Further, after the step of forming the second gate insulating film,
A silicon oxide film is deposited, and then this silicon oxide film is etched by anisotropic etching by an amount corresponding to the thickness of the deposited film,
There is a method of forming sidewall spacers. In the step of forming this sidewall spacer, the field insulating film is used as an etching stopper for the deposited silicon oxide film. However, since the difference in etching rate between the deposited silicon oxide film and the silicon oxide film constituting the field insulating film is small, it is difficult to control the end point of etching. The surface of the field insulating film is overetched, and the thickness of the field insulating film becomes thinner. As a result, when ion implantation is performed using the field insulating film as a mask, leakage occurs in the thinner portions of the field insulating film. That is, since the impurity is introduced into a region other than the region into which the impurity is introduced, there is a problem in that the electrical characteristics of the semiconductor integrated circuit device deteriorate.

Further, in the overlapping cutting step, in a region where only the gate width direction of the information storage gate electrode is exposed from the patterned first conductive film, the semiconductor The main surface of the substrate is etched. A part of the formation region of the semiconductor region constituting the source line is
Since the source line is in the region exposed from the first conductive film, a step corresponding to the shape of the end of the first conductive film is formed on the main surface of the semiconductor substrate in the region where the source line is to be formed.

Since the end of the first conductive film is processed vertically,
On the main surface of the semiconductor substrate in the region where the source line is formed,
A vertical step is formed. When impurities are introduced by ion implantation with this vertical step formed, a region where no impurity is introduced is formed in the vertical step. As a result, even if an annealing step is performed after the impurity introduction step to activate and diffuse the introduced impurity, a region is formed where the impurity is not completely diffused, and the source line may be disconnected at the stepped portion. There was a problem in that the electrical characteristics of the semiconductor integrated circuit device deteriorated because a region with low impurity concentration and high resistance value was formed and the resistance value of the source line increased. Also in the case of the method of forming the first conductive film, a vertical step corresponding to the shape of the end portion of the first conductive film is formed on the main surface of the semiconductor substrate in the formation region of the semiconductor region constituting the source line in the overlapping cutting step. Similarly, there was a problem in that the electrical characteristics deteriorated due to the formation of the metal.

Furthermore, since the spacing in the gate width direction of the information storage gate electrodes is determined by the resolution limit of the photoresist film, the spacing between the information storage gate electrodes, that is, the spacing between memory cells, is determined by the resolution of the photoresist film. It cannot be made smaller than the limit. As a result, there is a problem in that it is not possible to achieve high integration of semiconductor integrated circuit devices.

An object of the present invention is to provide a technique that can improve the electrical characteristics of a memory cell in a semiconductor integrated circuit device having an EPROM or an EEPROM.

Another object of the present invention is to
It is an object of the present invention to provide a technology that can achieve high integration in a semiconductor integrated circuit device having M.

Another object of the present invention is to
An object of the present invention is to provide a technique that can improve electrical characteristics in a method of manufacturing a semiconductor integrated circuit device having M.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

(1) E in which a memory cell is composed of a field effect transistor equipped with an information storage gate electrode and a control gate electrode
In a semiconductor integrated circuit device having a PROM or an EEPROM, a semiconductor substrate comprising a conductive film electrically connected to the information storage gate electrode in a self-aligned manner at an end in the gate width direction of the information storage gate electrode. Add a widening slope.

(2) E in which a memory cell is composed of a field effect transistor equipped with an information storage gate electrode and a control gate electrode
A method for manufacturing a semiconductor integrated circuit device having a PROM or an EEPROM includes a step of forming a first gate insulating film on an element forming surface of a semiconductor substrate, and a step of forming a first gate insulating film on the first gate insulating film to be used as a gate electrode for information storage. forming a first conductive film, patterning the first conductive film by anisotropic etching to define the gate width direction of the information storage gate electrode; and forming a second conductive film. a step of depositing the second conductive film, and etching the second conductive film by anisotropic etching by an amount corresponding to the thickness of the deposited film to form a slope portion connected to the sidewall of the first conductive film in a self-aligned manner; a step of forming a second gate insulating film; and a step of forming a third gate insulating film on the second gate insulating film to be used as a control gate electrode.
a step of forming a conductive film, the third conductive film, the second conductive film;
The method includes the steps of patterning each of the conductive film and the first conductive film by anisotropic etching using the same etching mask, and forming a source region and a drain region.

(3) A source line connected to the source region of the field effect transistor is formed from a semiconductor region formed on the element formation surface of the semiconductor substrate, and the source region and the source line are formed in the same ion implantation process. Form each of the semiconductor regions.

[For production]

According to the above-mentioned means (1), the size of the information storage gate electrode is increased by the sloped portion, so that the capacity of the memory cell is increased and the writing and erasing characteristics of the memory cell are improved. This allows EPROM or EEPROM
In the semiconductor integrated circuit device having the present invention, the electrical characteristics of the memory cell can be improved.

Furthermore, the distance between the memory cells is increased by the provision of the inclined portion.
It becomes smaller than the resolution limit of the photoresist film. Therefore, if the dimension in the gate width direction of the information storage gate electrode with the inclined portion connected to both ends thereof is made almost the same as that of the conventional information storage gate electrode, the electrical characteristics of the memory cell can be maintained. , the distance between memory cells in the gate width direction of the information storage gate electrode can be reduced. Thereby, it is possible to achieve higher integration of the semiconductor integrated circuit device.

According to the above-mentioned means (2), among the regions where the surface of the field insulating film is overetched in the step of patterning the first conductive film, the region in contact with the end of the first conductive film is Covered with a second conductive film. Also,
In the step of forming the sloped portion with the second conductive film, the surface of the field insulating film in the area exposed from the sloped portion is over-etched, but since this sloped portion is formed in the shape of a sidewall, the field insulation film is The surface of the film is not over-etched into steep steps. In addition, in the cleaning step performed before forming the second gate insulating film, the surface of the field insulating film in the region exposed from the slope is removed, but the surface of the field insulating film exposed from the slope is removed. Since a steep step shape is not formed, removal of the field 1fla film in a shape that wraps around under the slope portion is reduced. Furthermore, when forming the second gate insulating film by thermal oxidation, the thickness of the silicon oxide film formed on the second conductive film and the first conductive film is greater than that of the silicon oxide film formed on the field lIr1 edge film. Although the thickness of the silicon oxide film is thicker than that of the silicon oxide film, the shape of the end of the first conductive film is relaxed by providing the slope, and the surface of the field insulating film in the region in contact with the slope is Since no steep step portion is formed, no overhang portion made of the second gate insulating film is formed at the end portion of the information storage gate electrode in the gate width direction. Since no overhang portion is formed at the end of the information storage gate electrode in the gate width direction, each of the third conductive film, the second conductive film, and the first conductive film can be etched using the same etching mask. Even if patterning is performed by anisotropic etching, the third conductive film does not remain at the end of the information storage gate electrode in the gate width direction, so short circuits between the control gate electrodes can be prevented.

By preventing short circuits between the control gate electrodes, there is no need to perform isotropic etching, so the processing dimensional accuracy of the information storage gate electrodes and the control gate electrodes will not deteriorate due to the amount of side etching. Machining dimensional accuracy improves. Thereby, in the method of manufacturing a semiconductor integrated circuit device having an EFROM or an EEPROM, the electrical characteristics of the memory cell can be improved.

Further, in the step of etching the second conductive film by an amount corresponding to the thickness of the deposited film, the silicon oxide film constituting the field insulating film is used as an etching stopper for the deposited second conductive film. Since the difference in etching rate between the deposited second conductive film, such as a polycrystalline silicon film and a silicon oxide film, is sufficiently large, it is easy to control the end point of etching, and the deposited second conductive film, for example, a polycrystalline silicon film and a silicon oxide film, can be easily controlled at the end point. Overetching of the uncoated field dielectric surface is reduced. This reduces the reduction in the thickness of the field insulating film, so when ion implantation is performed using the field insulating film as a mask, leakage will not occur in the thinner part of the field insulating film. It is possible to reduce the impurity introduction into regions other than the region into which the impurity is introduced. This allows EPR
In a method of manufacturing a semiconductor integrated circuit device having OM or EEPROM, electrical characteristics can be improved.

According to the above-mentioned means (3), the surface of the formation region of the semiconductor region constituting the source region has a stepped portion corresponding to the shape of the end portion of the information storage gate electrode, that is, the surface shape of the sloped portion. It is formed.

The surface shape of the inclined portion is in the shape of a widening base of the semiconductor substrate, that is, in the shape of a sidewall. Therefore, in the formation region of the semiconductor region constituting the source region, the shape of the step formed on the surface of the semiconductor substrate is more relaxed than vertical, so even if impurities are introduced by ion implantation, The formation of regions where impurities are not introduced in the stepped portions is reduced. Therefore, it is possible to reduce the possibility that a region where impurities do not diffuse is formed in the step portion and the source line is disconnected at the step portion, or a region with low impurity concentration and high resistance remains and the resistance value of the source line increases. be able to. Thereby, electrical characteristics can be improved in a method of manufacturing a semiconductor integrated circuit device having an EFROM or an EEPROM.

[Embodiments of the invention]

An embodiment of the present invention will be specifically described below with reference to the drawings.

In addition, in an attempt to explain the embodiments, parts having the same functions are given the same reference numerals, and repeated explanation thereof will be omitted.

The structure of a semiconductor integrated circuit device having an EPROM, which is an embodiment of the present invention, is shown in FIG. 2 (a plan view of the main part showing the memory cell array section) and FIG. This will be explained using FIG. In addition, in FIG. 2, the glabella insulating film and the like are not shown.

As shown in FIGS. 2, 1A, and 1B, the semiconductor integrated circuit device is composed of a p-type semiconductor substrate 1. As shown in FIG. This p-type semiconductor substrate 1 is made of, for example, single crystal silicon. An n-type well region 2 and an n-type well region 3 are provided on the main surface of the P-type semiconductor substrate 1, respectively. A field insulating film 5 is provided on the main surface of the non-active region of the P' type semiconductor substrate 1. This field insulating film 5 is made of, for example, a silicon oxide film.

The film thickness of this field insulating film 5 is, for example, 400 [
nm]. Below this field insulating film 6, a p° type channel stopper region 4 is provided on the main surface of the p type well region 3.

Each element is separated from each other by an isolation region formed mainly by the field insulating film 5 and the p° type channel stopper region 4, respectively.

First, the configuration of the memory cell array section is shown in FIGS. 1A and 2.
This will be explained using figures.

As shown in FIGS. 1A and 2, the memory cell of the EPR○M is composed of one field effect transistor Qm. This field effect transistor Qm is provided on the main surface of the p-type well region 3 within a region defined by the field insulating film 5.

The field effect transistor Qm mainly includes a first gate insulating film 7. Consisting of an information storage gate electrode 14, a second gate insulating film 15, a control gate electrode 19A, a low concentration source region and a drain region composed of an n″ type semiconductor region 20, and an n° type semiconductor region 35. It is composed of a highly doped source region and a drain region.

The first gate insulating film 7 is provided on the main surface of the p-type well region 3. This first gate insulating film 7 is
For example, it is made of a silicon oxide film. The thickness of the first gate insulating film 7 is, for example, 15 to 20 nm.
That's about it.

The information storage gate electrode 14 is provided extending from above the first gate insulating film 7 to above the field insulating film 5. This information storage gate electrode 14 is formed by forming a first conductive film 9 and a slope portion 13 in different steps.
It consists of The inclined portion 13 is connected to the end of the first conductive film 9 on the field insulating film 5 in a self-aligned manner. This inclined portion 13 is formed in a so-called sidewall spacer shape, and has a shape that widens toward the p-type semiconductor substrate 1 side. Each of the first conductive film 9 and the inclined portion 13 is made of, for example, a polycrystalline silicon film. The thickness of the first conductive film 9 is, for example, about 200 [nm]. An n-type impurity such as (P) is introduced or diffused into the polycrystalline silicon film constituting the first conductive film 9 and the inclined portion 13 for the purpose of reducing the resistance value. Moreover, this first conductive film 9 and the inclined portion 1
3, for example, doped polycrystalline silicon (Doped Po
1y5ilicon: one in which phosphorus (P) is implanted during film deposition). The inclined portion 13 is formed, for example, by depositing a polycrystalline silicon film by the CVD method and then performing anisotropic etching by an amount corresponding to the thickness of the deposited film.

The second gate insulating film 15 is provided on the information storage gate electrode 14. The second gate insulating film 15 is composed of a laminated film in which, for example, a silicon oxide film, a silicon nitride film, and a silicon oxide film are sequentially laminated. The thickness of the lower silicon oxide film is, for example, about 5 [nm]. The thickness of the silicon nitride film is, for example, 10 to 20
It is about [nm]. The thickness of the upper silicon oxide film is:
For example, it is about 2 to 5 [nm].

The control gate electrode 19A is provided on the information storage gate electrode 13 with the second gate insulating film 15 interposed therebetween, and is configured integrally with the word line WL. This control gate electrode 19A is made of, for example, a polycrystalline silicon film. The thickness of this polycrystalline silicon film is, for example, about 200 to 300 [nm]. Further, the control gate electrode 19A may be composed of a laminated film (polycide film) of, for example, a polycrystalline silicon film and a high melting point metal silicide film, such as a tungsten silicide film. in this case.

The thickness of the polycrystalline silicon film is about 100 [nm], and the thickness of the tungsten silicide film is about 150 [nm].

The information storage gate electrode 14 and the control gate electrode 1
An insulating film 30 is provided around 9A.

This #fA edge film 30 is made of, for example, a silicon oxide film. The thickness of this silicon oxide film is, for example, 2° [nm
] It is about .

Furthermore, sidewall spacers 32 are provided on the sidewalls of the information storage gate electrode 14 and the control gate electrode 19A. This side wall spacer 32 is
For example, it is made of a silicon oxide film.

n- constituting the low concentration source region and drain region
The type semiconductor region 20 is provided on the main surface of the p-type well region 3 in a self-aligned manner with respect to the control gate electrode 19A.

The n-type semiconductor region 35 constituting the high concentration source region and drain region is provided in the main surface of the p-type well region 3 in a self-aligned manner with respect to the sidewall spacer 32. This n.

One side of the type semiconductor region 35 is connected to a source line 35 (SL). This source line 35 (SL) is connected to the n° type semiconductor region 35 that constitutes the source region and the drain region.
It is integrated with. Further, a data line 41 (DL) is connected to the other side of the n° type semiconductor region 35 through a connection hole 39 in the glabella insulating film 38.

This data line 41 is made of, for example, an aluminum alloy film.

The interlayer insulating film 38 is made of, for example, a silicon oxide film and a BPS
G (Boron Pbospho 5ilicate
It is composed of a laminated film including a glass film. The thickness of this interlayer insulating film 38 is, for example, 400 to 600 [
It is about nml.

A final passivation film 45 is provided above the interlayer insulating film 38 and the data line 41. The final passivation film 45 is, for example, P S
G (Phosho 5ilicate Glass)
It is composed of a two-layer film, or a PSG film and a silicon nitride film deposited by a plasma CVD method.

Next, the configuration of the peripheral circuit section will be explained. As shown in FIG. 1B, this peripheral circuit section includes an n-channel MISFETQn
(hereinafter referred to as nM OP Q n) and a p-channel MISFET QP (hereinafter referred to as p MOS Q p). In other words, the peripheral circuit section is
It has a so-called CMO3 configuration.

The nMO3Qn is provided on the main surface of the p-type well region 3 within a region defined by the field insulating film 5. This nMO8Qn mainly consists of a gate insulating film 17, a gate electrode 19B, an n-type semiconductor region 25 forming a low concentration source region and a drain region, and an n° type semiconductor region forming a high concentration source region and a drain region. The area 35 is composed of each area 35.

The gate insulating film 17 is provided on the main surface of the p-type well region 3. This gate insulating film 17 is made of, for example, a silicon oxide film. The thickness of this gate insulating film 17 is approximately 15 to 20 [nml] when nMO3Qn operates at a low voltage of 5 [V] or less, and 20 to 20 [nml] when it operates at a high voltage of 10 [V] or more. 25 [n++
The film thickness is set to approximately +].

The gate electrode 19B is connected to the gate IN! ! Membrane 17
is placed above. This gate electrode 19B is made of a second layer conductive film, that is, a polycrystalline silicon film, similar to the control gate electrode 19A. This gate electrode 19
The insulating film 30 is provided around B. Further, the side wall spacer 32 is provided on the side wall portion of this gate electrode 19B.

n constituting the low concentration source region and drain region
The - type semiconductor region 25 is provided in the main surface of the p-type well region 3 in a self-aligned manner with respect to the gate electrode 19B.

n constituting the high concentration source region and drain region
The °-type semiconductor region 35 is provided in the main surface of the p-type well region 3 in a self-aligned manner with respect to the sidewall spacer 32.

In this way, by configuring the source region and the train region of this nMOS Qn with the n-type semiconductor region 25 and the n-type semiconductor region 35, this nMO8Qn has an LDD (Lightly D aped D
rain) structure.

A glabella insulating film 38 is provided on one side of the n° type semiconductor region 35.
One end of the wiring 41 is connected through a connection hole 39 provided in the. This wiring 41 is connected to the data line 41 (D
It has the same configuration as L).

The pMOS Q p is provided on the main surface of the n-type well region 2 in a region defined by the feed insulating film 5 . This pM○SQp mainly consists of the gate insulating film 17 and the gate electrode! 9C1 p-type semiconductor region 2 constituting a low concentration source region and drain region
6. n° constituting the highly concentrated source and drain regions
each of the type semiconductor regions 36.

The gate insulating film 17 is provided on the main surface of the n-type well region 2. This gate insulating film 17 is made of, for example, a silicon oxide film. The film thickness of this gate insulating film 17 is 15 when pMO8Qp operates at low voltage.
~20 [nml], 2 when operating at high voltage
The film thickness is set to about 0 to 25 [nml].

The gate electrode 19C is provided on the gate insulating film 17. This gate electrode 19C is made of a second layer conductive film, that is, a polycrystalline silicon film, similar to the control gate electrode 19A. The insulating film 30 is provided around the gate electrode 19C. Furthermore, the side wall spacer 32 is provided on the side wall portion of this gate electrode 19C.

P constituting the low concentration source region and drain region
The - type semiconductor region 26 is provided on the main surface of the n-type well region 2 in a self-aligned manner with respect to the gate electrode 19C.

P constituting the high concentration source region and drain region
The '-type semiconductor region 36 is provided on the main surface of the n-type well region 2 in a self-aligned manner with respect to the sidewall spacer 32.

In this way, by configuring the source region and drain region of this pMOS Qp with the p~ type semiconductor region 26 and the p'' type semiconductor region 36, this pMO8Qp has an LDD structure.

An interlayer insulating film 37 is formed on one side of the p-type semiconductor region 36.
The other end of the wiring 41 is connected through a connection hole 38 provided in the.

As can be seen from the above description, according to the configuration of this embodiment, the size of the information storage gate electrode 14 increases by the amount of the sloped portion 13, so the capacity of the memory cell increases, and the memory cell can be programmed. , the erasing characteristics are improved. As a result, in a semiconductor integrated circuit device having an EPROM,
Electrical characteristics of memory cells can be improved.

Furthermore, the distance between memory cells becomes smaller than the resolution limit of the photoresist film due to the provision of the inclined portions 13.

Therefore, the dimension in the gate width direction of the electrode 14 to the information storage gate 1 connected to both ends of the inclined portion 13 is as follows.
If the information storage gate electrodes 14 are made almost the same as the conventional information storage gate electrodes, the distance between the memory cells in the gate width direction of the information storage gate electrodes 14 can be reduced while maintaining the electrical characteristics of the memory cells. This allows the EPROM
In the semiconductor integrated circuit device having the present invention, high integration can be achieved.

In detail, the method for manufacturing the semiconductor integrated circuit device is shown in FIGS. 3 to 6 (principal plan views showing the area shown in FIG. 2 for each manufacturing process), FIGS. 7A to 14A, and 7B. This will be explained using FIGS. 14B to 14B (cross-sectional views of main parts showing the regions shown in FIGS. 1A and 1B for each manufacturing process). In addition,
In FIGS. 3 to 6, interlayer insulating films and the like are not shown.

First, an n-type well region 2 and an n-type well region 3 are formed on the main surface of a p-type semiconductor substrate 1, respectively.

After that, as shown in FIG.
A p° type channel stopper region (4) and a field insulating film 5 (not shown) are formed on the main surface of the non-active region. The field insulating film 5 is.

For example, it is formed with a film thickness of about 400 [nm].

Next, the main surfaces of the active regions of the n-type well region 2 and n-type well region 3 are thermally oxidized to form the first gate insulating film 7.
form. This first gate insulating film 7 is, for example, 1
It is formed with a film thickness of about 5 to 25 [nm].

Next, a first conductive film 9, for example a polycrystalline silicon film, is deposited on the first gate insulating film 7. This polycrystalline silicon is formed to have a thickness of, for example, about 200 [nm]. Furthermore, after film deposition, phosphorus (P), which is an n-type impurity, is added to this polycrystalline silicon film by phosphorus (P) treatment or ion implantation.
to spread or introduce. In this step of introducing phosphorus (P), for example, the impurity concentration is I
Phosphorus (P) of about ms/cm21 is introduced by ion implantation with an acceleration energy of about 30 [KeV]. After diffusing or introducing this phosphorus (P), annealing is performed at a temperature of about 900 [°C] for about 30 minutes, and the first
The resistance value of the conductive film 9 is reduced. Note that the first conductive film 9 may be formed of doped polycrystalline silicon.

Next, a silicon oxide film 11 is formed. This silicon oxide film 11
is deposited by, for example, a CVD method or formed by a thermal oxidation method. This silicon oxide film 11 is, for example, 10 [n
It is formed with a film thickness of about m1.

Next, as shown in FIGS. 4, 7A, and 7B, the silicon oxide film 11. Each of the first conductive films 9 is sequentially patterned using photolithography technology. This patterning is performed by anisotropic etching (dry etching). By performing this patterning by anisotropic etching, the end portion of the '1st conductive film 9 is processed vertically.

In this patterning process, the information storage gate electrode (
14) so as to define only the gate width direction.
The conductive film 9 is patterned. Note that when patterning this first conductive film 9, each of the first gate insulating film 7 and field insulating film 5 is used as an etching stopper.

Next, the second conductive film 13, for example, a polycrystalline silicon film, is deposited by CVD.
Deposited by method. This polycrystalline silicon film is formed to have a thickness of, for example, 200 to 300 [nm]. Thereafter, this polycrystalline silicon film is subjected to a resistance reduction treatment similarly to the polycrystalline silicon film constituting the first conductive film 9.

Thereafter, the second conductive film 13 is anisotropically etched by an amount corresponding to the thickness of the deposited film, for example, by RIE (React
Etching using reactive ion etching. Through this etching step, as shown in FIGS. 5, 8A and 8B, the second conductive film 13 is self-aligned with the end of the first conductive film 9. The inclined portion 13 is connected to the semiconductor substrate 1 side in a spread-out shape (sidewall spacer shape). In the step of patterning the first conductive film 9, if the surfaces of the field insulating film 5 and the first gate insulating film 7 are over-etched in the region in contact with the end of the first conductive film 9. However, since it is covered by this inclined portion 13, an overhang structure is not formed. Note that in this etching process, the field insulating film 5
, the gate vlA edge film 7 and the silicon oxide film 11 are each used as an etching stopper. This second conductive film 13
In the step of etching the second conductive film 13, the silicon oxide film constituting the field insulating film 5 is used as an etching stopper for the second conductive film 13. Since the difference in etching rate between the polycrystalline silicon film and the silicon oxide film constituting the second conductive film 13 is sufficiently large, the end point of etching can be easily controlled. Over-etching of the surface of the field insulating film 5 that is not covered with the film 13 is reduced. As a result, the decrease in the film thickness of the field insulating film 5 is reduced, so that the field insulating film 5
When ion implantation is performed using the field insulating film 5 as a mask, it is possible to reduce the occurrence of leakage in the thinner part of the field insulating film 5, and to prevent impurities from being introduced into regions other than the region where the impurities are to be introduced. can be reduced. As a result, electrical characteristics can be improved in a method of manufacturing a semiconductor integrated circuit device having an EPROM.

In the step of forming the sloped portion 13, even if the surfaces of the field insulating film 5 and the first gate insulating film 7 are over-etched, the sloped portion 13 is formed in a sidewall shape. No steep steps are formed on the surfaces of the field insulating film 5 and the first gate insulating film 7 in the region in contact with the inclined portion 13.

Next, the silicon oxide film 11 is removed. In this removal step, the surfaces of the field insulating film 5 and the first gate insulating film 7 exposed from the first conductive film 9 and the inclined portion 13 are also etched. However, since no steep steps are formed on the surfaces of the field insulating film 5 and the first gate insulating film 7 in the region in contact with the sloped part 13, this removal process removes the surrounding area under the sloped part 13. Etching of the surfaces of the field insulating film 5 and the first gate insulating film 7 into the shape of the etching is reduced. In other words, formation of steep step portions on the surfaces of the field insulating film 5 and the first gate insulating film 7 in the region in contact with the slope portion 13 is reduced.

Next, as shown in FIGS. 9A and 9B, a second gate insulating film 15 is formed on the entire main surface of the p'' type semiconductor substrate. It is formed by sequentially stacking a silicon oxide film, a silicon nitride film, and a silicon oxide film.The lower silicon oxide film is formed to a thickness of 5 [nm] by, for example, a thermal oxidation method in a low oxygen concentration atmosphere.
] Formed with a film thickness of approximately . The silicon nitride film is, for example,
It is formed with a film thickness of about 10 to 20 [nm1] by the CVD method. The upper silicon oxide film is made of, for example, Veto2.
The film is formed to a thickness of about 2 to 5 [nl11] by oxidation in an atmosphere. This second gate insulating film 15 is formed in accordance with the surface shape of the underlying layer. The end of the first conductive film 9 is patterned by anisotropic etching, so it is processed vertically.
is formed. Further, in the region in contact with the end of the slope portion 13, no steep step is formed on the surfaces of the field insulating film 5 and the first gate insulating film 7 due to etching.

Therefore, there is no steep stepped portion in the base upon which the second gate insulating film 15 is formed.

Next, nMO8Qn and pMOs that constitute the peripheral circuit section
In the formation region of Qp, the second gate insulating film 15
, the first conductive film 9, the inclined portion 13, and the first gate insulating film 7 are removed, and the n-type well region 2 and the n-type well region 3 are removed as shown in FIGS. 10A and 10B. expose the main surface of the Thereafter, the main surfaces of the active regions of the n-type well region 2 and n-type well region 3 are thermally oxidized to form a gate insulating film 17. This gate insulating film 17 is, for example,
It is formed with a film thickness of about 15 to 20 [nm]. In addition,
The thickness of this gate insulating film 17 may be changed depending on the respective operating voltages of the nMOS Qn and pMO3Qp. For example, the gate insulating film 17 of a MOS that operates at a high voltage is formed to have a thickness of about 20 to 25 nm, and the gate insulating film 17 of a MOS that operates at a low voltage is formed to a thickness of 12.5 to 15 nm. ] Form to a degree.

Next, as shown in FIGS. 11A and 11B, the p-
A third conductive film 19 is formed over the entire main surface of the semiconductor substrate 1 . This third conductive film 19 is formed of, for example, a polycrystalline silicon film and has a thickness of about 200 to 300 [nm]. Also, this third conductive film! For example, 9 may be formed of a laminated film (polycide film) of a polycrystalline silicon film and a refractory metal silicide film, such as a tungsten silicide film. In this case, a polycrystalline silicon film is formed to a thickness of about 100 nm, and a tungsten silicide film is formed to a thickness of about 150 nm.
[Form to have a film thickness of about nm1.

Next, as shown in FIGS. 6, 12A, and 12B, the information storage gate electrode 14 and the control gate electrode 19A of the field effect transistor QI+1 are formed. Each of the information storage gate electrode 14 and the control gate electrode 19A is located in the memory cell formation region.
The third conductive film 19, the second gate insulating film 15. The inclined portion 13 and the first conductive film 9 are each formed by patterning by anisotropic etching using the same etching mask. In this patterning step, the control gate electrode 19A is formed, and the first conductive film 9
Each of the slope portions 13 and 13 is patterned by so-called overlapping cutting, in which patterning is performed so as to define the gate length direction of the information storage gate electrode 14. In this overlapping cutting step, since no overhang portion constituted by the second gate insulating film 15 is formed at the end of the information storage gate electrode 14 in the gate width direction, the third conductive film 19. Even if each of the inclined portion 13 and the first conductive film 9 is patterned by anisotropic etching using the same etching mask, the edge portion of the information storage gate electrode 14 in the gate width direction is Since the conductive film 19 of No. 3 does not remain, it is possible to prevent the shows 1 to 1 between the control gate electrodes 19A.

Since a short circuit between the control gate electrodes 19A is prevented, there is no need to perform one isotropic etching to remove the remaining third conductive film 19. There is no decrease in the processing precision of the gate electrode 19A, and the processing precision of the information storage gate electrode 14 and the control gate electrode 19A is improved.

Thereby, in the method of manufacturing a semiconductor integrated circuit device having an EERPOM, the electrical characteristics of the memory cell can be improved.

Furthermore, in the region where the source line (35) SL is formed,
The surface of the n-type well region 3 has the shape of the end of the information storage gate electrode 14, that is, the inclined portion! A step portion having a shape corresponding to the surface shape of No. 3 is formed. Since the surface shape of the inclined portion 13 is more relaxed than the vertical one, a step that is more relaxed than the vertical one is formed on the surface of the n-type well region 3 in the region where the source line SL is formed.

Next, an n-type semiconductor region 20 that constitutes a low concentration source region and a drain region of the field effect transistor Qm is formed. This n° type semiconductor region 20 is formed in the memory cell formation region by mainly introducing n type impurities into the main surface portion of the P type well region 3 using the control gate electrode 19A as a mask. In the step of introducing n-type impurities into, for example, the impurity concentration is 2 x 10
” Arsenic (As) in an amount of about 2 [atoms/am2] is introduced by an ion implantation method with an acceleration energy of about 60[eV].

Next, n M OS Q n and p that constitute the peripheral circuit
In the MO8Qp formation region, the third conductive film 19
is patterned to form a gate electrode 19B of nMOSQn.
and pMO8Qp(1) gate electrode 19G are formed.

Next, an n-type semiconductor region 25 that constitutes a low concentration source region and a drain region of nMOsQn is formed. This n-type semiconductor region 25 is formed in the formation region of nMOsQn by mainly introducing n-type impurities into the main surface portion of the n-type well region 3 using the control gate electrode 19B as a mask.

In the step of introducing this n-type impurity, for example, phosphorus (P) with an impurity concentration of about 10'' [atoms/cm2] is used.
) is introduced by ion implantation with an acceleration energy of about 30 [KeV]. Thereafter, as shown in FIGS. 13A and 13B, p-type semiconductor regions 26 constituting low concentration source and drain regions of pMO8Qp are formed. This p-type semiconductor region 26 is formed in the formation region of pMO3Qp by mainly introducing n-type impurities into the main surface portion of the n-type well region 2 using the gate electrode 19C as a mask.

In the step of introducing this n-type impurity, for example, boron (BF, ) with an impurity concentration of about 5 X], Q12 [atoms/cm'' is introduced by an ion implantation method with an acceleration energy of about 50 [XaV]. do.

Next, an insulating film 30 is formed around the information storage gate electrode 14, the control gate electrode 19A, and the gate electrodes 19B and 19C by thermal oxidation. This insulating film 30 has a thickness of, for example, 20 [n! It is formed with a film thickness of about n1.

Next, a silicon oxide film, for example, is deposited over the entire main surface of the p-type semiconductor substrate 1 to a thickness of about 300 to 4.00 [nm]. Thereafter, the silicon oxide film is etched by anisotropic etching, such as reactive ion etching, to form sidewall spacers 32 by an amount corresponding to the thickness of the deposited film.

Next, a silicon oxide film 33 is formed by thermal oxidation or CVD. This silicon oxide film 33 is formed to have a thickness of, for example, about 1° [nml].

Next, field effect transistors Qm and nM.

A Go-type semiconductor region 35 is formed which constitutes a source region and a drain region with a high concentration of SQn, and each of the source and IX5L. This n° type semiconductor region 35 mainly consists of the silicon oxide film 30, the control gate electrode 19A, and the gate electrode 19B in the memory cell and nMOsQn formation regions.
and sidewall spacers 32 are used as masks to form n-type impurities into the main surface of the P-type well region 3.

In the step of introducing this n-type impurity, for example, arsenic (A
s) is introduced by ion implantation with an acceleration energy of about 40 [KeV].

Since the step formed on the surface of the n-type well region 3 in the region where the source line SL is formed is less vertical, the step difference formed on the surface of the n-type semiconductor region 35 in the region where the source line SL is formed is less vertical.
Even if the step is formed, the formation of a region where impurities are not introduced in the stepped portion is reduced. Therefore, it is possible to reduce the possibility that a region where impurities do not diffuse is formed and the source line SL is disconnected at this stepped portion, or a region with a low impurity concentration and a high resistance value remains and the resistance value of the source line SL increases. I can do it. As a result, electrical characteristics can be improved in a method of manufacturing a semiconductor integrated circuit device having an EFROM.

Next, as shown in Figures 14A and 1.4B, p
A p° type semiconductor region 36 that constitutes a highly doped source region and a drain region of the MOS Qp is formed. This p°-type semiconductor region 36 is formed by doping n-type impurities into the main surface of the n-type well region 2 using the insulating film 30, gate electrode 19C, and sidewall spacer 32 as a mask in the pMO3Qp formation region. Formed by introducing. In the step of introducing this n-type impurity, for example, the impurity concentration is 2 × 10 '' [atoms/c
Boron (BF2) with an amount of approximately 40 [KeV] is introduced by ion implantation with an acceleration energy of approximately 40 [KeV].

Next, for example, C is applied to the entire main surface of the p-type semiconductor substrate 1.
A silicon oxide film and a BPSG film are sequentially laminated by a VD method to form an interlayer #fA edge film 38. This glabellar insulating film 38 is 1
For example, it is formed to have a thickness of about 400 to 600 [nm].

Next, a connection hole 39 is formed in the interlayer insulating film 38.

Thereafter, heat treatment is performed to reflow the BPSG film constituting the interlayer insulating film 38 and planarize the surface of the interlayer insulating film 38. This heat treatment is performed, for example, at a temperature of 900 to 950 [''C].

Next, an aluminum film is deposited, for example, by sputtering. Thereafter, this aluminum film is patterned by photolithography to form wiring 41.

Next, a final passivation film 45 is formed over the entire main surface of the p-type semiconductor substrate 1 to a thickness of, for example, about 1.2 [μm]. This fiber passivation film 4
5 is a single layer film of, for example, a PSG film.

Alternatively, a two-layer film is formed by sequentially stacking a PSG film and a silicon nitride film deposited by plasma CVD.

By forming this final passivation film 45, the semiconductor integrated circuit device of this embodiment shown in FIGS. 2, 1A, and 1B is completed.

As can be seen from the above description, according to the manufacturing method of this embodiment, an overhang portion composed of the second gate insulating film 15 is formed at the end of the information storage gate electrode 14 in the gate width direction. Not done. Since the overhang portion is not formed, the third conductive film 19 and the inclined portion 1
Even if each of the third conductive film 3 and the first conductive film 9 is patterned by anisotropic etching using the same etching mask, the third conductive film is not formed at the end of the information storage gate electrode 14 in the gate width direction. 19 does not remain, so a short circuit between the control gate electrodes 14 can be prevented. By preventing a short circuit between the control gate electrodes 14, there is no need to perform isotropic etching. The dimensional accuracy of the information storage gate electrode 14 does not deteriorate due to the amount of etching, and the dimensional accuracy of the information storage gate electrode 14 is improved. Thereby, in the method of manufacturing a semiconductor integrated circuit device having an EPROM, the electrical characteristics of the memory cell can be improved.

Further, in the step of forming the inclined portion 13, the silicon oxide film constituting the field insulating film 5 is used as an etching stopper for the deposited second conductive film 13.

Since the difference in etching rate between the deposited second conductive film 13, for example, a polycrystalline silicon film and a silicon oxide film, is sufficiently large, it is easy to control the end point of etching, and the first conductive film 9 and the sloped portion are easily controlled. Over-etching of the surface of the field isolation film 5 that is not covered with the film 13 is reduced. This reduces the decrease in the film thickness of the field insulating film 5, so when ion implantation is performed using the field insulating film 5 as a mask, this field #! It is possible to reduce the occurrence of leakage in the thinner portion of the Am film 5, and to reduce the introduction of impurities into regions other than the region into which impurities are introduced. As a result, electrical characteristics can be improved in a method of manufacturing a semiconductor integrated circuit device having an EPROM.

Furthermore, a step corresponding to the surface shape of the slope portion 13 is formed on the surface of the P-type well region 3 in the region where the source line 35 (SL) is formed. The inclined portion 13 has a shape that expands toward the p-type semiconductor substrate 1 side, that is, a sidewall shape. Therefore, in the formation region of the source line 35 (SL), the shape of the step formed on the surface of the p-type well region 3 is more relaxed than vertical, so even if impurities are introduced by ion implantation, The formation of a region in which impurities are not introduced into the stepped portion is reduced. Therefore,
A region where impurities do not diffuse is formed in this stepped portion, and the source line 35 (SL) may be disconnected at the stepped portion, or a region with low impurity concentration and high resistance may remain.
It is possible to reduce the increase in the resistance value of the resistor. As a result, electrical characteristics can be improved in a method of manufacturing a semiconductor integrated circuit device having an EPROM.

Although the present invention has been specifically explained above based on examples, it goes without saying that the present invention is not limited to the above-mentioned examples and can be modified in various ways without departing from the gist thereof.

For example, although this embodiment shows a semiconductor integrated circuit device having an EPROM, the present invention can also be applied to a semiconductor integrated circuit device having an EEPROM.

〔Effect of the invention〕

To briefly explain the effects obtained by the typical inventions disclosed in this application, it is possible to improve the electrical characteristics of a memory cell in a semiconductor integrated circuit device having an EFROM or an EEPROM as described below. can.

Furthermore, high integration can be achieved in a semiconductor integrated circuit device having the EPROM or EEPROM.

Furthermore, in the method for manufacturing a semiconductor integrated circuit device having the EFROM or EEPROM, electrical characteristics can be improved.

[Brief explanation of the drawing]

FIG. 1A and FIG. 1B show an ERPOM of an embodiment of the present invention.
FIG. 2 is a plan view of essential parts of the memory cell array section of the semiconductor integrated circuit device, and FIGS. 3 to 6 are: 7A to 14A and 7B to 14B are plan views showing the regions shown in FIG. 2 for each manufacturing process. FIG. In the figure, 1... P-type semiconductor substrate, 2... D-type well region, 3... P-type well region, 4... n'-type channel stopper region, 5... field insulating film, 7...・First gate insulating film, 9... First conductive film, 13... Slanted portion, 15... Second gate insulating film, 17... Gate IIIA edge film, 19A... For control Gate electrode, 19B
, 19C...gate electrode, 20.25...n-type semiconductor region, 26...p-type semiconductor region, 30...
Insulating film, 33...Silicon oxide film 532...Side wall spacer, 35...n° type semiconductor region, 36...
・p° type semiconductor region, 38... interlayer insulating film, 39...
- Connection hole, 41... Wiring, 45... Final passivation film. Figure 2

Claims (1)

[Claims] 1. An EP in which a memory cell is constituted by a field effect transistor equipped with an information storage gate electrode and a control gate electrode.
1. A semiconductor integrated circuit device having a ROM or an EEPROM, wherein the information storage gate electrode has a widening slope at an end in the gate width direction. 2. The information storage gate electrode has a substantially vertical portion and a widening inclined portion formed of a conductive film that is self-aligned and electrically connected to the substantially vertical portion. 2. A semiconductor integrated circuit device according to claim 1. 3. In a method of manufacturing a semiconductor integrated circuit device having a field effect transistor with a gate electrode, forming a first gate insulating film on the element formation surface of the semiconductor substrate;
forming a first conductive film to be used as a first gate electrode on the first gate insulating film; patterning the first conductive film by anisotropic etching; a step of defining the gate width direction of the electrode; a step of depositing a second conductive film; and etching the second conductive film by anisotropic etching to a thickness corresponding to the deposited film thickness; a step of forming a slope portion connected to the sidewall of the conductive film in a self-aligned manner; a step of forming a second gate insulating film; and a step of forming a second gate insulating film to be used as a second gate electrode on the second gate insulating film. forming a third conductive film; patterning each of the third conductive film, the second conductive film, and the first conductive film by anisotropic etching; and forming a source region and a drain region. 1. A method of manufacturing a semiconductor integrated circuit device, comprising a step of forming a semiconductor integrated circuit device. 4. An EPROM or EEPROM in which a memory cell is constituted by a field effect transistor in which the first gate electrode functions for information storage and the second gate electrode functions for control.
4. The method of manufacturing a semiconductor integrated circuit device according to claim 3, wherein: 5. A source line connected to the source region of the field effect transistor is formed of a semiconductor region formed on the element formation surface of the semiconductor substrate, and in the same ion implantation step,
5. The method of manufacturing a semiconductor integrated circuit device according to claim 3, wherein each of the semiconductor regions constituting the source region and the source line is formed.