JPH0487076A - Clock generating device for magnetic disk device - Google Patents

Abstract

PURPOSE:To obtain an NRZ data signal having a frequency about double as high as the conventional one by using the rise and fall edges of a reference clock signal. CONSTITUTION:A rise latch circuit 3 stores the output signal of a rise state circuit 1 at the rise edge of a clock signal received from a lower rank circuit. Meanwhile a fall latch circuit 4 stores the output signal of a fall state circuit 2 at the fall edge of the clock signal respectively. Then a rise clock circuit 5 and a fall clock circuit 6 input the outputs of the circuits 2 and 4 and output '1' or '0' according to the clock signals respectively. Furthermore a rise delay circuit 7 and a fall delay circuit 8 delay the outputs of both circuits 5 and 6. Then the outputs of these circuits 5 - 8 are inputted respectively and a clock output circuit 9 outputs a clock signal '1' when either one of those outputs is equal to '1'. Thus it is possible to obtain an output clock signal by applying the 2/3-division to an input clock signal.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a magnetic disk device, and more particularly to a clock generation circuit for a magnetic disk device that converts the frequency of a clock signal in the magnetic disk device.

[Conventional technology]

Conventionally, in a clock generation circuit of a magnetic disk device, a reference clock signal transferred from a lower-order device is frequency-divided by an integer to generate a lock signal as necessary.

For example, during 1-7 code conversion, the reference clock sent from the lower device has a frequency three times that of the clock signal for the NRZ data signal, and by dividing this reference clock signal in half, , 1-7 code, and frequency-divides this reference clock signal by one-third to generate a clock signal for the NRZ data signal.

[Problem to be solved by the invention]

In conventional clock generation circuits, the clock signal for the NRZ data signal is created by dividing the frequency of the reference clock signal, which is three times the frequency of the reference clock signal, so the operating limits of the elements used in the frequency conversion circuit in the clock generation circuit There was a problem in that only NRZ data signals up to one-third of the frequency could be obtained.

[Purpose of the invention]

The present invention aims to solve these problems of the prior art.

That is, an object of the present invention is to provide a clock generation circuit for a magnetic disk device that can obtain an NRZ data signal of a higher frequency than a conventional clock generation circuit while using elements equivalent to conventional ones. There is.

[Means to solve the problem]

The present invention has a rise state circuit and a false state circuit that output a predetermined signal in response to a hold signal sent from a higher-order circuit, and also has a rise-state circuit that outputs a predetermined signal in response to a hold signal sent from a lower-order circuit. a rise latch circuit that stores the output signal of
It is equipped with a fall latch circuit that stores the output signal of the false state circuit at the falling edge of the clock signal, and inputs the output of the rise state circuit or the false state circuit separately and outputs "1" or "0" according to the clock signal. It is equipped with a rise clock circuit and a fall clock circuit that output The configuration is such that the outputs of the delay circuit and the fall delay circuit are respectively inputted, and a clock output circuit is provided which outputs a clock signal "1" when the output of any one of these circuits is rl. This aims to achieve the above-mentioned purpose.

[For production]

When the hold signal is (0), the fall signal is (0,0)
, (0,1), (1,0) to the rise state signal according to (0,1), (1,0).

(0,0) and when the hold signal is (1), the fall signals (0,0), (0°1), (1
, O) to the rise state signal (0, O),'
(0,1), (1,O), and when the hold signal is (0), the Rician signal (0°0), (0,1)
, (1, O) to the false-state signal according to (0,1
), (1, O), (0°0), and when the hold signal is (1), the rise signal (0, O), (
0,1), (1°0) to the false signal (0,0).

(0, 1), (1, O), stores a rise state signal at the rising edge of the clock signal to generate a rise signal, and stores a false state signal at the falling edge of the clock signal to generate a fall signal. When the lower bit of the rise signal is (1) and the clock signal is (0), it outputs (1) to the rise clock signal, and otherwise it outputs (0) to the rise clock signal, and the fall signal The lower bit of is (1) and the clock signal is (1)
), outputs (1) to the fall clock signal, and otherwise outputs (0) to the fall clock signal, delays the rise clock signal and outputs it as a rise delay signal, and delays the fall clock signal. When any of the rise clock signal, fall clock signal, rise delay signal, or fall delay signal is (1), it generates (1) as the output lock signal. It is possible to obtain an output clock signal obtained by dividing the frequency of the input clock signal by two-thirds, the phase of which changes by changing the frequency of the input clock signal.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG.

Here, in this embodiment, a case will be described in which frequency division by two-thirds is performed.

In the embodiment shown in FIG. 1, a rise state circuit 1 is first provided, and when the hold signal is (0), the fall signal d is (0,0), (0,1).

According to (1, O), the rise state signal e is (0°1)
, (1, O), (0, O), and when the hold signal (b) is (1), the fall signal (d) is (0
, O), (0,l), and (1°0), the rise state signal (e) is generated as (0°0), (0,1), (1,0). In addition, a false stay circuit 2 is provided so that when the hold signal C is (0), the rise signal C is (0, O).
.

According to (0,1), (1,O), (0,1), (1,0), (0,O) are generated in the false stay signal f, and when the hold signal is (1), a rise signal is generated. (0,O), (0,1) of C.

According to (1, O), the false state signal f becomes (0,0
), (0,1), (1,O) are generated.

Further, a rise latch circuit 3 is provided to store the rise state signal e at the rising edge of the clock signal a and generate the rise signal C. A fall latch circuit 4 is provided to store a false stay signal f at the falling edge of the clock signal a and generate a fall signal d. Also,
A rise clock circuit 5 is provided to output (1) to the rise clock signal g when the lower bit of the rise signal C is (1) and the clock signal a is (0), and to output (1) to the rise clock signal g at other times. Outputs (0). A fall clock circuit 6 is provided to output (1) to the fall clock signal when the lower bit of the fall signal d is (1) and the clock signal a is (1), and to output (1) to the fall clock signal at other times. Outputs (0) to . A rise delay circuit 7 is provided to delay the rise clock signal g and output it as a rise delay signal i.

A fall delay circuit 8 is provided to delay the fall clock signal and output it as a fall delay signal j. Furthermore, a clock output circuit 9 is provided to generate (1) as an output clock signal k when any one of the rise clock signal g, the fall clock signal, the rise delay signal i, and the fall delay signal j is (1). As a result, an output clock signal k, which is a frequency-divided clock signal a, whose phase changes according to the hold signal S is generated.

In the figure, rise state circuit 1. False state circuit 2. Rise latch circuit 3. Each fall latch circuit 4 has a 2-bit output. It is assumed that only the lower bits of the rise latch circuit 4 are connected to the rise clock circuit 5, and only the lower bits of the fall latch circuit 4 are connected to the fall clock circuit 6.

Further, the value of each signal is expressed as (X,

Rise state circuit 1 is connected to fall latch circuit 4 by fall signal d, and connected to an upper level circuit (not shown) by hold signal d. The false stay circuit 2 is connected to the rise latch circuit 3 by the rise signal C, and is connected to a higher level circuit (not shown) by the hold signal C. Rise latch circuit 3 is connected to rise state circuit 1 by rise state signal e, and connected to a lower circuit (not shown) by clock signal a. The fall latch circuit 4 is connected to the false state circuit 2 by the false state signal f, and is connected to a lower circuit (not shown) by the clock signal a.

The rise clock circuit 5 is connected to the rise launch circuit 3 by the lower bit of the rise signal C, and is connected to the rise launch circuit 3 by the lower bit of the rise signal C.
It is connected to a lower-order circuit (not shown). The fall clock circuit 6 is connected to the fall latch circuit 4 by the lower bit of the fall signal d, and is connected to a lower circuit (not shown) by the clock signal a. The rise delay circuit 7 delays the rise clock circuit 5 by the rise clock signal g.
connected to. The fall delay circuit 8 is connected to the fall clock circuit 6 by a fall clock signal.

The clock output circuit 9 is connected to the rise delay circuit 7 by the rise delay signal i, connected to the rise clock circuit 5 by the rise clock signal g, connected to the fall delay circuit 8 by the fall delay signal j, and connected to the fall delay circuit 8 by the fall clock signal. It is connected to the fall clock circuit 6, and is connected to an upper circuit (not shown) in the output clock signal.

Next, the functions of each block shown in the figure will be explained.

The rise state circuit 1 outputs the following value according to the value of the hold signal S and the value of the fall signal d.

Hold signal b = (0), fall signal d = (0,0
), then rise state signal e=(0,1).

Hold signal b=(o), fall signal d=(0,1)
If so, rise state signal e=(1,0).

Hold signal b=(0), fall signal d=(1,0)
If so, rise state signal e-(0,0).

Hold signal b=(1), fall signal d=(0,0)
If so, rise state signal e-(0,O).

Hold signal b=(1), fall signal d-(0,1)
If so, rise state signal e=(0,1).

Hold signal b=(1), fall signal d=(1,0)
If so, rise state signal e=(LO).

The hold signal S is a signal that becomes active only for the desired period of time when the phase of the output clock, which is the frequency division result of the clock signal a, is desired to be changed.

Similarly, the false state circuit 2 outputs the following value according to the value of the hold signal S and the value of the rise signal C.

Hold signal b = (0), rise signal C = (0°0
), then the false state signal f=(0°1).

Hold signal b=(0), Rice signal C=(01)
Then, the false state signal f=(1°O).

Hold signal b = (0), rise signal C = (1°0
), then the false state signal f=(00).

Hold signal b=(1), rise signal C=(00)
Then, the false signal f=(0°0).

If the hold signal b=(1) and the rise signal c=(0°l), the false stay signal f=(0°1).

Hold signal b = (1), rise signal c = (1°0
), then the false state signal f=(1°O).

The rise latch circuit 3 stores the rise state signal e at the rising edge of the clock signal a and outputs the rise signal C.
Output. Similarly, the fall latch circuit 4 stores the fall state signal f at the falling edge of the clock signal a and outputs the fall signal d.

The rise clock circuit 5 receives a rise signal C=(*.

1) (* indicates don't care), when the clock signal a = (0), the rise clock signal g = (1
), and under other conditions, rise clock signal g= (
0).

The fall clock circuit 6 receives a fall signal d=(*,1
), when the clock signal a=(1), the fall clock signal is set as (1), and under other conditions, the fall clock signal h=(0).

The rise delay circuit 7 delays the rise clock signal g and outputs it as a rise delay signal i.

The fall delay circuit 8 delays the fall clock signal and outputs it as a fall delay signal j.

The clock output circuit 9 receives a rise clock signal g.

fall clock signal, rise delay signal i.

When any of the fall delay signals j is (1), (
1) Output.

Next, the operation of the circuit shown in FIG. 1 will be explained.

First, as an initial state, it is assumed that the clock signal a=(0), the hold signal b=(0), the rise signal C-(0,0), and the fall signal d=(0,0). In this state, a rise state signal e=(0,1) and a false state signal f=(0,1) are output. Also,
Rise clock signal g=(0), Fall clock signal h=(0), Rise delay signal i=(0),
The fall delay signal j=(0), and the output clock signal is -(0).

When the clock signal a=(1) and the hold signal b=(0), the rise latch circuit 3 takes in the value of the rise state signal e, and the fall latch circuit 4 maintains the current value. That is, the rise signal c-(0,1) and the fall signal d=(0,0). In this state, rise state signal e=(0,1), false state signal f=(
1°0). Also, rise clock signal g=(0)
, fall clock signal h=(0), rise delay signal i=(0), fall delay signal j-(0
), so the output clock signal becomes =(0).

Next, clock signal a=(0), hold signal b=(
0), the fall latch circuit 4 takes in the value of the false state signal f, and the rise latch circuit 3 maintains the current value. That is, rise signal c=(0,1),
The fall signal d=(1°0). In this state,
The rise state signal e=(0,0), and the false state signal f=(1°O). Also, the rise clock signal g = (1), the fall clock signal h = (0), the rise delay signal 1 = (1), and the fall delay signal j - (0), so the output/link signal = (1)
becomes.

Thereafter, each signal changes in the same way, and the output clock signal k is 1. A repetition of O, O is output.

As a result, a signal obtained by frequency-dividing the clock signal a by two-thirds is output as the output clock signal k.

Next, in the state shown below, hold signal S-(1)
Think about what you will do when it happens.

Clock signal a=(0), rise signal c=(0°0), fall signal d=(0,1), rise state signal e=(1,O), fall state signal f=(0
, 1), rise clock signal g=(0).

Fall clock signal h=(0), Rise delay signal 1-(0), Fall delay signal j=(0),
Output clock signal = (0) When hold signal b = (1) in this state, rise state signal e = (0,
1), the false state signal changes to f=(0,O).

Next, clock signal a=(1) and hold signal b=
(0), each signal changes as follows.

Rise signal c=(0, l), Fall signal d=(0,
1), rise state signal e=(1,0).

False stay signal f = (1, O), rise clock signal g = (0), fall clock signal h = (1)
, rise delay signal 1 = (0), fall delay signal j = (1), output clock signal = (1) Next, when the clock signal a = (0), the following will occur.

Rise signal c=(0,1), fall signal d=(1,O
), rise state signal e=(Q,O).

False state signal f = (1, O), Rise clock signal g = (1), Fall clock signal h = (0),
Rise delay signal 1 = (1), fall delay signal j = (0), output clock signal = (1) After that, the state returns to hold signal b = (0).

That is, the continuous occurrence of =(1) in the output clock signal means that the phase of the output clock signal has changed.

Note that the rise delay circuit 7. Fall delay circuit 8
has the effect of canceling out spikes caused by the delay time difference between the rise clock circuit 5 and the fall clock circuit 6.

As described above, according to the present invention, by using both the rising edge and the falling edge of the clock signal a, it is possible to realize two-thirds frequency division.

〔Effect of the invention〕

As explained above, according to the present invention, by using the rising edge and falling edge of the reference clock signal, it is possible to use the same frequency as the conventional reference clock signal while using the same elements as the conventional one. Ba,
It is possible to obtain an NRZ data signal with a frequency approximately twice that of the conventional one.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention. 1- rise state circuit, 2--false state circuit, 3-- rise latch circuit, 4- fall latch circuit, 5-- rise clock circuit, 6-- fall clock circuit, 7- rise delay circuit, 8- -Fall delay circuit, 9-clock output circuit. Applicant Nippon Electric Co., Ltd. Agent Patent Attorney Isamu Takahashi

Claims (1)

[Claims] (1) It has a rise state circuit and a fall state circuit that output a predetermined signal in response to a hold signal sent from an upper circuit, and the rise state circuit outputs a predetermined signal in response to a rising edge of a clock signal sent from a lower circuit. a rise latch circuit that stores the output signal of the fall state circuit, and a fall latch circuit that stores the output signal of the fall state circuit at the falling edge of the clock signal, and inputs the output of the rise state circuit or the fall state circuit separately. A rise clock circuit and a fall clock circuit are provided to output "1" or "0" according to the clock signal, and a rise delay circuit and a fall delay circuit are provided to delay each output of the rise clock circuit and fall clock circuit. and inputs each output of the rise clock circuit and the fall clock circuit and each output of the rise delay circuit and the fall delay circuit, respectively, and outputs a clock signal "1" when the output of any one of these is "1". 1. A clock generation device for a magnetic disk device, comprising a clock output circuit that outputs a clock output circuit.