JPH0340540B2 - - Google Patents

Description

[Detailed description of the invention]

(Industrial Application Field) The present invention relates to a transmission code format conversion method, and particularly to a conversion circuit from a binary code format from an NRZ code to a CMI code. (Conventional technology) Conventionally, to convert NRZ code to CMI code,
A conversion circuit having the configuration shown in FIG. 5 has been used.
That is, the NRZ code signal sequence a and clock b are input, and the logic circuit 20 performs appropriate logical operations to extract "1" patterns and "0" patterns.
After converting into a "1" pattern signal string c and a "0" pattern signal string d of the CMI code by the "1" pattern conversion circuit 21 and the "0" pattern conversion circuit, the signal string c and the signal string d are combined into a combination circuit 23. are combined to generate and output a CMI code signal sequence e. FIG. 6 is a diagram showing an example of a conventional circuit and a time chart. In this circuit, the NAND circuit 44,
Since the 46 inputs are a 1-bit width signal and a 1/2-bit width clock, the transient positions of the two inputs match, and a spike occurs in the output due to the difference in delay time of the logic circuit elements. .
Also, since the NAND circuits 45 and 23 have clock components in their inputs, spikes also occur in their outputs. e' in the time chart indicates the CMI code signal sequence when a spike occurs. That is,
When the output c of the NAND circuit 45 lags behind the output d of the NAND circuit 46, a spike occurs at a location in e'. In order to eliminate this drawback, a method is proposed in which the position of the transient is adjusted by delaying the input data using the timing adjustment circuit 24 shown by the dotted line in FIG.
The frequency multiplier circuit 25 shown by the dotted line doubles the clock, and the flip-flop circuit 26 outputs the clock.
Conventionally, methods have been used to format CMI codes. (Problems to be Solved by the Invention) However, the method of aligning transients has the disadvantage that it requires individual response to variations in delay time of logic circuit elements, and also has the drawback that The shaping method also has the disadvantage of increasing the circuit scale. Furthermore, in the two methods described here, the conventional method operates at twice the bit rate of the input code string, as is clear from the explanation so far, so the setup time of flip-flop circuits, etc. There is no solution to the problem of high-speed operation, where it is difficult to maintain a phase margin for the hold time. The two drawbacks mentioned above, namely, the disturbance of the output waveform due to spikes and the problem of operating speed, are common problems in the conventional NRZ code/CMI code conversion method.In particular, when implementing LSI, timing adjustment It has become an important design issue because it is difficult to configure the circuit inside an LSI, and the conditions for safe operation of the LSI are extremely strict due to shaping using a double clock. In view of the problems in the prior art described above, an object of the present invention is to provide a circuit with a circuit scale comparable to that of the conventional circuit.
It does not cause spikes in the CMI code, and the circuit operating speed is equal to the bit rate, making it suitable for high-speed operation.
The purpose is to provide an NRZ code/CMI code conversion circuit. (Means for Solving the Problems) The present invention has the following configuration to achieve the above object. That is, the NRZ code/CMI code conversion circuit of the present invention receives the NRZ code signal sequence D _o and performs logical operations on the signal in 1-bit width units to obtain the following logical formula (1) A _o = B _o-1 (D _{o o-1} ) B _o = D _{o o-1} P _o = D _o P _o-1 where n: Bit position in the signal string P _o : "1" in CMI code Polarity that controls data alternation P _{o- 1} : Polarity of P _o one bit before (1) or the following logical formula (2) A _o = B _o-1 [D _{o o-1} + P _o-1 V] B _o = B _o-1 ( _o ) P _o = P _o-1 (D _o V) However, n, P _o , P _o-1 : Same as above formula V: Violation signal ...(2) Signal string A _o and signal string B expressed by a logic circuit that outputs two signal strings of _o ; a delay circuit that delays one of the two signal strings by a half bit width; a delayed signal string from the delay circuit; and an exclusive OR circuit that receives as input the other signal string of the two signal strings and outputs a CMI code signal string. (Function) As is clear from the above configuration, the conversion circuit of the present invention generates a CMI code by combining two 1-bit width signal strings with a phase difference of 1/2 bit using an exclusive OR circuit. The two columns of signals are generated by appropriate logic circuits. FIG. 2a illustrates the principle of the invention. Focusing on one period t _o to t _o+1 , signal A and signal A
Let C be the output of the exclusive OR of the signal B with a 1/2 bit phase shift, then the truth table is
Figure b. Figure 2b includes all states regarding A _o , B _o-1 , and B _o , for example, when “0” is input in the NRZ code and B _o-1 is “0” teeth,
If A _o is set to “0” and B _o is set to “1” as indicated by * in the figure, the exclusive OR circuit output C _o will be “0” in the CMI code.
It becomes a pattern. As is clear from the above, A _o ,
By appropriately selecting the combination of B _o-1 and B _o , the exclusive OR output C _o can be made to match the desired CMI code. The logic circuit in the above configuration is configured based on a logical formula or a truth table corresponding to the logical formula to obtain the desired CMI code string for the input signal of the NRZ code. In this case, it is possible to obtain two signal sequences that result in the desired CMI code. It is easy to determine a logic circuit from a logic formula or a truth table corresponding to the logic formula. As described above, the input NRZ code signal sequence in the logic circuit of the present invention is processed in 1-bit width units, that is, at the bit rate of the input signal, and no signal is generated based on the clock component. First, this point differs from conventional conversion circuits. After two signal sequences are obtained by the logic circuit, the signals are shifted in phase by 1/2 bit and then applied to the exclusive OR circuit. Therefore, the transients of the two signal trains applied to the exclusive OR circuit never match, and even if there are variations in the delay times of the logic circuit elements, there is no room for spikes to occur. . (Example) Hereinafter, an example of the present invention will be described based on the drawings. FIG. 1 is a simplified block diagram of an embodiment of the invention. A signal train D of the NRZ code and a clock signal are added to the logic circuit 10 configured based on a logical formula or a truth table corresponding to the logical formula, and the signal train
B _o-1 and A _o are output. Here, the clock signal is a pulse train that repeats positive and negative with a width that is half the bit width of the input code string. signal train
B _o-1 is applied to a flip-flop circuit (hereinafter referred to as F/F) 11, and signal train A _o is applied to F/F 12. On the other hand, a clock signal is applied to the F/F 12, and a clock signal whose polarity has been inverted by an inverting circuit 13 is applied to the F/F 11. In other words, a clock signal shifted by 1/2 bit is applied to F/F11 and F/F12, and therefore, the difference between the output signal strings of each F/F is also greater than that between the input signal strings. It is shifted by 1/2 bit. That is, either one of the signal trains will be delayed by 1/2 bit with respect to the other signal train. Which signal train is delayed is determined by the polarity of the clock pulse and the setting of the timing relationship between the input code train and the clock pulse. The output signal string B of F/F 11 and the output signal string A (A _o-1 ) of F/F 12 are each output from exclusive OR circuit 1.
4 and output as a signal sequence C of CMI code. In NRZ code/CMI code conversion, in addition to the input NRZ code signal sequence and clock, one more input is added, and that signal is “1” (active).
In this case, the previously output “1” pattern
A violation signal is usually superimposed by outputting the CMI code while maintaining its polarity without inverting it. Specific circuit examples will be shown below for cases in which this violation signal is not included and cases in which it is included. FIG. 3 is an example of a circuit in which no violation is involved. If it does not include violation,
The truth table for conversion from NRZ code to CMI code is Table 1 corresponding to logical formula (1). In the truth table, D is the input NRZ code, P _o-1 and P _o are "1"
This is the polarity that controls the alternation of data. A _o , B _o , and B _o-1 are the signals described in FIGS. 2a and 2b. FIG. 3 is a diagram showing a circuit example and a time chart that specifically implement the truth table shown in Table 1. FIG. 4 shows a truth table corresponding to the logical formula (2) when a violation is included in Table 2, as well as its realization circuit and time chart. In this case, the number of variables that determine the outputs A _o , B _o , and P _o is increased by one variable compared to the case without violation, but the basic circuit configuration method remains the same.

【table】

[Table] (Effects of the invention) As explained above, the NRZ code/
The CMI code conversion circuit does not need to generate signals using clock components, and the input of the exclusive OR circuit, which is the final output, can be shaped with positive-phase and negative-phase clocks, so no spikes occur in the output CMI code. There is an advantage. Further, according to the present invention, since the operating speed of the circuit is equal to the bit rate of the input code string, it is easy to obtain a phase margin, and therefore it is more suitable for high-speed operation than the conventional system. Furthermore, since the logic circuit that is a component of the present invention can be easily determined from a logic formula or a truth table corresponding to the logic formula, there is a large degree of freedom in circuit configuration, which is advantageous in terms of circuit design. As explained above, the NRZ code/
The CMI code conversion circuit has a circuit scale similar to that of conventional circuits, and simultaneously solves the two problems of the conventional method: spike generation in the output CMI code and unsuitability for high-speed operation.It is also a circuit particularly suitable for LIS. has been successful in providing.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the configuration of an embodiment of the present invention, FIG. 2 is a diagram explaining the principle of the present invention, FIGS. 3 and 4 are diagrams showing a circuit diagram and a time chart of an embodiment of the present invention, and FIG. The figure shows an example of the configuration of a conventional conversion circuit, and FIG. 6 is a diagram showing an example of the conventional conversion circuit and a time chart. 10...Logic circuit, 11, 12...Flip-flop circuit, 13...Inversion circuit, 14...Exclusive OR circuit, 20...Logic circuit, 21..."1"
Pattern conversion circuit, 22... "0" pattern conversion circuit, 23... Combined circuit (NAND circuit), 30~
32...exclusive OR circuit, 34...AND circuit,
36, 38...flip-flop circuit, 40, 4
1...Flip-flop circuit, 42, 43...Inversion circuit, 44-46...NAND circuit, 801-
804...Flip-flop circuit, 807-81
0...OR circuit, 811-813...Exclusive OR circuit, 815...AND circuit, a, D _o ...NRZ
Code signal sequence, b...clock signal, e, C...
CMI code signal sequence, V...Violation signal.

Claims (1)

[Claims] 1. Receive the NRZ code signal sequence D _o and perform logical operations on the signal in 1-bit width units to obtain the following logical formula (1) A _o = B _o-1 (D _{o o-1} ) B _o = D _{o o-1 o} = D _o P _o-1 where n: Bit position in the signal string P _o : "1" in CMI code Polarity that controls data alternation P _o-1 : 1 bit of P _o Previous polarity...(1) or the following logical formula (2) A _o = B _o-1 [D _{o o-1} + P _o-1 V] B _o = B _o-1 ( _o ) P _o = P _{o- 1} (D _o V) However, n, P _o , P _o-1 : Same as above formula V: Violation signal ...(2) Two signal strings, signal string A _o and signal string B _o, expressed as a logic circuit that outputs a signal example of the two signal sequences; a delay circuit that delays one of the two signal sequences by a half bit width; a delayed signal sequence from the delay circuit; an exclusive OR circuit that receives the other signal string as input and outputs a CMI code signal string;
NRZ code/CMI code conversion circuit.