JPH0485959A - Master slice - Google Patents

Abstract

PURPOSE:To densify an integrated circuit by arranging transistors at certain angles to wiring lattices so that their electrodes may be arranged on different wiring lattices. CONSTITUTION:In the figure, X1-X15 and Y1-Y15 are wiring lattices, L11-L21 are Wirings made of first-layer aluminum, GND, VREF, VCS, VT, and VEE are source wirings made of second-layer aluminum, B11-B17 are the base electrodes of transistors Q11-Q17 respectively, C11-C17 are the collector electrodes of the transistors Q11-Q17 respectively, and E11-E17 are the emitter electrodes of the transistors Q11-Q17 respectively. The transistors are arranged at an angle of 45 deg. to the wiring lattices. Thereby when the wirings are drawn from the electrodes the direction of the drawing is not limited by the adjacent electrodes and the wires are distributed more freely. Moreover, the wires are distributed efficiently because detouring wiring is not required.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a master slice, and particularly to a bipolar master slice.

[Prior Art] FIG. 4 is a plan view of a semiconductor integrated circuit manufactured using a conventional master slice, which embodies the three-man OR/N OR gate shown in FIG. It is. In Fig. 3, I11 to ■1 are input terminals, OIL
, o1□ is an output terminal, Q11 to Q1f are transistors,
R11 to R16 are resistors, GND is the high-side power supply, Vp-B
is the low side power supply, one is the emitter follower termination power supply, VR
EF is a reference potential power supply, and VC5 is a current source power supply.

In Fig. 4, parts corresponding to those in Fig. 3 are given the same reference numbers (however, the symbols indicating each power supply in Fig. 3 indicate the power supply wiring for that power supply in Fig. 4). ), in Figure 4, ×1 to X1□
, Y1 to YI3 are wiring grids, L31 to L4) are first layer A
Wiring formed by ρ5. GND, VR
EF, Vcs, VT, and V- are power supply wirings formed by the second layer Af, and Bll to B17 are bases ti, c-th to C of transistors Q++ to Qt7, respectively.
I7 are collector electrodes of transistors Q11 to QI7, respectively, and Ell to E1 are collector electrodes of transistors Q1□ to QI7, respectively.
This is the emitter electrode of Q+7.

[Problems to be Solved by the Invention] In the conventional master slice described above, the electrodes of all transistors are arranged so as to be placed on the same wiring grid. For example, transistor QI
The linear connection between the emitter of #2 @#1Esz and the emitter electrode EI3 of transistor Q+3 is
It is obstructed by the collector electrode C1□ of □ and the collector electrode CI3 of the transistor QI3, and the wiring for connecting both emitters is detoured to the adjacent wiring grid Y6.

Furthermore, when forming the wiring to access the base electrode B12 of the transistor QI2, which is the input terminal of the three-man OR/N OR gate, in the first layer Af, wiring is only allowed from two directions, the top and bottom of the figure. Not yet. Therefore, the conventional master slice has a low degree of freedom in wiring.

Additionally, with current wiring technology, it is possible to create wiring with narrower spacing than the electrode spacing of transistors;
In the conventional example, since the electrodes of transistors are arranged along the same wiring grid, the spacing of the wiring grid is regulated by the spacing of the transistor electrodes. Therefore, in the conventional example, it has not been possible to achieve high integration to the limit of wiring technology.

[Means for Solving the Problems] In the master slice according to the present invention, circuit elements including transistors are formed on a semiconductor substrate in advance, and according to a desired circuit, the electrodes of the circuit elements are connected by wiring along a wiring grid. The transistor is characterized in that its electrodes are arranged at an angle with respect to the wiring grid so that their electrodes do not lie on the same wiring grid.

[Embodiments] Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a plan view for explaining one embodiment of the present invention, and similarly to FIG.
This is an embodiment of the R/NOR gate. In FIG. 1, parts corresponding to those in FIG. 3 are given the same reference numerals. Figure 1 Nioite, Xl-X,,,Y,
~Y, 5 is a wiring grid, Lll~L21 is a wiring formed by the first layer Aρ, GND, VREF, V
O2, Vd, and Vll are the power supply wirings formed by the second layer A1, respectively, BJI to BJ7 are the base electrodes of the transistors Q1+ to Q17, and 01□ to C17, respectively.
are the collector electrodes of the transistors Q++ to Q+7, respectively, Ell to E, ) are the collector electrodes of the transistors Q+t to Q!, respectively.
This is the main emitter electrode.

In this embodiment, each transistor is arranged at an angle of 45 degrees with respect to the wiring grid. If you configure it like this, it will be the same! ! Since there are no electrodes or wiring that disturb the connection between the emitter electrode E12 of the transistor Qs2 and the emitter electrode E13 of the transistor Q13, which are arranged on the grid ￥9, the connection between the two electrodes is made on the lsl grid ￥9. It becomes possible to connect the wires by running the wires in a straight line. In addition, since there are no electrodes or wires around the base electrode B12 of the transistor Q12, which is the input terminal, to prevent wiring, connections between other circuits and this electrode can be made from the first layer A (This can be done by

In addition, since the transistor is tilted at 45 degrees with respect to the wiring grid, the M grid spacing is
The interval is 1/, rl. Therefore, according to the present invention, the wiring density can be increased, and furthermore, the connection between electrodes can be performed by straight wiring without using detour wiring, so that it is possible to increase the density of the integrated circuit.

FIG. 2 is a plan view showing another embodiment of the invention. In the same figure, C21, B21 B2□ are the collector electrode, emitter electrode, and base electrode of the first transistor with a small area, and t, C2□, B22 . B22 are the collector electrode, emitter electrode, and base electrode of the second transistor, each having a large area. This embodiment relates to a case in which a first transistor and a second transistor with a small area are mixed, but even in such a case, according to the present invention, the wiring to each electrode can be connected to the other electrode. This allows for a high degree of freedom in wiring.

Note that in the above example, all transistors were arranged at an angle to the wiring grid, but if there is sufficient space, some transistors may be arranged not to be inclined to the wiring grid. can.

[Effects of the Invention] As explained above, the present invention avoids placing each electrode of a transistor on the same wiring grid. According to the present invention, when drawing out the wiring from each electrode, , the wiring direction is no longer subject to IIJ restrictions due to adjacent electrodes, and the degree of freedom in wiring increases. Further, since detour wiring can be avoided, efficient wiring becomes possible.

Furthermore, by tilting the arrangement direction of the transistors to the direction of the wiring lattice, the wiring lattice spacing, which was conventionally determined to be the same as the ti spacing of the transistor, can be made smaller than the electrode spacing of the transistor. When the transistor is tilted at 45 degrees with respect to the wiring grid, the wiring grid spacing can be set to 1/v"7 of the transistor electrode spacing, which reduces the number of wiring grids to 1 in the conventional method.
This makes it possible to increase the size by seven times, making it possible to miniaturize and increase the density of integrated circuits.

[Brief explanation of the drawing]

FIG. 1 is a plan view showing an embodiment of the present invention, and FIG. 2 is a plan view showing an embodiment of the present invention.
FIG. 4 is a plan view showing another embodiment of the present invention, FIG. 4 is a plan view of a conventional example, and FIG. 3 is an equivalent circuit diagram of the integrated circuit device shown in FIGS. 1 and 4. B11 to B+7, B21, B22... base electrode,
011~CI7, C2□, C2□... Collector is pole, Ell~E1), B21. R22...Emitter electrode, GND...Higher side power supply (or its wiring), I11~■13...Input terminal, Lth~L21, R31~R43...Wiring, 01.02
...output terminal, Q1+~QI7...transistor, R11~R16...resistor, ■. 5...Current source power supply (unplugged or its wiring), VER...Low side power supply (or its wiring), VREF...Reference potential power supply (or its wiring), VD...Emitter follower termination power supply. or its wiring), X1 to xx5, Y
l ~ Y 15''' wiring grid.

Claims (2)

[Claims] (1) Circuit elements including transistors are placed in advance in a semiconductor substrate, and the desired integrated circuit is completed by connecting the electrodes of the circuit elements with wiring that passes on a preset wiring grid according to the circuit configuration. A master slice characterized in that the transistors are arranged at an angle with respect to the wiring grid so that each electrode of the transistor is arranged on a different wiring grid. (2) The master slice according to claim 1, comprising a transistor in which all electrodes are arranged on the same wiring grid.