JPH0482739U - - Google Patents
Info
- Publication number
- JPH0482739U JPH0482739U JP12252390U JP12252390U JPH0482739U JP H0482739 U JPH0482739 U JP H0482739U JP 12252390 U JP12252390 U JP 12252390U JP 12252390 U JP12252390 U JP 12252390U JP H0482739 U JPH0482739 U JP H0482739U
- Authority
- JP
- Japan
- Prior art keywords
- board
- bus
- data
- input
- evaluation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000011156 evaluation Methods 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Landscapes
- Test And Diagnosis Of Digital Computers (AREA)
Description
第１図は本考案の一実施例を示す構成図、第２
図は同実施例のＩ／Ｏボード評価処理の手順を示
すフローチヤートである。
１……バス、２……ＣＰＵ、３……Ｉ／Ｏボー
ド、４……バスモニタ用ボード（テスタボード）
、５……入出力部、６……ＬＥＤ表示器、７……
メモリ、８……制御部、１０……ＤＭＡコントロ
ーラ。
Fig. 1 is a configuration diagram showing one embodiment of the present invention;
The figure is a flowchart showing the procedure of I/O board evaluation processing in the same embodiment. 1... Bus, 2... CPU, 3... I/O board, 4... Bus monitor board (tester board)
, 5... Input/output unit, 6... LED display, 7...
Memory, 8...control unit, 10...DMA controller.
Claims (1)
バスデータに対する入出力を制御する入出力部と
、 この入出力部を介して取り込まれたバス上のデ
ータの状態をビツト単位で表示する表示器と、 バスに接続されたＩ／Ｏボードに対する評価用
データを記憶したメモリと、 前記Ｉ／Ｏボード評価時には、前記メモリから
評価用データを読出してＩ／Ｏボードに転送する
一方、評価用データに応答してＩ／Ｏボードから
送出された応答データの状態を前記表示器に表示
させる制御部とを備えて成るバスモニタ用ボード
。[Scope of claim for utility model registration] It is configured to be detachable from the bus, and
An input/output section that controls the input/output of bus data; a display that displays the status of data on the bus taken in via this input/output section in bit units; and evaluation of the I/O board connected to the bus. When evaluating the I/O board, the evaluation data is read from the memory and transferred to the I/O board, and a response sent from the I/O board in response to the evaluation data is stored. A bus monitor board comprising: a control section for displaying data status on the display device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12252390U JPH0482739U (en) | 1990-11-26 | 1990-11-26 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12252390U JPH0482739U (en) | 1990-11-26 | 1990-11-26 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0482739U true JPH0482739U (en) | 1992-07-17 |
Family
ID=31870300
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12252390U Pending JPH0482739U (en) | 1990-11-26 | 1990-11-26 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0482739U (en) |
-
1990
- 1990-11-26 JP JP12252390U patent/JPH0482739U/ja active Pending
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