JPS6257848U - - Google Patents
Info
- Publication number
- JPS6257848U JPS6257848U JP15037185U JP15037185U JPS6257848U JP S6257848 U JPS6257848 U JP S6257848U JP 15037185 U JP15037185 U JP 15037185U JP 15037185 U JP15037185 U JP 15037185U JP S6257848 U JPS6257848 U JP S6257848U
- Authority
- JP
- Japan
- Prior art keywords
- data
- data buffer
- bus
- bitmap memory
- cpu
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Image Processing (AREA)
- Digital Computer Display Output (AREA)
Description
第１図は本考案の一実施例を示すブロツク図、
第２図はビツトマツプメモリ内のイメージと表示
画像の重み関係が一致する場合の説明図、第３図
はビツトマツプメモリ内のイメージと表示画像の
重み関係が異なる場合の説明図。
符号の説明、１０……ＣＰＵ、１１……データ
バス、１２……ビツトマツプメモリ、１３，１４
……データバツフア、１５……データバツフア制
御回路。
FIG. 1 is a block diagram showing an embodiment of the present invention.
FIG. 2 is an explanatory diagram when the weight relationship between the image in the bitmap memory and the display image is the same, and FIG. 3 is an explanatory diagram when the weight relationship between the image in the bitmap memory and the display image is different. Explanation of symbols, 10...CPU, 11...Data bus, 12...Bit map memory, 13, 14
...Data buffer, 15...Data buffer control circuit.
Claims (1)
等に対する表示に用いられるビツトマツプメモリ
を備えたデータ処理装置において、 前記ビツトマツプメモリとＣＰＵ間のデータバ
スに挿入されて、入力データを同一番号のバスラ
インへ出力する第１のデータバツフアと、 前記ビツトマツプメモリとＣＰＵ間のデータバ
スに挿入されて、入力データを異なる番号のバス
ラインへ出力する第２のデータバツフアとを備え
、 通常状態の表示にあつては前記第１のデータバ
ツフアを動作させ、前記ビツトマツプメモリでの
重み付けと前記ＣＲＴ等の重み付けを逆にする際
には前記第２のデータバツフアを動作させること
を特徴とするデータ処理装置。[Scope of claim for utility model registration] Accessible in word units, CRT
A data processing device equipped with a bitmap memory used for displaying data such as a first data buffer, which is inserted into a data bus between the bitmap memory and the CPU, and outputs input data to a bus line having the same number; a second data buffer inserted into a data bus between the bit map memory and the CPU and outputting input data to a bus line with a different number; operating the first data buffer when displaying a normal state; A data processing apparatus characterized in that the second data buffer is operated when the weighting in the bitmap memory and the weighting in the CRT or the like are reversed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15037185U JPS6257848U (en) | 1985-10-01 | 1985-10-01 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15037185U JPS6257848U (en) | 1985-10-01 | 1985-10-01 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6257848U true JPS6257848U (en) | 1987-04-10 |
Family
ID=31066452
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15037185U Pending JPS6257848U (en) | 1985-10-01 | 1985-10-01 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6257848U (en) |
-
1985
- 1985-10-01 JP JP15037185U patent/JPS6257848U/ja active Pending
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