JPS6052543U - Graphic input display device - Google Patents
Graphic input display deviceInfo
- Publication number
- JPS6052543U JPS6052543U JP14230583U JP14230583U JPS6052543U JP S6052543 U JPS6052543 U JP S6052543U JP 14230583 U JP14230583 U JP 14230583U JP 14230583 U JP14230583 U JP 14230583U JP S6052543 U JPS6052543 U JP S6052543U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- display device
- diagram showing
- data
- input display
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Processing Or Creating Images (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案の一実施例を示す全体のブロック図、第
２図は本考案を説明するための説明図、第３図、第４図
、第５図、第６図、第７図は実施例装置の処理動作を示
すフローチャート、第８図、第９図は実施例を説明する
ための説明図、第１０図は実施例装置の処理動作を示す
フローチャート、第１１図は他の実施例を示すブロック
図、第１２図は文字データ格納メモリマスク例を示す図
、第１３図はグラフィックデータ格納メモリマスク例を
示す図、第１４図は第１２図、第１３図を重ね合せた表
示装置における表示例を示す図、第１５図は従来のＭＰ
Ｕ周辺回路を示すブロック図、第１６図は従来のＭＰＵ
周辺回路によるアドレス構成を示す説明図、第１７図は
従来の回路が回路追加された場合のアドレス構成を示す
説明図、第１８図は本考案の他の実施例を示すＭＰＵ周
辺回路のブロック図、第１９図は第１８図上の回路８と
９の詳細を示すブロック図、第２０菌は第１８図による
アドレス構成を示す説明図、第２１図は第２０図に回路
追加された場合のアドレス構成を示す説明図である。
１：キーボード、２：キーボード制御回路、３：フロッ
ピーディスク装置、４：フロッピーディスク制御回路、
５：キャラジエネ用ＲＯＭ。
’６ ： ＲＡＭ、 ７ ： ＲＯＭ、 ８ ： Ｖ−
ＲＡＭ、 ９ ：マイクロコンピュータ、１０ ：ＣＲ
Ｔ制御回路、１１：ＣＲＴ、２１：制御部、２２：表示
マスクレジスタ、２３：表示文字格納メモリ、２４．２
６：表示マスク制御部、２５：画面表示制御部、２７：
グラフィックデータ格納メモリ、２８二文字データ生成
部、２９．３０：パラレルデータシリアル変換部、３１
：画面表示データ重ね合せ制御部、３２：表示装置、４
１：マイクロプロセッサ（ＭＰＵ）、４２ ： ＲＯＭ
、 ４３ ：ＲＡＭ、 ４４：外部記憶装置、４５：外
部記憶装置コントロール回路、４６：電源投入直後のリ
セット発生回、路、４７：アドレスデコーダ、４８ ：
ＲＯＭ／ＲＡＭセレクト回路、４９：セレクトコントロ
ール回路及びＭＰＵＩＪセットパルス発生回路、５０：
ＲＡＭセレクト用ＯＲ回路、５１ ＳＲＡＭアクセスイ
ネーブル回路、５２：ＲＯＭセレクト用ＡＮＤ回路、５
３：ＲＯＭアクセスイネーブル回路、５４：ＲＯＭイネ
ーブル回路、５５：リセット用ＯＲ回路、５６：セレク
トコントロール回路及びＭＰＵリセット回路イネーブル
回路、６０ニアドレス及びコントロールバス、６１：デ
ータバス。
ｔ＝ｔｖｒＲＹ
キーボ′−ドＪ−リ
１文字Ｒｅａｒｌ
ｌ ｂ ｖｔ−、ｑ −ｍ Ｉ
：井ヰ田井井
４寸寸十上七土七ｔｆ−七七Fig. 1 is an overall block diagram showing an embodiment of the present invention, Fig. 2 is an explanatory diagram for explaining the invention, Figs. 3, 4, 5, 6, and 7. is a flowchart showing the processing operation of the embodiment device, FIGS. 8 and 9 are explanatory diagrams for explaining the embodiment, FIG. 10 is a flowchart showing the processing operation of the embodiment device, and FIG. 11 is a flowchart showing the processing operation of the embodiment device. A block diagram showing an example, Fig. 12 is a diagram showing an example of a character data storage memory mask, Fig. 13 is a diagram showing an example of a graphic data storage memory mask, and Fig. 14 is a superimposed display of Figs. 12 and 13. A diagram showing an example of display on the device, FIG. 15 is a conventional MP
A block diagram showing the U peripheral circuit, Figure 16 is a conventional MPU
FIG. 17 is an explanatory diagram showing an address configuration by a peripheral circuit. FIG. 17 is an explanatory diagram showing an address configuration when a conventional circuit is added. FIG. 18 is a block diagram of an MPU peripheral circuit showing another embodiment of the present invention. , FIG. 19 is a block diagram showing the details of circuits 8 and 9 in FIG. 18, FIG. 20 is an explanatory diagram showing the address configuration according to FIG. 18, and FIG. FIG. 2 is an explanatory diagram showing an address configuration. 1: Keyboard, 2: Keyboard control circuit, 3: Floppy disk device, 4: Floppy disk control circuit,
5: ROM for Charagiene. '6: RAM, 7: ROM, 8: V-
RAM, 9: Microcomputer, 10: CR
T control circuit, 11: CRT, 21: control unit, 22: display mask register, 23: display character storage memory, 24.2
6: Display mask control section, 25: Screen display control section, 27:
Graphic data storage memory, 28 Two character data generation section, 29. 30: Parallel data serial conversion section, 31
: Screen display data superimposition control unit, 32: Display device, 4
1: Microprocessor (MPU), 42: ROM
, 43: RAM, 44: External storage device, 45: External storage device control circuit, 46: Reset generation circuit immediately after power-on, 47: Address decoder, 48:
ROM/RAM select circuit, 49: Select control circuit and MPUIJ set pulse generation circuit, 50:
OR circuit for RAM selection, 51 SRAM access enable circuit, 52: AND circuit for ROM selection, 5
3: ROM access enable circuit, 54: ROM enable circuit, 55: OR circuit for reset, 56: select control circuit and MPU reset circuit enable circuit, 60 near address and control bus, 61: data bus. t=tvrRY Keyboard J-ri 1 character Rial l b vt-, q -m I: Iidai 4 dimensions 10 kami 7 earth 7 tf-77
Claims (1)
任意の図形、及び、これに関連する文字データ表示場所
を入力する手段と、このデータを記憶する手段を有し、
この記憶データをもとに、これをＣＲＴ画面のどこに表
示するかというデータの入力手段、及び、その図形に付
加される文字データを入力する手段により、ＣＲＴ画面
に、図形及び文字を表示する図形入力表示装置。It has a means for inputting an arbitrary figure surrounded by a predetermined straight line, an arc, etc., and a display location of character data related thereto, and a means for storing this data,
Based on this stored data, a figure that displays figures and characters on the CRT screen by means of inputting data on where to display this on the CRT screen and means of inputting character data to be added to the figure. Input display device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14230583U JPS6052543U (en) | 1983-09-16 | 1983-09-16 | Graphic input display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14230583U JPS6052543U (en) | 1983-09-16 | 1983-09-16 | Graphic input display device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6052543U true JPS6052543U (en) | 1985-04-13 |
Family
ID=30318017
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14230583U Pending JPS6052543U (en) | 1983-09-16 | 1983-09-16 | Graphic input display device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6052543U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03250374A (en) * | 1990-02-28 | 1991-11-08 | Hitachi Ltd | Method and device for editing graphic |
-
1983
- 1983-09-16 JP JP14230583U patent/JPS6052543U/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03250374A (en) * | 1990-02-28 | 1991-11-08 | Hitachi Ltd | Method and device for editing graphic |
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