JPS5925589U

JPS5925589U - color display device

Info

Publication number: JPS5925589U
Application number: JP12003382U
Authority: JP
Inventors: 出小川
Original assignee: 三菱電機株式会社
Priority date: 1982-08-05
Filing date: 1982-08-05
Publication date: 1984-02-17

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of the drawing]

第１図は従来のカラーディスプレイ装置のブロック図、
第２図は第一１図の装置によってモニタ表示される画面
の一例を示す図、第３図は本考案に係るカラーディスプ
レイ装置の好ましい一実施例を示すブロック図、第４図
は第３図の装置によってモニタ表示される画面の一例を
示す図、及び第５図は本考案に係るカラーディスプレイ
装置の他の実施例を示すブロック図、である。１・・・・・・制御回路、２′・・・・・・文字・図形
コードメモリ、２ａ・・・・・・色指定コードメモリ、
２ｂ、　　２ｂ′・・・・・・背景色指定コードメモリ
、３′・・・・・・バッファレジスタ、４・・・・・・
文字・図形パターンメモリ、５・・・・・・シフトレジ
スタ、６′・・・・・・遅延メモリ、７′、９・・・・
・・ゲート回路、８・・・・・・モニタ、Ｃ・・・・・
・背景色存在コードメモリ。尚、図中、同一符号は同−
又は相当部分を示す。Figure 1 is a block diagram of a conventional color display device.
2 is a diagram showing an example of a screen displayed on a monitor by the device shown in FIG. 11, FIG. 3 is a block diagram showing a preferred embodiment of the color display device according to the present invention, and FIG. FIG. 5 is a block diagram showing another embodiment of the color display device according to the present invention. 1...Control circuit, 2'...Character/graphic code memory, 2a...Color specification code memory,
2b, 2b'...Background color specification code memory, 3'...Buffer register, 4...
Character/figure pattern memory, 5...shift register, 6'...delay memory, 7', 9...
...Gate circuit, 8...Monitor, C...
・Background color existence code memory. In addition, in the figures, the same symbols are the same.
or a corresponding portion.

Claims

[Scope of utility model registration request]

(1) Character/graphic code memory including character/graphic section address code memory and color specification code memory; buffer register; memory storing display dot patterns of each character/graphic section; shift register; gate circuit; and the above-mentioned characters.・Transfer the predetermined character/figure section address code and color designation code of the figure code memory to the buffer register, load the display dot pattern into the shift register sequentially according to the predetermined character/figure section address code, and transfer the display dot pattern to the shift register. a control circuit for displaying desired characters and figures on a monitor screen by performing a first logical product of the output signal of the register and a predetermined delay signal from the delay memory of the color designation code of the buffer register in the gate circuit; In the color display device, the character/graphic code memory, the buffer register, and the delay memory each include the color specifying code 4. In addition to the IJ, a background designation code memory is provided and interconnected, and the gate circuit receives a second signal of the background designation code added to the delay memory and a signal obtained by inverting the output signal of the shift register. A color display device characterized in that the color display device is configured to perform a logical product of the first logical product value and a second logical product value.

(2) The color display device according to claim 1, wherein the background designation code memory is a background color designation code memory.

(3) The color display device according to claim 1, wherein the background designation code memory is constituted by a logical product of a background color presence code memo, wa, and a fixed background color designation code memory.