JPS58195284U - graphic display device - Google Patents

graphic display device

Info

Publication number
JPS58195284U
JPS58195284U JP9456682U JP9456682U JPS58195284U JP S58195284 U JPS58195284 U JP S58195284U JP 9456682 U JP9456682 U JP 9456682U JP 9456682 U JP9456682 U JP 9456682U JP S58195284 U JPS58195284 U JP S58195284U
Authority
JP
Japan
Prior art keywords
display
graphic display
pattern
graphic
display device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9456682U
Other languages
Japanese (ja)
Inventor
無川　紘洋
Original Assignee
富士通株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 富士通株式会社 filed Critical 富士通株式会社
Priority to JP9456682U priority Critical patent/JPS58195284U/en
Publication of JPS58195284U publication Critical patent/JPS58195284U/en
Pending legal-status Critical Current

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  • Digital Computer Display Output (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来のグラフィックディスプレイ装置を説明す
る構成図、第２図は本考案に係るグラフィックディスプ
レイ装置の一実施例を説明する構成図、第３図および第
４図は、本考案に係る表示画面上に表示する図形パター
ンを説明する説明図である。 図において１は情報処理装置、４，５はリフレッシュメ
モリ、６はパターン発生器、７はキーボード、８はＯＲ
ゲート、９は表示部、２１は表示回路部、２２はスケー
ル表示パターン用メモリ回路、３１は表示画面、３２は
図形表示パターン、４１はスケール表示パターンを示す
。FIG. 1 is a block diagram illustrating a conventional graphic display device, FIG. 2 is a block diagram explaining an embodiment of the graphic display device according to the present invention, and FIGS. 3 and 4 are display diagrams according to the present invention. FIG. 2 is an explanatory diagram illustrating a graphic pattern displayed on a screen. In the figure, 1 is an information processing device, 4 and 5 are refresh memories, 6 is a pattern generator, 7 is a keyboard, and 8 is an OR
9 is a display section, 21 is a display circuit section, 22 is a memory circuit for a scale display pattern, 31 is a display screen, 32 is a graphic display pattern, and 41 is a scale display pattern.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 情報処理装置からの文字、図形表示情報を、リフレッシ
ュメモリおよびパターン発生器からなる表示回路部に入
力して表示面上に文字、図形表示パターンを表示する構
成において、前記表示回路部にスケール表示パターン用
メモリ回路を設けて、前記表示面上に表示された図形表
示パターンに、対するスケール表示パターンの重畳表示
を選択的に行なうことを特徴とするグラフィックディス
プレイ装置。In a configuration in which character and graphic display information from an information processing device is input to a display circuit section comprising a refresh memory and a pattern generator to display a character and graphic display pattern on a display screen, a scale display pattern is provided in the display circuit section. 1. A graphic display device comprising a memory circuit for selectively superimposing a scale display pattern on the graphic display pattern displayed on the display surface.
JP9456682U 1982-06-23 1982-06-23 graphic display device Pending JPS58195284U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9456682U JPS58195284U (en) 1982-06-23 1982-06-23 graphic display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9456682U JPS58195284U (en) 1982-06-23 1982-06-23 graphic display device

Publications (1)

Publication Number Publication Date
JPS58195284U true JPS58195284U (en) 1983-12-26

Family

ID=30226305

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9456682U Pending JPS58195284U (en) 1982-06-23 1982-06-23 graphic display device

Country Status (1)

Country Link
JP (1) JPS58195284U (en)

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