JPH0482099A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To perform a high-speed test by testing the writing and reading of a memory part while generating an address signal for test and data for writing according to a clock signal and outputting a timing signal for test to the outside. CONSTITUTION:At the time of the test, a test mode is selected by a control signal CNT, selectors 4A and 4B are switched to a test circuit 6 side, the control of reading and writing is performed, and the operation timing and operation control of respective parts is performed by a control signal generation part 65. Therefore, the operation test of a memory part 5 is performed at high speed, and the result of the test is decided by observing a test result signal TR outputted from a comparison circuit 66 at the point of time when the test end signal TE is outputted. Thus, the high-speed test can be performed.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to semiconductor memories.

[Conventional technology]

An example of a conventional semiconductor memory is shown in FIG.

This semiconductor memory includes an address input buffer circuit 1 that inputs an address signal AD from the outside and transmits it to the memory section 5, and an address input buffer circuit 1 that inputs write data from the outside and transmits it to the memory section 5.
a memory section that writes the data transmitted from the write data buffer circuit 2 to the address specified by the address signal transmitted from the address input buffer circuit 1 and reads the stored data. 5, and a control circuit 3B that controls transmission of the address signal AD, transmission of write data, and controls writing and reading of the memory section 5.

To test the operation quality of this semiconductor memory, the IC
Address signal AD using external test equipment such as a tester
and write data DT, and the read data (
○UT) was compared with the expected value generated by this test device.

[Problem to be solved by the invention]

The above-mentioned conventional semiconductor memory is configured to use an external test device to test its operation, so the operating speed is determined by the external test device and has the disadvantage that high-speed testing cannot be performed. Another disadvantage is that the test contents are determined by the functions of the test device, and the access time of the memory section 5 and the like cannot be measured.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory that allows high-speed testing and measurement of the access time and the like of the memory section.

[Means to solve the problem]

The semiconductor memory of the present invention includes an address input buffer circuit that inputs an external address signal and transmits it to an output terminal, a write data buffer circuit that inputs external write data and transmits it to an output terminal, and an address input buffer circuit that inputs an external address signal and transmits it to an output terminal. a ring oscillator whose oscillation frequency can be changed by a signal; a clock signal generation section that generates a tarokk signal based on the output signal of the ring oscillator; an address data generation section that generates an internal address signal for testing according to the clock signal; and the clock signal. a read/write data generating section that generates test write data and expected output value data according to the signals; and selects and outputs either the address signal from the output terminal of the address input buffer circuit or the internal address signal. a first selector that selects which one of the write data and the test write data from the output terminal of the write data buffer circuit; A memory section that writes data from the second selector to the address specified by the address signal and reads out the data stored at this address, and compares the data read from this memory section with the data of the expected output value. and a comparison circuit that outputs a test result signal, and operations of each part including selection control of the first and second selectors according to an external control signal, control of writing and reading data in the memory section, and control of generation of the clock signal. and control means for controlling the test timing signal and outputting a test timing signal to the outside.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention.

This embodiment includes an address input buffer circuit 1 that inputs an address signal AD from the outside and transmits it to an output terminal, a write data buffer circuit 2 that inputs write data DT from the outside and transmits it to the output terminal, and an external control signal CN from
a ring oscillator 61 whose oscillation frequency can be changed by T;
The clock signal C is generated by the output signal of this ring oscillator 61.
A clock signal generating section 62 that generates the clock signal ADI, an address data generating section 63 that generates the internal address signal ADI for testing according to the clock signal, and generating write data DTW for testing and data DTC of the expected output value according to the clock signal CK. a first selector 4A that selects and outputs either the address signal from the output end of the address input buffer circuit 1 or the internal address signal ADI, and the write data buffer circuit 2. A second selector 4B selects either the write data from the output terminal or the test write data DTW, and the second selector 4B selects the address specified by the address signal from the first selector 4A. A memory unit 5 writes data from and reads data stored at this address, and compares the data read from this memory unit 5 with the expected output value data DTC and outputs a test result signal TR. operation control of the address input buffer circuit 1 and the write data buffer circuit 2 according to the external control signal CNT and the internal control signal CNTl from the control signal generator, and the selector 4A.
.
The control signal generating section 65 controls the operation of the comparator circuit 66, and outputs a test end signal TE, one of the test timing signals, to the outside. In addition, the output of the ring oscillator 61 is the monitor signal ○
It is output to the outside as SM.

In this embodiment, the ring oscillator 61. Clock signal generator 62. Address data generation section 63, read/write data generation section 64. Control signal generator 65. and comparison circuit 6
6 constitutes a test circuit 6, and the control circuit 3 and control signal generating section 65 constitute a control means.

Next, the operation of this embodiment will be explained.

During normal read/write operations, address signals to the memory section 5 are sent from the outside to the address input buffer circuit 1 and the selector 4.
Similarly, write data is input from the outside via the write data buffer circuit 2 and selector 4B, and this data is written during a write operation, and is stored from this address during a read operation. The data that is being read out is read out. These operation timings and control of reading and writing are performed by the control circuit 3 using an external control signal CNT.

At the time of testing, the control signal CNT sets the test mode, and the control circuit 3 switches the selectors 4A4B to the test circuit 6.
The operation timing and operation control of each section are performed by the control signal generating section 65.

Therefore, the operation test of the memory section 5 is performed at high speed, and the test result is the test result signal TR outputted from the comparator circuit 66 at the time when the test end signal TE is issued.
It is determined by observing.

The ring oscillator 61 has a variable length, and the control signal CN
The number of stages of the ring oscillator 61 can be selectively switched by T, thereby changing the basic cycle during testing and selecting the test cycle. This ring oscillator 61
By changing the oscillation frequency of the oscillation frequency, the main purpose of measuring the gate delay is performed using the monitor signal O3M, and the control signal CNT is used to control the test cycle so as to obtain the desired test cycle.

Further, the comparison circuit 66 starts a comparison operation by a signal instructing to start judgment outputted from the control signal generating section 65, and the output of the signal instructing to start judgment is outputted from the memory when the internal address signal ADI is output. It is necessary to delay the access time by the access time of the control signal generator 65, and it is possible to measure the access time by changing the delay amount of a variable delay circuit provided in the control signal generator 65. .

Further, the address data generating section 63. By changing the configurations of the read/write data generating section 64 and the control signal generating section 65, it is possible to change the test pattern.

FIG. 2 is a block diagram showing a second embodiment of the invention.

This embodiment is based on the address input buffer circuit 1 in the first embodiment. Selector 4A and address data generator 6
3 are integrated to form an address output circuit 7, so that some of the circuit elements are shared with each other, and read data from the memory section 5 is outputted via a read output buffer circuit 8. , there is an advantage that the number of circuit elements can be reduced.

Furthermore, by outputting the output of the memory section 5 via the read buffer circuit 8, when the memory section 5 has a plurality of output bits, there is no skew between the bits of data output to the outside, and furthermore, the memory Since the access time of the section 5 can be determined by the clock input of the address input buffer section 72 and the read output buffer circuit 8, the access time can be determined simply by changing the oscillation frequency of the ring oscillator 61. Oscillator 61
The access time could not be determined without changing both the delay time of the signal that instructs the comparator circuit 66 of the control signal generator 65 to start the determination,
In the case of 5A, it is sufficient to use a signal that instructs the start of determination with a certain delay time from the clock input of the readout output buffer circuit 8, which has the advantage that the circuit can be simplified.

FIG. 3 (consisting of Part 1 and Part 2, hereinafter simply referred to as FIG. 3) is a circuit diagram showing part of the address output circuit 7 and test circuit 6A of this embodiment, and includes an ECL that generates a test pattern rMARcHj. shows a logic circuit,
For the sake of explanation, an example is shown in which the address signal input is 3 bits.

A portion centered around the flip-flops FFAl-FFA3 corresponds to the address output circuit 7, and an address input buffer section 72 and an address data generation section 71 are shared with the flip-flops FFAl-FFA3.

In this circuit, during testing, the shift mode switching signal SFT of the control signal CNT is set to "°1", the outputs of all flip-flops are set to "0" by the scan data input SI○, and the address signal AD (AO ~A2) is set to “1” and the test mode switching signal TES is input.
By setting T MODE to "i", the address output AD will be output in the test cycle in accordance with the clock signal CK.
○, write data DTW, output expected value data 9C1
Reading ratio/writing switching signal RWC, test end signal TE
This outputs the following.

When this circuit is used, the number of gates can be reduced by one flip-flop and two AND-NAND gates used as selectors per address bit.

Incidentally, the internal circuit of the EX○R gate used in the circuit shown in FIG. 3 and the input/output terminal names of the flip-flop FFCl are shown in FIGS. 4(a) and 4(b).

〔Effect of the invention〕

As explained above, the present invention provides a ring oscillator whose oscillation frequency can be controlled externally, generates a clock signal from the output of this oscillator, and generates an address signal for testing and data for writing according to this tarlock signal. By testing the writing and reading of the memory section and outputting the timing signal for the test to the outside, high-speed testing can be performed without using external test equipment, and the access time of the memory section etc. The effect is that it can be easily measured.

[Brief explanation of drawings]

1 and 2 are block diagrams showing the first and second embodiments of the present invention, respectively, and FIG. 3 shows part of the address output circuit and test circuit of the embodiment shown in FIG. 2. The circuit diagram, FIGS. 4(a) and (b), is a schematic diagram showing the EX-OR gate circuit diagram and the input/output terminal names of the flip-flop used in the circuit shown in FIG. 3, respectively, and FIG. 5 is a schematic diagram showing the input and output terminal names of the flip-flop. FIG. 1 is a block diagram showing an example of a conventional semiconductor memory. DESCRIPTION OF SYMBOLS 1... Address input buffer circuit, 2... Write data buffer circuit, 3, 3A, 3B... Control circuit,
4^+4B...Selector, 5...Memory section, 6,6
A...Test circuit, 7...Address output circuit, 8.
...Read output buffer circuit, 61...Ring oscillator, 62...Clock signal generation section, 63...Address data generation section, 64...Read/write data generation section, 65
゜65A...Control signal generation section, 66...Comparison circuit,
71...Address data generation section, 72...Address input buffer section, EOR1 to EOR3...EX-OR
Gate, FFAl~FFA6. FFBI, FFCl...
·flip flop.

Claims (1)

[Claims] 1. An address input buffer circuit that inputs an address signal from the outside and transmits it to the output terminal; a write data buffer circuit that inputs write data from the outside and transmits it to the output terminal; a ring oscillator whose oscillation frequency is changed by a signal from the ring oscillator; a clock signal generation section for generating a clock signal from the output signal of the ring oscillator; an address data generation section for generating an internal address signal for testing according to the clock signal; a read/write data generator that generates test write data and output expected value data according to a clock signal; and selects one of an address signal from an output terminal of the address input buffer circuit and the internal address signal; a first selector for outputting; a second selector for selecting one of the write data from the output terminal of the write data buffer circuit and the test write data;
a memory section that writes data from the second selector to an address specified by an address signal from the selector and reads out the data stored at this address; a comparison circuit that compares data and outputs a test result signal; controls selection of the first and second selectors according to an external control signal; controls writing and reading data in the memory section; controls generation of the clock signal; What is claimed is: 1. A semiconductor memory comprising: control means for controlling the operations of various parts including the above, and for outputting a test timing signal to the outside. 2. The semiconductor memory according to claim 1, wherein the address input buffer circuit, the address data generation section, and the first selector are integrated as an address output circuit.