KR20010002740A - Apparatus having memory for simplifing data interface - Google Patents

Abstract

PURPOSE: An apparatus for building a memory therein is provided to shift one-bit internal test data to generate n-bit internal test data so as to reduce circuit sizes, and to shorten a path through which data generated in a logic circuit is transmitted to a memory, so as to perform a high speed operation. CONSTITUTION: A memory(108) stores data. A built-in self test(BIST) circuit generates one-bit test data. A logic circuit(100) controls write/read operations of the memory(108), and generates n-bit write data for being written in the memory(108). A data interface(110) responds to a first/a second selection signals to receive one-bit internal test data generated in the BIST circuit(102), and shifts the one-bit internal test data n times, then generates n-bit internal test data, or receives n-bit write data generated in the logic circuit(100). The data interface(110) transmits the received n-bit write data to the memory(108) or receives n-bit external test data from an exterior, then transmits the n-bit external test data to the memory(108).

Description

Apparatus having memory for simplifing data interface

The present invention relates to a device with a built-in memory, and more particularly, to a device with a built-in memory to simplify the interface of data input to the memory.

Hereinafter, a device incorporating a memory according to the prior art will be described with reference to the accompanying drawings.

1 is a schematic block diagram illustrating a data interface of a memory in a device having a memory according to the related art, including a logic circuit 10, a built-in self test (BIST) circuit 12, and a selector 18. And a device 22 incorporating a memory including a memory 20, an external test data generator 14, and a mode controller 16 are shown.

Referring to FIG. 1, the logic circuit unit 10 is a block that is merged with the memory 20 to control the memory 20 and controls a write / read operation of the memory 20. Here, LDIN0 to LDINn represent n-bit write data generated in the logic circuit section 10. The BIST circuit unit 12 is a block for generating the test data of n bits (BDIN0 to BDINn) by the device incorporating the memory 22 when the device incorporating the memory 22 is in the test mode. That is, as shown in FIG. 1, the BIST circuit unit 12 is a block included in the device 22 having a built-in memory. When the memory device is tested, the BIST circuit unit 12 stores test data in the device 22 having the built-in memory. Allow it to occur. On the other hand, the external test data generator 14 refers to test equipment that is accessed from the outside of the device having the memory and generally tests the device 22 having the memory. The mode control unit 16 generates the first and second selection signals SEL1 and SEL2 for controlling the mode of the device 22 incorporating a memory. The selector 18 receives n bits of data generated from the logic circuit unit 10, the BIST circuit unit 12, and the external test data generator 16, respectively, and selects the first selection signal SEL1 and the second control signal SEL2. In response to the Here, the first and second selection signals SEL1 and SEL2 are signals indicating whether the device 22 incorporating the memory is in the normal mode or the test mode.

For example, when the first control signal SEL1 is at the "high" logic level, the device incorporating the memory is a normal mode, and the selector 18 selects n bits of data LDIN0 to n generated by the logic circuit unit 10. Output to the memory 20. On the other hand, when the first control signal SEL1 is at the "low" logic level, the device 22 incorporating the memory enters the test mode. At this time, when the second control signal SEL2 is at the "high" logic level, the device 22 incorporating the memory is n-bit data MIDN0 to n generated by the external test equipment, that is, the external test data generator 16. ) Is output to the memory 20. On the other hand, when the second control signal SEL2 is at the "low" logic level, the selector 18 selects and outputs n bits of data BDIN0 to n generated by the BIST circuit unit 12.

In the case of a device incorporating a memory according to the related art as described above, as the number of bits increases, the size of the selector increases, and the number of bits output from the BIST circuit 12 also increases, thereby increasing the BIST circuit 12. As a result, a problem arises in that the area of the entire chip of the device incorporating the memory becomes large, thereby reducing the operation speed.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide an apparatus in which a memory having a simple data interface capable of simplifying a circuit configuration and reducing a chip size by simplifying a data interface of a memory.

1 is a schematic block diagram illustrating a data interface of a memory in a device having a memory according to the related art.

2 is a diagram illustrating an embodiment of a device having a simple data interface according to the present invention.

3 is a circuit diagram showing in detail the data interface 110 according to the present invention shown in FIG.

In order to achieve the above object, a device having a memory for simplifying the data interface according to the present invention includes a memory for storing data, a BIST circuit portion for generating 1-bit test data, and a write / read operation of the memory. In response to the logic circuit portion generating n-bit write data to be written to the memory and the first and second selection signals, the 1-bit internal test data generated by the BIST circuit portion is received and shifted n times to perform n-bit internal test. And a data interface for generating data, receiving n-bit write data generated by the logic circuit unit, and transferring the received data to the memory, or receiving n-bit external test data from the outside and transferring the data to the memory. It is done.

Hereinafter, with reference to the accompanying drawings, a configuration of a device having a simple data interface incorporating a memory and its data interface operation according to the present invention will be described.

2 is a diagram illustrating an embodiment of a device having a simple data interface according to the present invention. The apparatus shown in FIG. 2 is shown including a device 118 incorporating a memory according to the present invention, a mode controller 104 and an external test data generator 106. Here, the device incorporating a memory according to the present invention includes a logic circuit unit 100, a BIST circuit unit 102, a data interface 110, and a memory 108. In addition, the data interface 110 includes first to n th interfaces 112 to 116.

The description of the logic circuit unit 100, the mode control unit 104, and the external test data generation unit 106 illustrated in FIG. 2 is described with reference to the logic circuit unit 10, the mode control unit 16 and the external test data generation illustrated in FIG. 1. Since the operations of each section 14 are the same, the description thereof is omitted here.

The BIST circuit unit 102 shown in FIG. 2 is a block for generating internal test data. In the past, the BIST circuit unit 102 generates n-bit internal test data. However, in the present invention, only one bit of test data is generated.

In response to the first and second selection signals SEL1 and SEL2, the data interface 110 receives one-bit internal test data BDIN generated by the BIST circuit unit 102 and shifts n times, respectively, The data is generated as n bits of internal test data and the generated n bits of internal test data are transferred to the memory. In addition, in response to the first and second selection signals SEL1 and SEL2, the n-bit write data LDIN0 to n generated by the logic circuit unit 100 are received and transferred to the memory, or n-bit from the outside. Accept external test data from and pass it to memory. The memory 108 stores n bits of data DIN0 to n generated in the data interface 110 in response to the first and second selection signals SEL1 and SEL2.

In more detail, the data interface 110 is composed of the first to n th interfaces 112 to 116, and the shifters are connected in series to receive 1-bit internal test data BDIN and perform n shifts. Generates n bits of internal test data. As described above, in the case of the device incorporating the memory according to the present invention, even if the number of bits for interfacing with the memory increases, the BIST circuit unit 102 only needs to generate one bit of test data, and thus the conventional BIST generates n bits of internal test data. Compared with the circuit part, the size of the circuit can be greatly reduced.

3 is a circuit diagram showing in detail the data interface 110 according to the present invention shown in FIG. Data interface 110 according to the present invention is composed of n interfaces, each of the n interface is a first selector (128, 138), flip-flop (126, 136), a second selector (124, 234) and And buffers 122 and 132. 3 shows the first and second interfaces 120 and 130.

First, the first selector 128 of the first interface 120 shown in FIG. 3 inputs the least significant bit BDIN0 of one bit of internal test data BDIN and n bits of external test data MDIN0 to n. In response to the first selection signal SEL1, one data of the input data is selected and output. The flip-flop 126 shifts and outputs data generated from the first selector 128 in response to the clock signal. The second selector 124 inputs the least significant bit LDIN0 among the data generated by the flip-flop 126 and the n-bit write data LDIN0 to n generated by the logic circuit unit 100, and the second select signal SEL2. In response to), one of the input data is selected and output. The buffer 122 buffers the data output from the second selector 124 and generates data DIN0 so that the buffered data is written to the memory 108.

In addition, the first selector 138 of the second interface 130 shown in FIG. 3 selects the second bit BDIN1 of the data generated from the flip-flop 126 and the n-bit external test data MDIN0 to n. In response to the first selection signal SEL1, one data of the input data is selected and output. The flip-flop 136 shifts the data generated from the first selector 138 in response to the clock signal CK and outputs the second selector 134 to the first selector of the third interface although not shown. The second selector 134 inputs the second bit LDIN1 of the data generated by the flip-flop 136 and the n-bit write data LDIN0 to n generated by the logic circuit unit 100, and the second select signal ( In response to SEL2), one of the input data is selected and output. The buffer 132 buffers the data output from the second selector 134 and generates write data DIN1 so that the buffered data is written to the memory 108.

Although not shown in FIG. 3, as described above, the first to n th interfaces 112 to 116 illustrated in FIG. 2 are connected in series, and the 1-bit internal test data (1) is flipped by the flip-flops 126 and 136. BDIN) is shifted to generate n bits of internal test data.

As a result, as described above, in the case of the device having the memory according to the present invention, the size of the BIST circuit can be reduced, and as shown in FIG. 3, the normal operation, that is, the n-bit write data generated in the logic circuit unit 100, is illustrated. When (LDIN0 to n) is written to the memory 108, the data transfer path is shortened as compared with the conventional one, which secures a set-up margin of the memory buffer which is likely to be insufficient in high frequency operation and operates at high speed It is advantageous to

As described above, since the device having a built-in memory for simplifying the data interface according to the present invention generates n-bit internal test data by shifting internal test data of 1 bit, the size of the circuit is greatly reduced as compared with the prior art, and it operates normally. The path from which data generated at the time logic circuit part is transferred to the memory is shortened, which is advantageous in high speed operation.

Claims (3)

A memory for storing data; A BIST circuit unit generating one bit of test data; A logic circuit section for controlling write / read operations of the memory and generating n bits of write data to be written to the memory; And In response to the first and second selection signals, one bit of internal test data generated by the BIST circuit unit is received and shifted n times to generate n bits of internal test data, or n bits of And a data interface for accepting write data to the memory or receiving n-bit external test data from the outside and transferring the test data to the memory. The data interface of claim 1, wherein the data interface comprises first to nth interfaces, The first to n th interfaces are connected in series to input and shift the one-bit internal test data to generate n-bit internal test data, and to receive the n-bit external test data and the n-bit write data, respectively. And outputting the n-bit internal test data, the n-bit external test data, or the n-bit write data in response to the first selection signal and the second selection signal. Built-in device. The method of claim 2, wherein the first interface A first selector configured to input a least significant bit of the internal test data of the 1 bit and the external test data of the n bit, and select and output one data of the input data in response to the first selection signal; A first flip-flop for shifting and outputting data generated from the first selector in response to a clock signal; A second selector for inputting the least significant bit of the data generated in the first flip-flop and the n-bit write data, and selecting and outputting one of the input data in response to the second selection signal; And A first buffer configured to buffer data output from the second selector and to write the buffered data to the memory, The nth interface is Receiving the most significant bit of the n-bit external test data and the data shifted in the (n-1) interface as the (n-1) th data of the n-bit internal test data, and in response to the first selection signal, A third selector for selecting and outputting one of the received data; A second flip-flop generated by shifting data generated by the third selector in response to the clock signal; A fourth selector which receives the most significant bit of the n-bit write data and the data generated from the second flip-flop, and selects and outputs one of the received data in response to the second selection signal; And And a second buffer for buffering data generated by the fourth selector and writing the buffered data to the memory.