JPH0482057A - Method and device for data transmission - Google Patents

Abstract

PURPOSE:To satisfactorily transmit plural control information by transmitting a bit synchronizing signal for a period longer than the data length of a prescribed number of bits in advance of data which includes a start bit and consists of the prescribed number of bits. CONSTITUTION:The bit synchronizing signal is transmitted for a period longer than the time length of a data part consisting of the prescribed number of bits in advance of this data part which includes the start bit and consists of the prescribed number of bits. In this case, a clock signal part preceding the data part has a period 1T and 50% duty cycle and consists of a clock signal functioning as the bit synchronizing signal and has such length that data for control signal of the data part can be surely demodulated with the clock signal on the reception side. Thus, plural control information are satisfactorily transmitted.

Description

[Detailed description of the invention] [Industrial application field]

The present invention relates to a data transmission method and apparatus.

[Conventional technology]

It is well known that in recent years, digital VTRs and high-definition VTRs based on various standards have been developed and commercialized. Since the above-mentioned various VTRs must handle wideband signals, for example, for RF replay, a preamplifier is installed on a rotating cylinder to amplify the output signal of the playback head in order to make it wideband and low noise. In addition, in order to provide a VTR with a simultaneous recording and reproducing function, a recording amplifier is sometimes mounted on a rotating cylinder. When the recording amplifier is mounted on a rotating cylinder as described above, the signal level of the recording signal transmitted by the rotating transformer is kept low, so the cross between the channels of the single rotating transformer is used. The amount of interference exerted on reproduction system signals can be reduced. On the other hand, in order to miniaturize equipment, it is better to have fewer channels in the rotary transformer used to transmit playback and recording signals, and for this reason, for example, they are installed at 180-degree symmetrical positions on the rotary cylinder. The output signals from the preamplifiers that amplify the output signals of the two playback heads may be switched on the rotating cylinder and transmitted by one rotating transformer, or alternatively, the output signals may be switched on the rotating cylinder and transmitted by one rotating transformer, or they may be installed at 80 degrees symmetrical positions on the rotating cylinder, for example. Conventionally, the recording amplifier that supplies recording signals to the two recording heads shown in FIG. It is coming. In addition, as for the signal switching operation and other circuit operations on the rotary cylinder side as described above, for example, the on/off operation of the recording amplifier within one track of the magnetic tape during insert editing, the side panel operation of the output amplitude of the recording amplifier, etc. It is conceivable to have the switching control performed on the rotary cylinder side, but in order to have the signal switching control for the component provided on the rotary cylinder side performed on the rotary cylinder side as described above, it is necessary to perform the switching control described above. It is necessary to transmit control signals for operations etc. to the rotating cylinder side. And, as a conventional technique for transmitting control signals for switching control operations etc. from the outside to the rotating cylinder side. ↓One channel of a one-turn transformer is used for the oscillator output whose output voltage changes depending on the head switching signal. The voltage is transmitted to the rotating cylinder side, and the rotating cylinder side determines the change in voltage and switches the head. '■ The output of the generator whose frequency changes according to the head switching signal is transmitted to the rotating cylinder side using one channel of the one-turn transformer. The oscillation frequency is a frequency at which the transmission characteristics of the rotary transformer are frequency dependent. ■The output of the pulse generator, which generates a different number of pulses depending on the head switching signal, is transmitted to the rotating cylinder side using one channel of the rotating transformer, and the number of pulses is counted on the rotating cylinder side. Make sure to switch. ■Various signal transmission methods such as 0 that switch between recording and playback without performing the above-mentioned means such as ■ to t■ during recording are disclosed in, for example, Japanese Patent Application Laid-Open No. 60-5406. .

[Problem to be solved by the invention]

However, the above-mentioned conventional technology does not work well when there are a large number of components to be controlled, such as a reproducing head amplifier, a recording amplifier, etc. mounted on a rotating cylinder, or when complex control is to be performed. The problem is that it is not possible to exercise proper control. [Means for solving the problem: The present invention provides a bit synchronization signal for a period longer than the data length of the predetermined number of bits, preceding the data of a predetermined number of bits including a start bit. The data of the predetermined number of bits is restored based on the delayed bit synchronization signal obtained by delaying the bit synchronization signal that has been transmitted for a period longer than the data length of the predetermined number of bits. In the data transmission method and the magnetic recording/reproducing device in which the signal transmission to the component provided on the rotating cylinder side is performed using a rotary transformer, the data transmission method includes a start bit. A signal consisting of control data of a predetermined number of bits, and a bit synchronization signal that precedes the control data of the predetermined number of bits and has a period longer than the length of the control data of the predetermined number of bits. means for transmitting the signal to the rotating cylinder via a rotary transformer as a signal in the form of a signal with a DC component of zero;
Regarding the signal transmitted to the rotating cylinder side via the rotary transformer, a delayed bit synchronization signal is obtained by delaying the bit synchronization signal that precedes the control data of a predetermined number of bits that includes a start hit. means and
The present invention provides a data transmission device comprising means for demodulating control data of a predetermined number of bits using the delayed bit synchronization signal described above to obtain a control signal.

[Effect]

A predetermined number of bits of control data including a start bit, and a period that precedes the predetermined number of bits of control data and is longer than the length of the predetermined number of bits of control data. A signal consisting of a bit synchronization signal and a bit synchronization signal over
Transmitted to the rotating cylinder side via a rotary transformer. A delayed bit synchronization signal is generated by delaying the bit synchronization signal that precedes a predetermined number of bits of control data that includes a start bit in the signal transmitted to the rotating cylinder via a rotary transformer. let The control data of a predetermined number of bits is demodulated using the above-mentioned delayed bit synchronization signal to obtain a control signal to perform a control operation of the controlled member on the rotary cylinder side.

【Example】

Hereinafter, specific details of the data transmission method and apparatus of the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 shows an example in which the data transmission method of the present invention is applied to the transmission of control signals in a magnetic recording/reproducing device in which the transmission of signals to components provided on the rotating cylinder side is performed using a rotary transformer. 1 is a block diagram of an example configuration of a data transmission device configured to perform
Further, FIGS. 2 and 3 are signal waveform diagrams for explaining the configuration principle and operation principle of the data transmission method of the present invention. In Fig. 1, 1 is a control signal input terminal provided on the display side of the magnetic recording/reproducing device, 2 is a buffer amplifier, 3 is a rotary transformer, 4 is a comparator, and 5 is a shift register (5 bit shift register). register), 6 is a delay circuit, 7
, 8 is an AND circuit, 9 is a D-type flip-flop, 10 is an inverter, 11 is a decoder, 12 is a counter (3-bit counter), and 13 is a set/reset flip-flop. FIG. 2 is a diagram showing an example of signal arrangement on the time axis in the data transmission method of the present invention. In the data transmission method of the present invention, as illustrated in FIG. A bit synchronization signal is transmitted for a period longer than the time length of the data section of the predetermined number of bits, preceding the data section of the predetermined number of bits that includes bits. FIG. 2(b) is a signal waveform diagram showing an enlarged part of the signal train illustrated in FIG. 2(a), and FIG. This is a signal waveform diagram of the signal shown in No. i)) after being waveform-shaped after passing through an AC coupling circuit, and the signal shown in No. 2 (b) and the third
It may be considered that this is the same signal waveform diagram as shown in (a) of the figure. The structure of the data portion of the signal illustrated in the signal waveform diagrams of FIG. 2(b) and FIG. It is shown as a configuration having additional information for configuring the data section as a state 1 with zero DC component regardless of the content of the data, and is also shown in FIG. The illustrated data transmission device has a configuration in which a predetermined control signal can be demodulated using data in the configuration illustrated in FIG. 2 (b) and FIG. 3 (a). be. In FIG. 2(b), the clock signal section preceding the data section is composed of a clock signal having a period of -4T and a duty cycle of 50% and functioning as a bit synchronization signal, The length is such that the data for the control signal of the data section can be reliably demodulated using the clock signal on the receiving side. In addition, the data section has the star 5 bit Ssb synchronized at the beginning, and is m times the period IT of the clock signal mentioned above (however, 1 m
contains n-bit data indicated by a high level state and a low level state during the period (m≧1, an integer), and also sets the DC component to zero during the period of the data part. For example, the data portion of the signal shown in FIG. 2(b) includes the start bit Ssb of the IT high level period at the beginning. , then 0, 1 . . . by the low level period of IT and the high level period of 2T. A period representing 3-bit control data such as i follows, followed by a 2T low level period and an IT
The additional information period consists of a high level period of IT and a low level period of IT. In Figure 1, 1 point i! The i-line frame FD indicates the component part F D % on the fixed part side of the magnetic recording/reproducing device, and 1
The point IIAwA frame RD indicates a component RD which is a rotary cylinder side cylinder row, and the transmission of signals between the same parts is carried out by a rotary transformer (RT) 3. The signal exemplified in FIG.
A) Rotary transformer 3 after being amplified by 2
The signal is transmitted to the components on the rotating cylinder side via , and is supplied to the non-inverting input terminal of the comparator (COMP) 4 . The comparator 4 compares the input signal supplied to its non-inverting input terminal with the reference voltage supplied to its inverting input terminal, and produces a signal Sa shown in FIG. 3(a). output, and send it to shift register (SR) 5 and delay circuit (
DL)6. The above-mentioned shift register 5 has its configuration determined depending on the number of bits of control data contained in the data section supplied thereto.
For example, the data part of one word supplied to
As shown in the data section of No. 2, which is an example,
Start focus SsD of high level period of first picture 1T
In front of the star (bit Ssb), there is a low-level period of <IT and two high-level periods, and thus a period in which the control data represents control data of every three pins such as 0, x, and l. In such a case, a 5-bit shift register 5 (generally expressed, the number of data bits n + 2 bits) is used as the shift register 5 used. As circuit 6, start bit S
It consists of sb, 3-bit data for control signals, and additional information for configuring the data part as one in which the DC component is zero, regardless of the content of the 3-bit data. The delay time T (K+3/4) is equal to or longer than the longest period indicated by the data portion of the signal, and shorter than the period of the clock signal portion preceding the data portion (where T is the clock signal portion). This is the period of the signal].The delay circuit N6 to which the signal Sa shown in FIG. The signal sb ((b) in FIG. 3) is supplied to the shift register 5 as a clock signal, and the signal sb is supplied to the inverter (IN
V) After reversing the polarity with L○, the counter (C
T) 12 (supposed to be a 3-bit counter in the example shown in the first figure) is also supplied as a clock signal. As described above, the shift register 5 to which the signal Sa output from the comparator 4 is supplied as an input signal shifts the input signal Sa using the signal sb output from the delay circuit 6 as a clock signal. By the way, the signal Sa outputted from the comparator 4 and inputted to the shift register 5 is a portion of the sequential clock signal in the clock signal portion arranged in advance of the data portion, and is also outputted from the delay circuit 6. signal sb
In the case where the sequential clock signals in the clock signal portion arranged in advance of the data portion are delayed signal portions, all of the information read into the shift register 5 will be in a low level state. That is, used as a clock signal in the above case = tC
The state of the signal level of the input signal Sa to the shift register 5 at the rising timing of the signal Sb is at the rising timing of the signal Sb, which is out of phase by 3/4 with respect to the signal Sa whose duty cycle is 50%. Since the input signal S is at low level, the clock signal section is at low level.
Shift register 5 in the state where it is input as a
The signal levels of the respective outputs Ql, Q2, . . . , Q5 sequentially become low level. In addition, the 3-bit counter 12, to which a signal obtained by inverting the polarity of the output signal sb of the delay circuit 6 described above by the inverter 10, is given one after another as a clock signal, is connected to the clock signal section which is arranged in advance of the 2-data section. The output signal sb from the delay circuit 6, which outputs a signal obtained by delaying sequential clock signals, is continuously supplied as a clock signal to generate a carry signal, which is sent to the set-reset flip-flop. (SRFF) 13
By being applied to the set terminal S of the set reset flip-flop 13, the high level Q output Sd (see (d) in FIG. 3) of the set reset flip-flop 13 is supplied to the AND circuits 7 and 8. That is, if the output signal Sa from the comparator 114 is a continuous signal of sequential clock signals in the clock signal section arranged in advance of the data section, all outputs of the shift register 5 are set to a low level state. At the same time, the high level Q output Sd of the set/reset flop prop 13 is supplied to the AND circuit 7.8. When the signal content of the output signal Sa from the comparator 4 is transferred to the signal of the data section, data of a predetermined number of bits including a start bit is sequentially input to the shift register 5. The data part of the signal Sa illustrated in FIG. , L, l continues, and then a period of 2T
Since the additional information period consisting of a low level period of , a high level period of IT, and a low level period of IT continues, the shift register 5 is shown as an example in FIG. 3(a). When such a data section is input manually, the high level state corresponding to the start pitch -5sb is changed to the Q1 output of the shift register 5 every time a clock signal is sequentially applied.
The output is shifted sequentially from Q2 output to Q3 output to Q4 output to Q5 output. By the way, the AND circuit 7 outputs the Q output Sd signal of the set/reset flip-flop 13 and the Q4 signal of the shift register 5.
When the output and the signal sb output from the delay circuit %6 are both at high level, a high level clock pulse is sent to the output of the 3-bit D-type flip-flop circuit 'j.
lI9, the state of the Q1 to Q3 outputs in the shift register 5 at that point is sent to the D-type flip-flop 9.
to be memorized. The 3-bit information stored in the D-type flip-flop 9 as described above is 3-bit control data following the start bit Ssb indicating the beginning position of the data section.
The 3-bit control data stored in the type flip-flop 9 is decoded into a control signal by a decoder 11 and applied to the controlled circuit. Next, when a high level state corresponding to the start bit Ssb described above appears at the Q5 output of the shift register 5, a reset signal is applied from the AND circuit 8 to the counter 12, and the counter 12 is reset. At the same time, the Q5 output of the shift register 5 described above is supplied to the set-reset flip-flop 13 as a reset signal, so the set-reset flip-flop 13
will also be reset. Until now, (b) in Figures 1 and 2 and (b) in Figure 3 have been used.
The embodiment described with reference to a) has a 1-bit start bit Ssb followed by 3-bit control data, so that data transmission is performed in a state that does not include a DC component. The 3-bit control data is transmitted using a data section in which additional bits for the data are added as necessary, and the receiving side decodes the 3-bit control data to perform eight types of control. In this embodiment, a 5-bit shift register, a 3-bit D-type flip-flop 9, and a 3-bit counter 12 are used to control the 3-bit control in the data section. data is reliably stored in the 3-bit D-type flip-flop 9, and it is transferred to the decoder 1.
However, it is natural that more types of control can be realized by increasing the number of bits of control data, but as the number of bits of control data increases, , the above-mentioned shift register 5.・Of course, the number of bits of the D-type flip-flop 9, counter 12, etc. should be changed,
Accordingly, the length of the clock signal section that should be placed prior to the data section and the amount of delay caused by the delay circuit 6 should also be set so that the predetermined operations of each component in the receiving section can be performed well. It is something. [Effects of the Invention] As is clear from the detailed explanation above, the present invention provides the above-mentioned data having a predetermined number of bits, which precedes the data having a predetermined number of bits and includes a start bit. Based on the delayed bit synchronization signal obtained by transmitting the bit synchronization signal for a period longer than the data length, and delaying the bit synchronization signal that has been transmitted for a period longer than the data length of the predetermined number of bits, , a data transmission method that demodulates data of a predetermined number of bits, control data of a predetermined number of bits including a start bit, and control data of a predetermined number of bits as described above. A signal consisting of a preceding bit synchronization signal having a period longer than the control data length of the predetermined number of bits described above is sent to the rotating cylinder side via a rotary transformer as a signal in the form of a signal with zero DC component. The bit cycle signal in the signal transmitted to the rotating cylinder side via the rotary S lance is delayed to generate a delayed bit synchronization signal, and the delayed bit synchronization signal is used to control a predetermined number of bits. Since this device demodulates control data to obtain a control signal and performs a control operation on a controlled member on the rotary cylinder side, the present invention can transmit the If& data of control 4 through a small number of transmission paths. Also, by transmitting the clock signal used for demodulating the transmitted data in advance of the data, and then delaying it and using it as the clock signal,
A plurality of pieces of control information can be transmitted satisfactorily with a simple configuration, and the present invention can satisfactorily solve the problems of the conventional art described above.

[Brief explanation of the drawing]

FIG. 1 shows an example in which the data transmission method of the present invention is applied to the transmission of control signals in a magnetic recording/reproducing device in which the transmission of signals to components provided on the rotating cylinder side is performed using a rotary transformer. a block diagram of an example configuration of a data transmission device configured to perform
2 and 3 are signal waveform diagrams for explaining the configuration principle and operating principle of the data transmission method of the present invention.
- Input terminal for control signals provided on the demarcation section side of the magnetic recording/reproducing device, 2... Sofa increaser. 3... Rotary transformer, 4... Comparator, 5... Shift register, 6... Delay circuit, 7, 8... AND circuit, 9... D-type flip-flop, 10... Inverter, 11...・Decoder, 12... Counter, ', 3・
・・Set-reset flip-flop,

Claims (1)

[Claims] 1. A bit synchronization signal is transmitted for a period longer than the data length of the predetermined number of bits, preceding the data of a predetermined number of bits including a start bit. Data transmission method 2 is to delay a bit synchronization signal that has been transmitted for a period longer than the data length of the predetermined number of bits, preceding the data of a predetermined number of bits including a start bit. A data transmission method 3 in which data of the predetermined number of bits described above is demodulated based on the delayed bit synchronization signal obtained by using a rotary transformer to transmit the signal to the component provided on the rotating cylinder side. In a magnetic recording/reproducing apparatus which is designed to perform means for transmitting a signal consisting of a bit synchronization signal for a period longer than the control data length of the predetermined number of bits as a signal in the form of a signal with zero DC component to the rotating cylinder side via the rotary transformer; Regarding the signal transmitted to the rotating cylinder side via the rotary transformer, a delayed bit synchronization signal is obtained by delaying the bit synchronization signal that precedes a predetermined number of bits of control data including a start bit. and means for demodulating a predetermined number of bits of control data using the delayed bit synchronization signal to obtain a control signal.