USRE39832E1 - Optical recording disk capable of resynchronization in digital encoding and decoding - Google Patents
Optical recording disk capable of resynchronization in digital encoding and decoding Download PDFInfo
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- USRE39832E1 USRE39832E1 US10/137,488 US13748802A USRE39832E US RE39832 E1 USRE39832 E1 US RE39832E1 US 13748802 A US13748802 A US 13748802A US RE39832 E USRE39832 E US RE39832E
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
- H04L25/40—Transmitting circuits; Receiving circuits
- H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
- H04L25/4906—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using binary codes
- H04L25/4908—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using binary codes using mBnB codes
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/12—Formatting, e.g. arrangement of data block or words on the record carriers
- G11B20/1217—Formatting, e.g. arrangement of data block or words on the record carriers on discs
- G11B20/1251—Formatting, e.g. arrangement of data block or words on the record carriers on discs for continuous data, e.g. digitised analog information signals, pulse code modulated [PCM] data
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/14—Digital recording or reproducing using self-clocking codes
- G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
- G11B20/1423—Code representation depending on subsequent bits, e.g. delay modulation, double density code, Miller code
- G11B20/1426—Code representation depending on subsequent bits, e.g. delay modulation, double density code, Miller code conversion to or from block codes or representations thereof
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B27/00—Editing; Indexing; Addressing; Timing or synchronising; Monitoring; Measuring tape travel
- G11B27/10—Indexing; Addressing; Timing or synchronising; Measuring tape travel
- G11B27/19—Indexing; Addressing; Timing or synchronising; Measuring tape travel by using information detectable on the record carrier
- G11B27/28—Indexing; Addressing; Timing or synchronising; Measuring tape travel by using information detectable on the record carrier by using information signals recorded by the same method as the main recording
- G11B27/30—Indexing; Addressing; Timing or synchronising; Measuring tape travel by using information detectable on the record carrier by using information signals recorded by the same method as the main recording on the same track as the main recording
- G11B27/3027—Indexing; Addressing; Timing or synchronising; Measuring tape travel by using information detectable on the record carrier by using information signals recorded by the same method as the main recording on the same track as the main recording used signal is digitally coded
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
- H04L25/40—Transmitting circuits; Receiving circuits
- H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
- H04L25/4904—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using self-synchronising codes, e.g. split-phase codes
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/12—Formatting, e.g. arrangement of data block or words on the record carriers
- G11B2020/1264—Formatting, e.g. arrangement of data block or words on the record carriers wherein the formatting concerns a specific kind of data
- G11B2020/1265—Control data, system data or management information, i.e. data used to access or process user data
- G11B2020/1287—Synchronisation pattern, e.g. VCO fields
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B2220/00—Record carriers by type
- G11B2220/20—Disc-shaped record carriers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B2220/00—Record carriers by type
- G11B2220/20—Disc-shaped record carriers
- G11B2220/25—Disc-shaped record carriers characterised in that the disc is based on a specific recording technology
- G11B2220/2537—Optical discs
Definitions
- the reissue applications are a parent reissue application Ser. No. 09 / 295 , 376 and three divisional reissue applications, namely Ser. No. 10 / 137 , 488 ( the present application ) , Ser. Nos. 10 / 138 , 737 and 10 / 138 , 738 .
- This invention relates to a recording/reproducing apparatus which records and reproduces digital signals, and more particularly to the digital data encoding/decoding apparatus for optical disk apparatus which carries out mark edge recording by pit width modulation.
- the optical disk apparatus has attracted keen public attention as a digital information recording/reproducing apparatus with a large storage capacity and the ability to interchange media.
- the digital data is encoded for encoding in such a manner that it fits in the recording/reproducing channel characteristics determined by the optical head and optical recording media, and reproduced signals are data-detected to make binary-coded signals, from which decoding is carried out to obtain original digital data.
- encoding and decoding techniques to enable efficient digital recording and reproducing have been put into practical use as various digital data encoding/decoding apparatus.
- the code stream obtained by encoding the data with modulation having a proper rule is recorded.
- the clock signals which are clock components of the code stream are retrieved from the reproduced signals by utilizing the properties of the code stream imparted by the above-mentioned modulation.
- the recorded code stream is separated and the original digital data is obtained by decoding, which is the operation reverse to encoding.
- a (2, 7) code is used as the encoding system as found in the International Standard (ISO/IEC DIS 10089). Table 1 shows the conversion rule of the (2, 7) code.
- the (2, 7) code is an encoding system which converts 1-bit digital data to 2-bit codes, and is so called because of its characteristic that a “1” is separated by a minimum of two “0's” and a maximum of seven “0's” in the code stream after encoding an original digital data stream.
- This encoding rule is called (d, k) conversion rule because a “1” is separated by a minimum of d “0's” and a maximum of k “0's” in the code stream after encoding.
- decoding timing to the bits of the code stream and the data stream is to be properly provided when the original data stream is decoded from the reproduced code stream. Otherwise, such decoding timing failure does not keep the rule of the encoding system and will result in errors.
- Table 1 the 1-bit data must be made to correctly correspond with the 2-bit code.
- a specific code pattern called SYNC or RESYNC BYTE is inserted in the code stream after encoding to achieve bit synchronization at the time of decoding. In the above-mentioned international standard, for the RESYNC BYTE.
- This RESYNC BYTE is a pattern which cannot exist in any code stream after encoding for any data stream in the rule specified in Table 1, and a RESYNC BYTE will never be detected by mistake with other code data.
- This kind of method enables this bit synchronization by periodically arranging bit patterns, which can easily be identified, as a RESYNC BYTE to achieve bit synchronization in the encoded code streams as described in, for example, OPTICAL DATA FORMAT EMPLOYING RESYNCHRONIZABLE DATA SECTORS, U.S. Pat. No. 4,791,622 by D. W. Clay et al. and SYNC ENCODING SYSTEM FOR DATA SECTORS WRITTEN ON A STORAGE MEDIUM, U.S. Pat. No. 4,797,167 by M. J. O'Keeffe et al.
- This bit synchronization pattern is called a SYNC BYTE when it is used at the data head, and a RESYNC BYTE when used at the intermediate position.
- the SYNC BYTE decides the bit synchronization at the start of decoding, while the RESYNC BYTE periodically corrects deviation of a decoding bit to prevent propagation of decoding error after any defect occurs when clock reproduction failure occurs in the middle of data reproduction, and both frequently have the same patterns.
- the unit of the recording data amount must also be increased.
- the recording data unit is increased, there will be more possibility to cause failure to reproduce clocks during data reproduction due to the drop-out of reproduced signals arising from a defect of the media, and the system reliability will be lowered.
- the importance of the RESYNC BYTE has been further increased to suppress continuous occurrence of decoding errors in order to prevent disability in decoding all of the data after the clock reproduction failure occurs.
- MPR mark position recording
- PPM pit position modulation
- PWM pit width modulation
- MER mark edge recording
- the(2, 7) code has the superior capabilities, and the PPM recording system using this (2, 7) code has been adopted in the above-mentioned international standard, but as part of further improving the recording density, in the PWM recording, investigation has been made on systems such as a (1, 7) code.
- NRZI code is performed after a (2, 7) or (1, 7) code. The positional relationship between the mark formed in correspondence with the part in which “1” of the code stream obtained as above continues and the space other than this formed by “0” is used for recording information.
- the mark is formed by applying the comparatively high optical output to the medium and locally raising medium temperature, and has a problem that the positional relationship of mark edge deviates when the optical output deviates from the optimum value. That is, when the optical output is greater than the optimum value, the recorded mark generally becomes larger, and, on the contrary, when it is smaller, it becomes smaller, causing the power margin, the set margin for optical output in recording, to become smaller. In this way, the positional relationship between the mark initiation end and the finish end deviates from the optimum bit intervals of code data, resulting in higher possibility to cause decoding errors in achieving synchronization of data from reproduced signals for decoding.
- a specific pattern is given to the invalid data of the portion corresponding to RESYNC BYTES to operate an encoder, and in inserting RESYNC BYTES in the corresponding portion of the code stream after encoding, the present invention enables smooth connection in terms of code regularity.
- the above and other objects of the present invention are realized in the digital data encoding apparatus of the present invention that periodically inserts RESYNC BYTES comprising a bit compensation part, RESYNC detection part, and bit synchronization part into the code stream of the digital data encoded in accordance with the (d, k) conversion rule.
- the digital data encoding method and apparatus of the present invention has an encoding means to encode data input in accordance with the (d, k) conversion rule and RESYNC BYTES adding means which periodically generates RESYNC BYTES comprising a bit compensation part, RESYNC detection parts, and a synchronization part. Furthermore, it is provided with an encoding means to perform NRZI encoding on the (d, k) encoded code and RESYNC BYTES.
- the digital data decoding apparatus of the present invention comprises a means to detect RESYNC BYTES, a means to detect bit synchronization, and a decoding means to be initialized by the means to detect bit synchronization.
- the present invention will achieve highly reliable decoding operation by realizing RESYNC BYTE comprising a bit compensation part, RESYNC detection part, and bit synchronization part and initializing the decoder by detecting the bit synchronization part after detecting the existence of the RESYNC detection part based on the above-mentioned configuration.
- FIG. 1 is a diagram of the recording format
- FIG. 2 is a block diagram illustrating a digital encoding apparatus in one embodiment of the present invention
- FIG. 3 is signal waveform illustrating the operation of FIG. 2 ;
- FIG. 4 is a block diagram illustrating the digital decoding apparatus in one embodiment of the present invention.
- FIG. 5 is signal waveform illustrating the operation of FIG. 4 ;
- FIG. 6 is signal waveform illustrating the operation of FIG. 2 ;
- FIG. 7 is a block diagram illustrating the digital encoding apparatus in another embodiment of the present invention.
- TABLE 1 is a conversion table of (2, 7) code
- TABLE 2 is a conversion table of (1, 7) code
- Digital data is recorded and reproduced along the recording track formed on the optical disk medium and for recording and reproducing units, sectors are set in such a manner to divide the one-round recording track as shown in the track format of FIG. 1 .
- Each sector consists of address ID (ADRS) set at the head which shows the pre-formatted sector address, audio data 0, audio data 1, and video data are arranged on the disk medium with gaps in-between.
- the disk rotating speed is constant and the audio data and video data recording and reproducing timing is controlled with the address ID detection timing set as a standard. Every time the disk medium is exchanged, the disk center deviates by about scores of micrometers, and the timing of data deviates due to this center deviation. However, the above-mentioned gaps are provided with this deviation taken into account to prevent any trouble from occurring in recording and reproduction.
- the video data part begins with a VFO (variable frequency oscillator), which is a fixed continuous pattern for synchronizing clock reproduction, and comprises an 8-byte-long pre-amble block which begins with SYNC (synchronization) BYTES, a continuation of a 94-byte-long block beginning from RESYNC (resynchronization) BYTES, and finally 4-byte-long post-amble block including RESYNC BYTES.
- the SYNC BYTES and RESYNC BYTES are used to achieve data synchronization when reproduced signals are decoded, and SYNC BYTES and RESYNC BYTES are designed to have the same patterns.
- This format is a recording format of a ZCAV (zone-divided constant angular velocity) system with a storage capacity increased by dividing the recording tracks in a plurality of zones in accordance with the size of the disk radius and varying the number of blocks beginning from the above-mentioned RESYNC BYTES in accordance with the zone, and the number of blocks is varied from 106 to 200 in accordance with the disk radius position of the track.
- ZCAV zone-divided constant angular velocity
- the roles of the digital data encoding apparatus are to encode the data into a data stream formatted as shown in FIG. 1 , and, then, to insert SYNC BYTES or RESYNC BYTES.
- the roles of the digital data decoding apparatus are to detect SYNC BYTES or RESYNC BYTES from the data detected from the reproduced signals, and based on the detection results, to decode the data while achieving proper bit synchronization of the decoder and to obtain to original recorded data.
- a (1, 7) code is used for encoding.
- Table 2 shows the conversion table of the (1, 7) code.
- a 3-bit code is assigned for 2-bit data before encoding, and as an exception, a 6-bit code is assigned to the 4-bit data list in the table.
- a “1” is separated by a minimum of one “0” and a maximum of seven “0's.”
- 2-bit or 4-bit data is assigned to 3-bit or 6-bit code, and therefore, it is necessary to achieve synchronization in units of 2-bit data to 3-bit code.
- FIG. 2 shows a configuration of a digital data encoding apparatus in one embodiment according to the present invention
- FIG. 3 illustrates the signal waveform to describe the operation.
- numeral 1 denotes the (1, 7) encoder, 2 the NRZI encoder, 3 an exclusive OR gate, 4 an AND gate, 5 D-type flip flop, 6 a pattern detector, 7 a fixed part register, 8 a RESYNC generator, 9 a switch, and 10 a timing controller.
- the RESYNC generator 8 and switch 9 compose a RESYNC adding means.
- the digital data are formatted as VFO-RESYNC BYTES, post-amble, etc. are arranged, and added to the (1, 7) RLL encoder 1 .
- the (1, 7) RLL encoder 1 converts the data in accordance with the conversion table shown in Table 2 and outputs. For example, in the formatted data corresponding to VFO, a value consisting of all continuous “0” is fixedly given, and as clear from Table 2, in the encoder output, a single “010” pattern continues. This single pattern is used for pull-in of PLL which carries out clock reproduction at the time of reproduction.
- the data corresponding to RESYNC BYTES is 2 bytes long and has 16 consecutive “0's” arranged in advance, and the RESYNC BYTES inserted after encoding are 24 bits.
- FIG. 3 (a) shows the data in the vicinity including this RESYNC BYTE, and the data (b) encoded by the (1, 7) RLL encoder 1 is further encoded with the NRZI encoder comprising the exclusive OR gate 3 , AND gate 4 , and D-type flip flop 5 .
- adding the RESYNC positioning signal (c) given by the timing controller 10 to the AND gate 4 initializes the NRZI encoder 2 for every RESYNC BYTE position.
- This initialization causes the NRZI encoder 2 output to the (d) and the NRZI encoder 2 output at the position right after RESYNC BYTE is fixed to “0.”
- the pattern detector 6 is controlled by the timing controller 10 , monitors the patterns of NRZI encoder 2 output, and outputs No. 1 and No. 2 bits of the bit compensation part as ⁇ 1 1 ⁇ or ⁇ 0 0 ⁇ in accordance with the patterns right before the RESYNC BYTE. In the example of FIG. 3 , ⁇ 1 1 ⁇ is outputted.
- the code patterns right before the RESYNC BYTE after NRZI encoding are classified as shown in Table 3 with all the combinations shown in Table 2 taken into account.
- the fixed part register 7 outputs ⁇ 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 1 0 0 ⁇ .
- the switch 9 inserts the output of the RESYNC generator 8 , which comprises the pattern detector 6 and fixed part register 7 , to the NRZI encoder 2 by the RESYNC BYTE timing given by the timing controller 10 . Consequently, the output of switch 9 becomes as shown with (e) and the recorded data are recorded and the recorded mark is formed as per (f).
- the recorded data becomes the (1, 7)-encoded and NRZI-encoded code stream with RESYNC BYTES periodically inserted.
- the bit compensation part in RESYNC BYTES operates to enable the (1, 7) encoding rule to be smoothly connected to the RESYNC detection part in inserting RESYNC BYTES, and RESYNC BYTES are configured to enable the RESYNC detection part to have 11 consecutive “1's,” and the bit synchronization part has an isolated ⁇ 1 1 1 ⁇ pattern separated by “0's”.
- the RESYNC detection part is designed to fixedly have 11 consecutive “1's” but if it is not fixed to “1” and may be a continuation of either “1's” or “0's,” initialization of the NRZI encoder 2 is not needed and the circuit can be simplified.
- the pattern detection part monitors the data right before RESYNC BYTES of the data stream (1, 7) encoded as per (b) of FIG. 3 and outputs No. 1 to No. 3 bits among the bit compensation part ⁇ Cb 0 Ca 0 0 ⁇ given by Table 4, while the fixed part register outputs the remaining 2 bits ⁇ 0 0 ⁇ of the bit compensation part, ⁇ 1 0 0 0 0 0 0 0 0 0 0 ⁇ of the RESYNC detection part, and ⁇ 1 0 0 1 0 0 1 0 ⁇ of the bit synchronization part.
- RESYNC BYTES of (1) and (2) are 2 bytes in data length before encoding but to achieve resynchronization, still shorter configuration is possible.
- FIG. 4 is an embodiment of the digital data decoding apparatus according, to the present invention, which corresponds to the digital data encoding apparatus of FIG. 2 .
- FIG. 5 shows the waveform to describe the operation.
- numeral 11 is an exclusive OR gate, 12 a D-type flip flop, 13 a NRZI decoder, 14 a (1, 7) decoder, 15 a pattern detector, 16 a bit synchronization detector, 17 a timing generator, and 18 a RESYNC detector comprising 15 , 16 and 17 .
- the reproduced signal obtained by reproducing the recorded mark (b) formed by recording the recorded data shown in FIG. 5 (a) is the signal as shown in (c), in which the recorded data is low-pass-filtered.
- This reproduced signal is data-detected and the recorded code stream is obtained.
- data detection first of all, a suitable slice level is provided for the reproduced signal and is made into the binary-coded signal by a comparator as shown in (d). From this binary-coded signal, the reproduced clock signal CLOCK 1 of (e), the clock component, is reproduced by the phase locked loop, and based on this reproduced clock signal, the recorded code data is detected as shown in (f).
- the obtained signal (f) is inputted into FIG. 4 .
- the pattern detector 15 detects the generation of the RESYNC detection part as shown in (g). In this detection, because in the code stream outside the RESYNC BYTES, a maximum 8 “1's” are allowed continue based on the (1, 7) conversion rule, it is assumed that there would be no mis-detection of the RESYNC detection part.
- the bit synchronization detector 16 detects “0 1 1 1 0” and outputs as shown in (i).
- the timing generator 17 uses outputs of the pattern detector 15 and bit synchronization detector 16 as its inputs, and outputs RESYNC detection signal (j) as well as signal CLOCK 2 corresponding to the clock of decoded data, which is (1, 7) encoded, when the RESYNC detection part of RESYNC BYTES and then the bit synchronization part can be detected while the RESYNC gate signal of FIG. 5 (h) is enabled, and in addition, from the RESYNC BYTE cycle defined by the recording format, the timing generator 17 generates the above-mentioned RESYNC gate signal.
- the NRZI decoder 13 NRZI-decodes the input code stream and outputs as shown in (k).
- the (1, 7) decoder 14 decodes the data in accordance with the inverse conversion rule shown in Table 2 from the decoded clock CLOCK 2 in good bit synchronization outputted by the timing generator 17 and outputs as shown in (1).
- (1, 7) decoding because the RESYNC detector is the data which does not satisfy the conversion rule, it always generates an error resulting in demodulation failure at the portion corresponding to RESYNC BYTES, but because of the characteristics of the conversion rule shown in Table 2, this error does not propagate beyond RESYNC BYTES and the RESYNC detector recovers normal decoding condition.
- the mark formed as the RESYNC detector is comparatively longer than that of other data portions, and the peak shift, etc. generated by recording and reproduction is likely to increase. For this reason, the RESYNC detector tends to arrange by mistake 10 or 12 consecutive “1's.” Considering such cases, it is allowed to assign all of 10, 11, and 12 consecutive “1's” in the code stream to the RESYNC detector as a detection standard of the pattern detector 15 .
- the 10,11, and 12 are examples of the k+2 to k+4.
- the number of continuing “1's” is a maximum of 8, and even when this becomes nine consecutive “1's” by mistake due to the peak shift, this is not mistakenly taken as the RESYNC detector.
- the continuous length of “1's” at the RESYNC detector is assigned to k+3 and its detection standard is designated as k+2, k+3, or k+4. This same principle is applied to the case in which RESYNC BYTES of (2) are established to simplify the apparatus.
- the NRZI encoding operation can be executed after the RESYNC BITE adding operation.
- the present invention contemplates to provide an excellent method and apparatus for digital data encoding/decoding which enables resynchronization without mistakenly detecting code data of other portions as RESYNC codes, by arranging the RESYNC BYTES comprising a bit compensation part, RESYNC detection part, and a bit synchronization part in the code data after modulation, detecting the existence of RESYNC BYTES by detecting the RESYNC detection part, and further detecting the bit synchronization part to achieve bit resynchronization.
- the value of the digital data corresponding to the synchronization code can all be encoded to “0's” in advance and the code data corresponding to the bit synchronization part before they are replaced to RESYNC BYTES can be made identical to those after replacement, enabling the replacement by simple switching and providing features that the hardware can be simplified.
- decoding of the code data part following the RESYNC BYTES can be continuously carried out without any hindrance, enabling the easy initialization of the decoder by detection of the bit synchronization part.
- a bit compensation part is provided before the RESYNC detection part, thereby achieving smooth connection between the code data and RESYNC BYTES, and the clock of the phase locked loop is reproduced without any trouble.
- mis-detection of RESYNC BYTES by the unerased area can be reduced.
- the correlationship between the data part and RESYNC BYTES is made smaller, and RESYNC BYTE detection free from mis-detection is achieved. If this feature is utilized, even in the CLV (constant linear velocity) system, a format adopted to compact disks, etc., it is apparent that the problem that the deviation of linear velocity of the recording track becomes greater than a specified level can be solved and satisfactory RESYNC detection is readily available.
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Abstract
Description
{0 0 1 0 0 0 0 0 0 0 1 0 0 1 0 0}
is periodically inserted, and in the event of decoding operation, first, this RESYNC BYTE is detected; then, based on this, the above-mentioned bit synchronization is achieved for decoding. This RESYNC BYTE is a pattern which cannot exist in any code stream after encoding for any data stream in the rule specified in Table 1, and a RESYNC BYTE will never be detected by mistake with other code data.
{
{1 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 1 0 0}
{
This means that after this RESYNC BYTE is inserted into the (1, 7) encoded data, NRZI encoding is performed. That is, the pattern detection part monitors the data right before RESYNC BYTES of the data stream (1, 7) encoded as per (b) of FIG. 3 and outputs No. 1 to No. 3 bits among the bit compensation part {
{
or
{
{
TABLE 1 | |||
| CODE | ||
10 | 0100 | ||
010 | 100100 | ||
0010 | 00100100 | ||
11 | 1000 | ||
011 | 001000 | ||
0011 | 00001000 | ||
000 | 000100 | ||
TABLE 2 | |||
| CODE | ||
11 | 101 | ||
10 | 100 | ||
01 | 001 | ||
00 | 010 | ||
1111 | 101000 | ||
1110 | 100000 | ||
0111 | 001000 | ||
0110 | 010000 | ||
TABLE 3 | |||
right | bit | ||
before | compensation | ||
code | part | Ca | substituted code array |
BCP | RDP | BSP | ||||
|
|
|
|
|
||
|
11000 | 0 | |
11000 | 11111111111 | 00011100 |
|
00000 | 0 | |
00000 | 11111111111 | 00011100 |
|
11000 | 1 | |
11000 | 11111111111 | 00011100 |
|
00000 | 1 | |
00000 | 11111111111 | 00011100 |
|
11000 | 1 | |
11000 | 11111111111 | 00011100 |
|
11000 | 1 | |
11000 | 11111111111 | 00011100 |
|
00000 | 0 | |
00000 | 11111111111 | 00011100 |
|
11000 | 0 | |
11000 | 11111111111 | 00011100 |
|
00000 | 1 | |
00000 | 11111111111 | 00011100 |
|
11000 | 1 | |
11000 | 11111111111 | 00011100 |
0 1 1 1 1 1 1 | 00000 | 1 | 0 1 1 1 1 1 1 | 00000 | 11111111111 | 00011100 |
1 0 0 0 0 0 0 | 11000 | 1 | 1 0 0 0 0 0 0 | 11000 | 11111111111 | 00011100 |
TABLE 4 | ||||
right | bit | |||
before | compensation | |||
code | part | Aa | Ab | substituted code array |
BCP | RDP | BSP | |||||
|
|
|
|
|
|||
|
00100 | 0 | 1 | |
00100 | 10000000000 | 10010010 |
|
00100 | 0 | 1 | |
00100 | 10000000000 | 10010010 |
|
10000 | 1 | 0 | |
10000 | 10000000000 | 10010010 |
|
10000 | 1 | 0 | |
10000 | 10000000000 | 10010010 |
|
10000 | 1 | 0 | |
10000 | 10000000000 | 10010010 |
0 1 0 0 0 0 0 | 10000 | 1 | 0 | 0 1 0 0 0 0 0 | 10000 | 10000000000 | 10010010 |
Claims (7)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/137,488 USRE39832E1 (en) | 1993-03-15 | 2002-05-03 | Optical recording disk capable of resynchronization in digital encoding and decoding |
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5054186A JP2863052B2 (en) | 1993-03-15 | 1993-03-15 | Digital data encoding method, decoding method, encoding device, and decoding device |
US08/212,724 US5546427A (en) | 1993-03-15 | 1994-03-14 | Method and apparatus for digital code resynchronization in data encoding/decoding |
US08/592,486 US5623477A (en) | 1993-03-15 | 1996-01-26 | Optical recording disk capable of resynchronization in digital encoding and decoding |
US09/295,376 USRE37801E1 (en) | 1993-03-15 | 1999-04-21 | Optical recording disk capable of resynchronization in digital encoding and decoding |
US10/137,488 USRE39832E1 (en) | 1993-03-15 | 2002-05-03 | Optical recording disk capable of resynchronization in digital encoding and decoding |
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US08952486 Reissue | 1996-01-26 |
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USRE39832E1 true USRE39832E1 (en) | 2007-09-11 |
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US10/137,488 Expired - Lifetime USRE39832E1 (en) | 1993-03-15 | 2002-05-03 | Optical recording disk capable of resynchronization in digital encoding and decoding |
US10/138,738 Expired - Lifetime USRE40996E1 (en) | 1993-03-15 | 2002-05-03 | Optical recording disk capable of resynchronization in digital encoding and decoding |
US10/138,737 Expired - Lifetime USRE41022E1 (en) | 1993-03-15 | 2002-05-03 | Optical recording disk capable of resynchronization in digital encoding and decoding |
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US10/138,737 Expired - Lifetime USRE41022E1 (en) | 1993-03-15 | 2002-05-03 | Optical recording disk capable of resynchronization in digital encoding and decoding |
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Also Published As
Publication number | Publication date |
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USRE41022E1 (en) | 2009-12-01 |
USRE40996E1 (en) | 2009-11-24 |
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