JPH0480970A - Insulated-gate field-effect transistor - Google Patents
Insulated-gate field-effect transistorInfo
- Publication number
- JPH0480970A JPH0480970A JP19523890A JP19523890A JPH0480970A JP H0480970 A JPH0480970 A JP H0480970A JP 19523890 A JP19523890 A JP 19523890A JP 19523890 A JP19523890 A JP 19523890A JP H0480970 A JPH0480970 A JP H0480970A
- Authority
- JP
- Japan
- Prior art keywords
- region
- schottky barrier
- drain region
- diode
- groove
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005669 field effect Effects 0.000 title claims description 5
- 230000004888 barrier function Effects 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims description 6
- 239000004065 semiconductor Substances 0.000 claims description 4
- 230000003071 parasitic effect Effects 0.000 abstract description 13
- 238000011084 recovery Methods 0.000 abstract description 10
- 239000002184 metal Substances 0.000 abstract description 8
- 229910052751 metal Inorganic materials 0.000 abstract description 8
- 229910052710 silicon Inorganic materials 0.000 abstract description 6
- 239000010703 silicon Substances 0.000 abstract description 6
- 238000000034 method Methods 0.000 abstract description 5
- 238000004544 sputter deposition Methods 0.000 abstract description 4
- 238000001312 dry etching Methods 0.000 abstract description 3
- 239000011248 coating agent Substances 0.000 abstract description 2
- 238000000576 coating method Methods 0.000 abstract description 2
- 229910021332 silicide Inorganic materials 0.000 abstract description 2
- 230000007547 defect Effects 0.000 abstract 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 11
- 229920005591 polysilicon Polymers 0.000 description 11
- 239000010408 film Substances 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 239000000969 carrier Substances 0.000 description 5
- 239000012535 impurity Substances 0.000 description 5
- 238000000137 annealing Methods 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 4
- 239000005360 phosphosilicate glass Substances 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- 238000009825 accumulation Methods 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 239000010410 layer Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 230000001360 synchronised effect Effects 0.000 description 2
- 238000011282 treatment Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
- H01L29/7806—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a Schottky barrier diode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/47—Schottky barrier electrodes
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
この発明は、絶縁ゲート型電界効果トランジスタの構造
に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the structure of an insulated gate field effect transistor.
従来から、電力用絶縁ゲート型電界効果トランジスタと
して、縦型ＭＯ３ＦＥＴ構造を基本とし、種々の構造が
提案されている。それらの構造はいずれも、ポリシリコ
ンをゲート電極として又、そのポリシリコンゲート電極
をマスクとして、チャネル領域、ソース領域を二重セル
フアライメント法により形成するものが基本である。第
１図に、従来縦型Ｍ ＯＳ Ｆ Ｅ Ｔのセルの一部の
断面構造を示す。図中１はドレイン領域、２はチャネル
領域、３はソース領域、４はポリシリコンゲート電極、
５はゲート絶縁膜、６は高濃度Ｐ″″″領域 はソース
およびパックゲートオーミックコンタクト用電極、８は
層間絶縁膜である。第２図に、第１図の等価回路を示す
。図中Ｄ１はドレイン領域１とチャネル領域２及び高濃
度Ｐ゛領域６により 形成される寄生ＰＮ接合ダイオー
ドである。このような構造の縦型ＭＯ３ＦＥＴを電源機
器の１次側スイッチング素子として使用する時、
この寄生ＰＮ
接合ダイオードＤ１は、フライホイールダイオドとして
使用される。ところが、この場合、寄生ＰＮ接合ダイオ
ードの少数キャリアの蓄積による逆回復損失が大きく、
高周波動作ができない。そこで、一般には高速のショッ
トキーバリアダイオドをパラに外付けする等の工夫が必
要となっている。また、同期整流素子として使用した場
合にゲー
は、傘中ト電圧立上りの遅れ等により、この寄生ＰＮ接
合ダイオードが動作し、順方向損失及び逆回復損失等の
問題を生じ、ＦＥＴの低損失・高速性が活かされていな
い。Conventionally, various structures have been proposed as insulated gate field effect transistors for power use, based on a vertical MO3FET structure. The basic structure of all of these structures is to form a channel region and a source region by a double self-alignment method using polysilicon as a gate electrode and using the polysilicon gate electrode as a mask. FIG. 1 shows a cross-sectional structure of a part of a conventional vertical MOS FET cell. In the figure, 1 is a drain region, 2 is a channel region, 3 is a source region, 4 is a polysilicon gate electrode,
5 is a gate insulating film, 6 is a high-concentration P region, an electrode for source and pack gate ohmic contacts, and 8 is an interlayer insulating film. Fig. 2 shows an equivalent circuit of Fig. 1. In the figure, D1 is a parasitic PN junction diode formed by the drain region 1, channel region 2, and high concentration P region 6. When a vertical MO3FET with such a structure is used as a primary side switching element of a power supply device, this parasitic The PN junction diode D1 is used as a flywheel diode.However, in this case, the reverse recovery loss due to the accumulation of minority carriers in the parasitic PN junction diode is large.
High frequency operation is not possible. Therefore, it is generally necessary to take measures such as attaching a high-speed Schottky barrier diode externally. In addition, when used as a synchronous rectifier, this parasitic PN junction diode operates due to a delay in the rise of the voltage during operation, causing problems such as forward loss and reverse recovery loss, resulting in low loss and High speed is not taken advantage of.
本発明は、上記、寄生ＰＮ接合ダイオードが動作するこ
とによる欠点（逆回復損失、順方向損失）を克服するこ
とを目的とする。The present invention aims to overcome the drawbacks (reverse recovery loss, forward loss) caused by the operation of the parasitic PN junction diode.
第３図は、本発明の実施例であって、縦型ＭＯ３ＦＥＴ
のセル断面図を示したものである。FIG. 3 shows an embodiment of the present invention, in which a vertical MO3FET
This figure shows a cross-sectional view of the cell.
図中１は、エピタキシャル法等により形成されるシリコ
ン基体であり、ｎ−型のドレイン領域、２はドレイン領
域１の主表面からＰ型の不純物、例えばボロンをイオン
注入し、アニールならびに拡散処理を行ったチャネル領
域、３はチャネル領域２の内部にドレイン領域１と同一
の導電型になるｎ型の不純物、例えばリンをイオン注入
しアニルならびに拡散処理を行ったソース領域、４はゲ
ト絶縁膜５を介してチャネル領域２上にドレイン領域１
とソース領域３にまたがるように設けたゲート電極であ
り、例えばポリシリコンにより形成される。８は、ゲー
ト電極４とソース電極７を絶縁分離する層間絶縁膜であ
り、例えば、リンケイ酸ガラス（ＰＳＧ）で形成される
。ポリシリコンやＰＳＧはいずれも周知のＣＶＤ法等で
形成される。In the figure, 1 is a silicon substrate formed by an epitaxial method, etc., and 2 is an n-type drain region, and 2 is a P-type impurity, such as boron, ion-implanted from the main surface of the drain region 1, and then subjected to annealing and diffusion treatment. 3 is a source region in which an n-type impurity, such as phosphorus, is ion-implanted into the channel region 2 to have the same conductivity type as that of the drain region 1, and annealing and diffusion treatments are performed; 4 is a gate insulating film 5; drain region 1 on channel region 2 via
This is a gate electrode provided so as to straddle the source region 3 and the source region 3, and is made of polysilicon, for example. Reference numeral 8 denotes an interlayer insulating film for insulating and separating the gate electrode 4 and the source electrode 7, and is made of, for example, phosphosilicate glass (PSG). Both polysilicon and PSG are formed by the well-known CVD method.
９は、ソース領域１にかかる主表面からｎ−ドレイン領
域伊まで到達するようにＵ字形の溝を周知／の異方性ド
ライエツチング技術で形成し、その溝表面に例えば、ス
パッタ法で形成した金属被膜である。金属として、ｎ型
シリコンに対してショットキー障壁を形成する金属、例
えばＣｒ、Ｔｉ、Ｍｏまたはこれらのシリサイドを用い
ればｎ−ドレイン領域にかかる溝部領域は、ショットキ
ーバリアーダイオードとなり、バックゲートは、溝の側
面でコンタクトされる。9, a U-shaped groove was formed by a well-known anisotropic dry etching technique so as to reach from the main surface of the source region 1 to the n-drain region 1, and was formed on the surface of the groove by, for example, a sputtering method. It is a metal coating. If a metal that forms a Schottky barrier to n-type silicon, such as Cr, Ti, Mo, or a silicide thereof, is used as the metal, the trench region over the n-drain region becomes a Schottky barrier diode, and the back gate becomes a Schottky barrier diode. Contact is made on the sides of the groove.
第４図は、本発明の製造工程を示したものである。FIG. 4 shows the manufacturing process of the present invention.
図中（ａ）は、高濃度ｎ゛基体所望の不純物濃度ｎ−層
１をエピタキシャル成長させたものである。（ｂ）は、
高濃度Ｐ＋領域６を（ａ）の基体に、Ｐ型となる不純物
、例えばボロンを高濃度に選択的にイオン注入し形成し
たものである。In the figure (a), an n- layer 1 with a desired impurity concentration is epitaxially grown on a high-concentration n-substrate. (b) is
The high-concentration P+ region 6 is formed by selectively ion-implanting a P-type impurity, such as boron, into the substrate of (a) at a high concentration.
次に、ゲート絶縁膜例えば酸化膜５をシリコン基体の熱
酸化により形成し、その後ポリシリコン４を減圧ＣＶＤ
法で形成する。ポリシリコンへのリンの気相デポジショ
ン、及びポリシリコンのパタニングによりゲート電極を
形成する（図中Ｃ）。Next, a gate insulating film such as an oxide film 5 is formed by thermal oxidation of the silicon substrate, and then polysilicon 4 is formed by low pressure CVD.
form by law. A gate electrode is formed by vapor phase deposition of phosphorus onto polysilicon and patterning of the polysilicon (C in the figure).
次にこのポリシリコンをマスクにして、ボロンのイオン
注入、アニール及び拡散によりチャネル領域２を形成し
、さらに同一ポリシリコンをマスクにして、ｎ型になる
不純物、例えばリン牽イオン注入、アニール、及び拡散
により、ソース領域３を形成する（図中ｄ）。次にゲー
ト電極とソース電極とを絶縁分離するために、層間膜８
（ＰＳＧ）を常圧ＣＶＤ法等により形成し、さらに、ソ
ース領域とソース電極をコンタクトさせるためのコンタ
クトホールを形成する（図中ｅ）。次にコンタクトホー
ルの内側のシリコンを、異方性ドライエツチングにより
、ｎ′″ドレイン領域に到達する０字ｌ形の溝Ｕを形成
する（図中ｆ）。次にｎ型シリコンに対する金属９、例
えば、Ｃｒ薄膜をスパッタリング法により、溝内に形成
し、バターニングを行う（図中ｇ）。最後に、ソース電
極７となる金属、例えばＡ１層をスパッタリングにより
形成し、パターニングを行う（図中ｈ）。Next, using this polysilicon as a mask, a channel region 2 is formed by ion implantation, annealing, and diffusion of boron. Furthermore, using the same polysilicon as a mask, an impurity to become n-type, such as phosphorous ion implantation, annealing, and A source region 3 is formed by diffusion (d in the figure). Next, in order to insulate and separate the gate electrode and the source electrode, an interlayer film 8
(PSG) is formed by a normal pressure CVD method or the like, and a contact hole for contacting the source region and the source electrode is formed (e in the figure). Next, the silicon inside the contact hole is subjected to anisotropic dry etching to form a 0-shaped groove U reaching the n''' drain region (f in the figure). Next, a metal 9 for the n-type silicon, For example, a Cr thin film is formed in the groove by sputtering and patterned (g in the figure).Finally, a metal that will become the source electrode 7, for example an A1 layer, is formed by sputtering and patterned (g in the figure). h).
第５図は、本発明品の等何回路を示したものである。図
中Ｄ１は、チャネル領域２及び高濃度Ｐ“領域６とｎ−
ドレイン領域１とにより形成されるＰＮ接合ダイオード
、ＳＢＤはｎ−ドレイン領域の溝部に形成されるショッ
トキーバリアーダイオドである。FIG. 5 shows a similar circuit of the product of the present invention. In the figure, D1 indicates the channel region 2 and the high concentration P" region 6 and n-
The PN junction diode SBD formed by the drain region 1 is a Schottky barrier diode formed in the groove of the n-drain region.
本半導体装置を電源機器の１次側のスイッチング素子ど
して使用し、このＭＯＳＦＥＴのソースドレイン間に並
列接続されている寄生ダイオードをフライホイールダイ
オードとして使用する場合の動作を以下に示す。第６図
にショットキーバリアダイオードＳＢＤ及びＰＮ接合ダ
イオードＤ１の順方向Ｖ−Ｉ特性を示す。ショットキー
バリアダイオードＳＢＤはＰＮ接合ダイオードＤ１より
も低い電圧で立上る。本発明では、これら二つのダイオ
ードが並列接続されているため、ＰＮ接合ダイオードＤ
ユが動作する前にショットキーバリアダイオードＳＢＤ
が動作し、ＰＮ接合ダイオドの立上り電圧になるまで、
ショットキーバリアダイオードのみが動作する。ショッ
トキバリアダイオードは多数キャリアデバイスであり、
少数キャリアの蓄積が無い。従って、この動作領域では
逆回復による損失は極めて小さくなる。The operation when this semiconductor device is used as a switching element on the primary side of a power supply device and a parasitic diode connected in parallel between the source and drain of this MOSFET is used as a flywheel diode will be described below. FIG. 6 shows forward VI characteristics of the Schottky barrier diode SBD and the PN junction diode D1. The Schottky barrier diode SBD rises at a lower voltage than the PN junction diode D1. In the present invention, since these two diodes are connected in parallel, the PN junction diode D
Schottky barrier diode SBD before operation
operates and reaches the rising voltage of the PN junction diode.
Only Schottky barrier diodes work. A Schottky barrier diode is a majority carrier device,
There is no accumulation of minority carriers. Therefore, in this operating region, the loss due to reverse recovery is extremely small.
次に、本半導体装置を同期整流素子として使用する場合
の実施例について述べる。Next, an example in which the present semiconductor device is used as a synchronous rectifier will be described.
第７図は、実施例を示した特性例である。FIG. 7 is a characteristic example showing an example.
図中１はＭＯＳＦＥＴのチャネル電流のみの特性、２は
ショットキーバリアダイオードのみの特性、３は寄生Ｐ
Ｎ接合ダイオードのみの特性、４は本発明による特性で
ある。図中Ｏ−ａ間は、チャネル電流のみが流れる領域
であり、ａ−ｂ間は、チャネル電流とショットキバリア
ダイオードを流れる電流との合成電流が流れる領域であ
る。従って、０−ｂ間まで、多数キャリアによる電流が
流れ、少数キャリアの蓄積が無いため、逆回復損失が極
めて小さくなる。In the figure, 1 is the characteristic of only the MOSFET channel current, 2 is the characteristic of only the Schottky barrier diode, and 3 is the characteristic of the parasitic P
Characteristics of only the N-junction diode, 4 are characteristics according to the present invention. In the figure, a region between O and a is a region where only the channel current flows, and a region between a and b is a region where a combined current of the channel current and the current flowing through the Schottky barrier diode flows. Therefore, current due to majority carriers flows between 0 and b, and there is no accumulation of minority carriers, so that reverse recovery loss becomes extremely small.
通常動作では、例えば、図中Ｃ点で動作させるため、他
の整流素子に比べ順方向電圧降下■、の非常に低い整流
素子となる。また、大きいノイズ電流が入った場合でも
、ｂ点までは、多数キャリア電流が流れるため、ノイズ
電流による逆回復損失は極めて小さくなる。さらに、ゲ
ート電圧立ち上がりの遅れが生じて、寄生ダイオードが
動作した場合でも、ショットキバリアダイオードが動作
するため、従来構造よりも順方向損失及び逆回復損失が
小さくなる。In normal operation, for example, since the rectifying element operates at point C in the figure, the rectifying element has a forward voltage drop that is very low compared to other rectifying elements. Furthermore, even when a large noise current is applied, the majority carrier current flows up to point b, so that the reverse recovery loss due to the noise current becomes extremely small. Furthermore, even if a parasitic diode operates due to a delay in the rise of the gate voltage, the Schottky barrier diode operates, so the forward loss and reverse recovery loss are smaller than in the conventional structure.
以上の説明から明らかなように本発明によれば従来構造
の縦型ＭＯ３ＦＥＴのセル内部にショットキーバリアダ
イオードを内蔵させるため■特別に外付はショットキー
ダイオードを設ける必要が無いため回路構成が簡略化さ
れる。As is clear from the above explanation, according to the present invention, a Schottky barrier diode is built into the cell of a conventionally structured vertical MO3FET. ■There is no need to provide an external Schottky diode, so the circuit configuration is simplified. be converted into
■ショットキーバリアダイオードを内蔵しても、チップ
サイズは増加しない。−（低価格）■寄生ＰＮ接合ダイ
オード領域の一部からＳＢＤになっているため、寄生Ｐ
Ｎ接合ダイオードの有効面積を小さくでき、ＰＮ接合ダ
イオードが動作しても少数キャリアの注入量を減らすこ
とができる。■Including a Schottky barrier diode does not increase the chip size. - (Low price) ■Since a part of the parasitic PN junction diode region becomes SBD, the parasitic P
The effective area of the N-junction diode can be reduced, and even when the PN-junction diode operates, the amount of minority carriers injected can be reduced.
■寄生ＰＮ接合ダイオードが動作する前にＳＢＤが動作
する為、逆回復損失が小さい。■Since the SBD operates before the parasitic PN junction diode operates, reverse recovery loss is small.
■ノイズ電流に対しても逆回復損失が小さい。■Reverse recovery loss is small even against noise current.
等、実用上の効果は大きい。etc., the practical effects are great.
第１図、第２図は従来の縦形ＭＯ８ＦＥＴセルの断面図
及びその等価回路図、第３図、第５図は本発明の一実施
例構造を示す断面図及びその等価回路図、第４図は本発
明の製造工程を示す断面図、第６図、第７図は本発明の
動作を示す特性図である。図中１はドレイン領域、２は
チャンネル領域、３はソース領域、４はポリシリコンゲ
ート電極、５はゲート絶縁膜、６は高濃度Ｐ′″領域、
７ はソース電極、８は層間絶縁膜、９はショットキバ
リア金属、Ｄｌは寄生ＰＮダイオード、ＳＢＤ はショ
ットキバリアダイオードである。1 and 2 are a sectional view and an equivalent circuit diagram of a conventional vertical MO8FET cell, FIGS. 3 and 5 are a sectional view and an equivalent circuit diagram of an embodiment of the present invention, and FIG. 6 is a sectional view showing the manufacturing process of the present invention, and FIGS. 6 and 7 are characteristic diagrams showing the operation of the present invention. In the figure, 1 is a drain region, 2 is a channel region, 3 is a source region, 4 is a polysilicon gate electrode, 5 is a gate insulating film, 6 is a high concentration P''' region,
7 is a source electrode, 8 is an interlayer insulating film, 9 is a Schottky barrier metal, Dl is a parasitic PN diode, and SBD is a Schottky barrier diode.
Claims (1)
導電型のチャネル領域を形成し、該チャネル領域内に形
成した第１導電型のソース領域及び該ドレイン領域上に
ゲート絶縁膜を介して、該ドレイン領域と該ソース領域
にまたがるように設けたゲート電極から成り、該ゲート
電極に囲まれた窓内にソース電極をコンタクトさせるよ
うにした絶縁ゲート型電界効果トランジスタにおいて、
ソース電極からドレイン領域に至るまで溝を掘り、少な
くとも該溝部ドレイン領域にショットキー障壁を形成し
た構造を特徴とする絶縁ゲート型電界効果トランジスタ
。A second conductivity type semiconductor substrate serving as a drain region is provided with a second conductivity type semiconductor substrate.
A conductivity type channel region is formed, a first conductivity type source region formed in the channel region, and a gate provided over the drain region so as to span the drain region and the source region with a gate insulating film interposed therebetween. In an insulated gate field effect transistor consisting of an electrode and having a source electrode in contact with a window surrounded by the gate electrode,
1. An insulated gate field effect transistor characterized by a structure in which a trench is dug from a source electrode to a drain region, and a Schottky barrier is formed at least in the trench drain region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19523890A JPH0480970A (en) | 1990-07-24 | 1990-07-24 | Insulated-gate field-effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19523890A JPH0480970A (en) | 1990-07-24 | 1990-07-24 | Insulated-gate field-effect transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0480970A true JPH0480970A (en) | 1992-03-13 |
Family
ID=16337785
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19523890A Pending JPH0480970A (en) | 1990-07-24 | 1990-07-24 | Insulated-gate field-effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0480970A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006149195A (en) * | 1995-06-21 | 2006-06-08 | Cree Inc | Converter circuit, and circuit having at least one switching device, and circuit module |
| EP1999792A2 (en) * | 2006-03-10 | 2008-12-10 | Alpha & Omega Semiconductor Limited | Shielded gate trench(sgt) mosfet cells implemented with a schottky source contact |
| WO2013177552A1 (en) * | 2012-05-24 | 2013-11-28 | Microsemi Corporation | Monolithically integrated sic mosfet and schottky barrier diode |
-
1990
- 1990-07-24 JP JP19523890A patent/JPH0480970A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006149195A (en) * | 1995-06-21 | 2006-06-08 | Cree Inc | Converter circuit, and circuit having at least one switching device, and circuit module |
| EP1999792A2 (en) * | 2006-03-10 | 2008-12-10 | Alpha & Omega Semiconductor Limited | Shielded gate trench(sgt) mosfet cells implemented with a schottky source contact |
| EP1999792A4 (en) * | 2006-03-10 | 2009-05-20 | Alpha & Omega Semiconductor | Shielded gate trench(sgt) mosfet cells implemented with a schottky source contact |
| WO2013177552A1 (en) * | 2012-05-24 | 2013-11-28 | Microsemi Corporation | Monolithically integrated sic mosfet and schottky barrier diode |
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