JPH0480879B2 - - Google Patents

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Publication number
JPH0480879B2
JPH0480879B2 JP9539084A JP9539084A JPH0480879B2 JP H0480879 B2 JPH0480879 B2 JP H0480879B2 JP 9539084 A JP9539084 A JP 9539084A JP 9539084 A JP9539084 A JP 9539084A JP H0480879 B2 JPH0480879 B2 JP H0480879B2
Authority
JP
Japan
Prior art keywords
substrate
annealing
film
implanted
compound
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP9539084A
Other languages
Japanese (ja)
Other versions
JPS60239399A (en
Inventor
Toshiki Ehata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Industries Ltd
Original Assignee
Sumitomo Electric Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Electric Industries Ltd filed Critical Sumitomo Electric Industries Ltd
Priority to JP9539084A priority Critical patent/JPS60239399A/en
Publication of JPS60239399A publication Critical patent/JPS60239399A/en
Publication of JPH0480879B2 publication Critical patent/JPH0480879B2/ja
Granted legal-status Critical Current

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Description

【発明の詳細な説明】 〔技術分野〕 本発明はGaAs、InP等の化合物半導体にN型
もしくはP型の不純物となり得るイオンを注入し
た後、化合物半導体を高温にてアニールし、イオ
ン注入層を活性化させる方法に関するものであ
る。
[Detailed Description of the Invention] [Technical Field] The present invention involves implanting ions that can become N-type or P-type impurities into a compound semiconductor such as GaAs or InP, and then annealing the compound semiconductor at a high temperature to form an ion-implanted layer. It relates to a method of activation.

〔背景技術〕[Background technology]

GaAs等の化合物半導体結晶基板を用いイオン
注入によつてトランジスタや集積回路を製作する
場合、アニールの工程は導電層を形成する上で不
可欠である。アニールは一般にイオン注入された
化合物半導体基板を抵抗加熱炉で数十分間高温加
熱処理するものである。加熱温度は基板に含まれ
る蒸気圧の高い成分例えばAsやPが蒸発を開始
する温度より高いため基板が熱分解を生じるとい
う問題があつた。このためアニールによつて基板
表面に形成する導電層の電気的性質が変動し、バ
ラツキが大きいという問題があつた。
When manufacturing transistors and integrated circuits by ion implantation using a compound semiconductor crystal substrate such as GaAs, an annealing process is essential for forming a conductive layer. Annealing generally involves heating a compound semiconductor substrate into which ions have been implanted at a high temperature for several tens of minutes in a resistance heating furnace. Since the heating temperature is higher than the temperature at which components with high vapor pressure contained in the substrate, such as As and P, begin to evaporate, there has been a problem that the substrate undergoes thermal decomposition. For this reason, there was a problem in that the electrical properties of the conductive layer formed on the substrate surface varied due to annealing, resulting in large variations.

これを防ぐため蒸気圧の高い成分の蒸気圧下で
アニールしたり蒸発を防ぐための保護膜例えば、
SiO2膜やSi3N4膜を基板表面に形成した後にアニ
ールする方法が採られている。しかしながら前者
の方法では蒸気圧の高い成分を含むガスが有毒で
あるため操作や処理が複雑なプロセスとなり、生
産性が著しく低いという問題が残る。一方、後者
では保護膜の形成法、形成条件によつて膜の性質
が異なるため安定性、再現性が低くアニール中に
保護膜が割れる等の問題がある。
To prevent this, annealing under the vapor pressure of components with high vapor pressure or a protective film to prevent evaporation, for example,
A method is used in which a SiO 2 film or a Si 3 N 4 film is formed on the substrate surface and then annealed. However, in the former method, the problem remains that the gas containing components with high vapor pressure is toxic, making the process complicated to operate and processing, and resulting in extremely low productivity. On the other hand, in the latter case, since the properties of the protective film vary depending on the method and conditions for forming the protective film, there are problems such as low stability and reproducibility and cracking of the protective film during annealing.

また、従来のアニール法は電気炉で数十分間高
熱温処理するため基板結晶内の残留不純物である
CrやMnが拡散や表面近傍での高濃度化等を起こ
し、イオン注入された原子と相互に影響を及ぼす
ことが知られている。このためアニールによる活
性化率が不安定となり、トランジスタや集積回路
の電気特性を制御することが困難となつている。
さらに従来のアニール法では注入された原子がア
ニール中に表面と平行な方向に十分の数ミクロン
も拡散する横方向拡散も知られている。このため
注入領域、例えば実効ゲート長が変化することに
なり1μmという微細加工が必要な素子製造の面
からは重大な問題となる。
In addition, the conventional annealing method involves high-temperature treatment for several tens of minutes in an electric furnace, which causes residual impurities in the substrate crystal.
It is known that Cr and Mn cause diffusion and high concentration near the surface, and interact with ion-implanted atoms. For this reason, the activation rate due to annealing becomes unstable, making it difficult to control the electrical characteristics of transistors and integrated circuits.
Furthermore, in conventional annealing methods, lateral diffusion is also known, in which implanted atoms diffuse several tenths of a micrometer in a direction parallel to the surface during annealing. This causes a change in the implanted region, for example, the effective gate length, which poses a serious problem in terms of device manufacturing, which requires microfabrication of 1 μm.

これに対し、近年赤外線ランプによるアニール
法が報告されている。図2はその一例である。基
板を急速に加熱できるという特徴から従来法のア
ニールより約2桁短いアニール時間が可能であ
り、従つて横方向拡散も抑制できると共に蒸気圧
の高いAsやPの成分の蒸発も最小限に低減でき
ると報告されている。しかしながら、AsやPの
蒸発は原理的に皆無にできない。例えば、800℃
で10秒間熱処理しただけでも鏡面研磨された
GaAs基板表面の全面にわたつて微小な斑点が生
じ、いわゆるAs抜けが観察され、AsやPの蒸発
については依然問題が残つている。
In contrast, an annealing method using an infrared lamp has been reported in recent years. FIG. 2 is an example. Due to its ability to rapidly heat the substrate, the annealing time is approximately two orders of magnitude shorter than that of conventional annealing methods, and lateral diffusion can be suppressed as well as the evaporation of As and P components, which have high vapor pressure, to a minimum. It is reported that it is possible. However, evaporation of As and P cannot be completely eliminated in principle. For example, 800℃
Mirror polishing was achieved even after heat treatment for 10 seconds.
Minute spots appear over the entire surface of the GaAs substrate, and so-called As omission is observed, and there still remains a problem with the evaporation of As and P.

〔発明の開示〕[Disclosure of the invention]

本発明はこのような従来法の欠点を解消し、化
合物半導体の熱分解を防ぐと同時に横方向の拡散
を抑制し得るアニール方法を提供するものであ
る。
The present invention eliminates the drawbacks of the conventional methods and provides an annealing method capable of preventing thermal decomposition of a compound semiconductor and at the same time suppressing lateral diffusion.

以下、実施例に即して、本発明を説明する。図
2は化合物半導体としてGaAs基板を用いる場合
の本発明によるアニール法の構成を図示したもの
である。一度真空排気された後、N2ガスを満た
した石英管11の内部中央に石英治具12を介し
て保持された厚さ数mmのカーボングラフアイト板
13上に両面に厚さ1000ÅのSi3N4膜14をプラ
ズマCVD法で形成したGaAs基板15をイオン注
入された面を上にして置き、その上に同様に両面
に1000ÅのSi3N4膜14′を形成したGaAs基板1
5′をのせて石英管11の外部よりGaAs基板1
5の両面からランプヒータ16を用いて照射して
加熱させる。アニール温度は、GaAs基板15の
近傍に設置した熱電対により測定し、これを基準
にしてランプに印加する電力をPID制御すること
により、加熱速度、アニール温度を一定にした。
本発明になるアニール法で900℃10秒間アニール
した試料は従来の電気炉で、800℃20分アニール
した試料と同等のキヤリア濃度プロフアイルを示
した。
Hereinafter, the present invention will be explained based on Examples. FIG. 2 illustrates the configuration of an annealing method according to the present invention when a GaAs substrate is used as a compound semiconductor. Once evacuated, Si 3 with a thickness of 1000 Å is placed on both sides on a carbon graphite plate 13 with a thickness of several mm, which is held via a quartz jig 12 in the center of the quartz tube 11 filled with N 2 gas. A GaAs substrate 15 on which an N 4 film 14 has been formed by plasma CVD is placed with the ion-implanted side facing up, and a GaAs substrate 1 on which a 1000 Å Si 3 N 4 film 14' is similarly formed on both sides is placed.
5′ and GaAs substrate 1 from outside of quartz tube 11.
5 is irradiated and heated from both sides using a lamp heater 16. The annealing temperature was measured by a thermocouple placed near the GaAs substrate 15, and the heating rate and annealing temperature were kept constant by PID control of the power applied to the lamp based on this measurement.
A sample annealed at 900°C for 10 seconds using the annealing method of the present invention showed a carrier concentration profile equivalent to a sample annealed at 800°C for 20 minutes in a conventional electric furnace.

また上記条件のランプアニール法を適用し、実
際にピンチオフ電圧が−0.5V〜−1.2Vの範囲で、
GaAs電界効果トランジスタを作製したところ、
17mm×17mmの領域中の6000〜7000個のFETのピ
ンチオフ電圧のバラツキが1シグマで100mVと
いう結果を得た。ちなみに基板15′をのせずに
アニールした場合はピンチオフ電圧は同じでバラ
ツキのみが1シグマで200〜150mVと大きくな
り、かつ再現性が悪化した。このことから基板1
5′がGaAs基板15とSi3N4膜14の両者の熱分
解を防ぐことに有効であることが確認できた。
In addition, by applying the lamp annealing method under the above conditions, when the pinch-off voltage is in the range of -0.5V to -1.2V,
When we fabricated a GaAs field effect transistor,
The results showed that the variation in pinch-off voltage of 6000 to 7000 FETs in a 17 mm x 17 mm area was 100 mV at 1 sigma. Incidentally, when annealing was performed without placing the substrate 15' on it, the pinch-off voltage was the same, only the variation was large at 200 to 150 mV at 1 sigma, and the reproducibility was deteriorated. From this, board 1
5' was confirmed to be effective in preventing thermal decomposition of both the GaAs substrate 15 and the Si 3 N 4 film 14.

本発明を構成する要件の一つはランプからの熱
線として赤外線のみならず、赤外線よりも波長の
短い光をも利用することにある。化合物半導体は
赤外領域の光線に対して大きな透過率を有してい
るため赤外線による化合物半導体基板の加熱は実
質上効率が極めて小さくなる。そこで本発明では
赤外線より短波長な光で基板を直接加熱すると同
時に赤外線で基板を載せたカーボングラフアイト
治具を加熱することにより、加熱効率を著しく向
上することにある。
One of the requirements constituting the present invention is to utilize not only infrared rays but also light with a shorter wavelength than infrared rays as the heat rays from the lamp. Since compound semiconductors have a high transmittance to light in the infrared region, the efficiency of heating the compound semiconductor substrate with infrared rays is extremely low. Therefore, the present invention aims to significantly improve heating efficiency by directly heating the substrate with light having a wavelength shorter than infrared rays and simultaneously heating the carbon graphite jig on which the substrate is mounted with infrared rays.

さらにもう一つの要件は化合物半導体基板の少
なくともイオン注入された面に無機化合物の保護
膜を形成し、かつ、その上に同一構造の基板を置
いてアニールすることにある。これにより蒸気圧
の高い成分の蒸発を完全に阻止することが可能と
なる。この目的から考えるに無機化合物膜として
は実施例のSi3N4膜やプラズマCVD法に何ら限定
されるものではなく、他にSiO2膜、Al2O3膜AlN
膜等を周知の製法で形成することも可能である。
Yet another requirement is to form a protective film of an inorganic compound on at least the ion-implanted surface of the compound semiconductor substrate, and to place a substrate of the same structure on top of the protective film and anneal it. This makes it possible to completely prevent evaporation of components with high vapor pressure. Considering this purpose, the inorganic compound film is not limited to the Si 3 N 4 film in the example or the plasma CVD method, but also SiO 2 film, Al 2 O 3 film, AlN film, etc.
It is also possible to form the film etc. by a well-known manufacturing method.

さらにアニールは化合物半導体基板に高温で不
必要な化学反応を生じないために不活性ガス中で
行なえば本発明の目的を満たすことから雰囲気は
実施例のN2ガスに何ら限定されるものではなく、
N2の他にAr、He等の不活性ガスやH2ガス及び
それらの混合ガスも適用できることを付言する。
Furthermore, the atmosphere is not limited to the N 2 gas used in the example, as the object of the present invention can be achieved if annealing is performed in an inert gas to avoid unnecessary chemical reactions at high temperatures on the compound semiconductor substrate. ,
It should be added that in addition to N 2 , inert gases such as Ar and He, H 2 gas, and mixed gases thereof can also be applied.

【図面の簡単な説明】[Brief explanation of the drawing]

図1は本発明によるアニール法の構成例を図示
したものであり、図2は従来のアニール法の構成
例である。 11……石英管、12……石英治具、13……
カーボングラフアイト板、14,14′……無機
化合物膜、15,15′……化合物半導体基板、
16……ランプヒータ。
FIG. 1 shows an example of the structure of the annealing method according to the present invention, and FIG. 2 shows an example of the structure of the conventional annealing method. 11...Quartz tube, 12...Quartz jig, 13...
Carbon graphite plate, 14, 14'...Inorganic compound film, 15, 15'... Compound semiconductor substrate,
16...Lamp heater.

Claims (1)

【特許請求の範囲】[Claims] 1 N型またはP型となりうるイオンを注入され
た化合物半導体基板の少なくともイオン注入され
た側の表面に無機化合物膜を形成し、該基板のイ
オン注入された側の表面上に、無機化合物膜を形
成した同一構造の半導体基板を、両基板の無機化
合物膜が互いに接するように重ね赤外線及びそれ
より短い波長域にスペクトルをもつランプにて該
化合物半導体を照射して加熱することを特徴とす
る化合物半導体のアニール法。
1 Forming an inorganic compound film on at least the ion-implanted side surface of a compound semiconductor substrate into which ions that can be N-type or P-type are implanted, and forming an inorganic compound film on the ion-implanted surface of the substrate. A compound characterized in that the formed semiconductor substrates having the same structure are stacked so that the inorganic compound films of both substrates are in contact with each other, and the compound semiconductor is heated by irradiating the compound semiconductor with a lamp having a spectrum in the infrared rays and shorter wavelength ranges. Semiconductor annealing method.
JP9539084A 1984-05-11 1984-05-11 Process for annealing compound semiconductor Granted JPS60239399A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9539084A JPS60239399A (en) 1984-05-11 1984-05-11 Process for annealing compound semiconductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9539084A JPS60239399A (en) 1984-05-11 1984-05-11 Process for annealing compound semiconductor

Publications (2)

Publication Number Publication Date
JPS60239399A JPS60239399A (en) 1985-11-28
JPH0480879B2 true JPH0480879B2 (en) 1992-12-21

Family

ID=14136316

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9539084A Granted JPS60239399A (en) 1984-05-11 1984-05-11 Process for annealing compound semiconductor

Country Status (1)

Country Link
JP (1) JPS60239399A (en)

Also Published As

Publication number Publication date
JPS60239399A (en) 1985-11-28

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