JPH0263294B2 - - Google Patents

Info

Publication number
JPH0263294B2
JPH0263294B2 JP60074556A JP7455685A JPH0263294B2 JP H0263294 B2 JPH0263294 B2 JP H0263294B2 JP 60074556 A JP60074556 A JP 60074556A JP 7455685 A JP7455685 A JP 7455685A JP H0263294 B2 JPH0263294 B2 JP H0263294B2
Authority
JP
Japan
Prior art keywords
annealing
wafer
sio
seconds
trapping
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP60074556A
Other languages
Japanese (ja)
Other versions
JPS6142145A (en
Inventor
Aurahamu Ueinbaagu Jiiu
Riidaa Yangu Donarudo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of JPS6142145A publication Critical patent/JPS6142145A/en
Publication of JPH0263294B2 publication Critical patent/JPH0263294B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28185—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
    • H01L21/2686—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation using incoherent radiation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28202—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/004—Annealing, incoherent light
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/91—Controlling charging state at semiconductor-insulator interface

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • High Energy & Nuclear Physics (AREA)
  • General Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Optics & Photonics (AREA)
  • Electromagnetism (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Formation Of Insulating Films (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Description

【発明の詳細な説明】 Ａ 産業上の利用分野 本発明は、半導体ウエハのSiO2の焼鈍処理に
関する。DETAILED DESCRIPTION OF THE INVENTION A. Field of Industrial Application The present invention relates to the annealing treatment of SiO 2 of semiconductor wafers.

Ｂ 開示の概要 金属酸化物半導体（MOS）ウエハのSiO2膜の
焼鈍処理。流動酸素中にて輻射加熱源で加熱す
る。B Summary of Disclosure Annealing treatment of SiO 2 film of metal oxide semiconductor (MOS) wafer. Heating with a radiant heating source in flowing oxygen.

Ｃ 従来技術 MOSウエハにおけるSiO2層の電子的特性を改
善するため1000℃で相当永く焼鈍することは既知
である。しかし急速焼鈍（アニーリング）につい
ては何ら示されていない。C. Prior Art It is known to anneal SiO 2 layers in MOS wafers at 1000° C. for a considerable period of time to improve their electronic properties. However, there is no mention of rapid annealing.

Ｄ 発明が解決しようとする問題点 SiO2のホール・トラツピングを減らし、放射
強度を上げ、絶縁性を改善したい要求があつた。D Problems to be Solved by the Invention There were demands to reduce hole trapping of SiO 2 , increase radiation intensity, and improve insulation.

Ｅ 問題点を解決するための手段 本発明は強いハロゲン・ランプの輻射でウエハ
を急速加熱し、他の処理工程の分断や永く待つ期
間なしに焼鈍を行なうことができる。E. SUMMARY OF THE INVENTION The present invention provides rapid heating of wafers with intense halogen lamp radiation to effect annealing without the need for other process steps or lengthy waiting periods.

Ｆ 作用 ハロゲン・ランプにより急加熱ができ、ウエハ
上のSiO2の特性が向上する。F Effect A halogen lamp allows rapid heating, improving the properties of SiO 2 on the wafer.

Ｇ 実施例 本発明はMOS回路ウエハのSiO2絶縁膜の特性
をよくするための処理である。第１図でウエハ１
の面上にSiO2絶縁体２があり、この面には後に
導体が付着される。ウエハは水晶板３の上に置か
れ、水晶容器４内に置かれる。入口５から酸素ガ
スが入れられる。ガスは出口６から出る。ランプ
の列７がオンにされるとウエハ１が所望の焼鈍温
度に急速に加熱される。タングステン・ハロゲ
ン・ランプがランプの一例である。G. Embodiment The present invention is a process for improving the characteristics of the SiO 2 insulating film of a MOS circuit wafer. In Figure 1, wafer 1
There is a SiO 2 insulator 2 on the surface of which a conductor will later be deposited. The wafer is placed on a crystal plate 3 and placed in a crystal container 4. Oxygen gas is introduced through the inlet 5. Gas exits through outlet 6. When the row of lamps 7 is turned on, the wafer 1 is rapidly heated to the desired annealing temperature. A tungsten halogen lamp is an example of a lamp.

厚さ100〜1000ÅのSiO2膜の焼鈍は常圧のO2
（酸素）雰囲気中でなされる。好適な温度、時間
は1000℃、100秒程度である。実用上の範囲は10
〜300秒である。100秒が最良である。 Annealing of SiO2 film with a thickness of 100~1000Å is performed using O2 at normal pressure.
(oxygen) atmosphere. The preferred temperature and time are 1000°C and about 100 seconds. Practical range is 10
~300 seconds. 100 seconds is best.

第２図は焼鈍によるホール・トラツピングの減
少効果を示す。MOSキヤパシタ構造におけるホ
ール注入時間の関数としてのフラツトバンド電圧
シフトを示している。フラツトバンド電圧シフト
は、SiO2中のホール・トラツピングの量に比例
している。コントロールと記したカーブは焼鈍前
の高いトラツピングを示す。他のカーブは急加熱
焼鈍（RTA）後のトラツピングを示し、数字は
焼鈍時間（秒）である。特に100秒の場合は劇的
なホール・トラツピングの減少を示し、０のレベ
ルに達している。 Figure 2 shows the effect of annealing on reducing hole trapping. Figure 3 shows the flat band voltage shift as a function of hole injection time in a MOS capacitor structure. The flat band voltage shift is proportional to the amount of hole trapping in SiO2 . The curve labeled control shows high trapping before annealing. The other curves show trapping after rapid heat annealing (RTA) and the numbers are annealing time (seconds). In particular, the case of 100 seconds shows a dramatic decrease in hole trapping, reaching a level of 0.

RTAの前に窒素で前処理するとRTAの焼鈍特
性に改良がみられる。この前処理は例えば窒素中
での永い酸化後焼鈍（POA）等の処理で、シリ
コン−２酸化シリコン相接面に窒素原子を与え
る。例えば1000℃の窒素中で17時間のPOAがな
される。 Pretreatment with nitrogen before RTA improves the annealing properties of RTA. This pretreatment is, for example, a long post-oxidation annealing (POA) in nitrogen to provide nitrogen atoms to the silicon-silicon dioxide interface. For example, POA is performed for 17 hours in nitrogen at 1000°C.

Ｈ 発明の効果 永い時間をかけての焼鈍につきものの汚染や不
所望の拡散等なしに、ホール・トラピングが減
り、輻射強度が増したウエハが簡単な工程で得ら
れる。温度の制御も楽である。H. Effects of the Invention Wafers with reduced hole trapping and increased radiation intensity can be obtained in a simple process without the contamination and undesired diffusion associated with long-term annealing. Controlling the temperature is also easy.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本願実施例の側面図、第２図はホー
ル・トラツピングのグラフである。 １…ウエハ、２…SiO2、５…入口、６…出口、
７…ランプ。 FIG. 1 is a side view of the embodiment of the present application, and FIG. 2 is a graph of hole trapping. 1... Wafer, 2... SiO 2 , 5... Inlet, 6... Outlet,
7...Lamp.

Claims (1)

【特許請求の範囲】[Claims] １ 半導体ウエハ上のSiO2膜の特性を改善する
ために、上記ウエハを酸素ガス中に置いて輻射加
熱源により1000℃に加熱し100秒間焼鈍するウエ
ハ処理法。1. A wafer processing method in which the wafer is placed in oxygen gas, heated to 1000°C by a radiant heating source, and annealed for 100 seconds in order to improve the characteristics of the SiO 2 film on the semiconductor wafer.
JP7455685A 1984-07-30 1985-04-10 Method of treating wafer Granted JPS6142145A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/635,391 US4585492A (en) 1984-07-30 1984-07-30 Rapid thermal annealing of silicon dioxide for reduced hole trapping
US635391 1984-07-30

Publications (2)

Publication Number Publication Date
JPS6142145A JPS6142145A (en) 1986-02-28
JPH0263294B2 true JPH0263294B2 (en) 1990-12-27

Family

ID=24547617

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7455685A Granted JPS6142145A (en) 1984-07-30 1985-04-10 Method of treating wafer

Country Status (4)

Country Link
US (1) US4585492A (en)
EP (1) EP0170848B1 (en)
JP (1) JPS6142145A (en)
DE (1) DE3580417D1 (en)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4661177A (en) * 1985-10-08 1987-04-28 Varian Associates, Inc. Method for doping semiconductor wafers by rapid thermal processing of solid planar diffusion sources
US4814291A (en) * 1986-02-25 1989-03-21 American Telephone And Telegraph Company, At&T Bell Laboratories Method of making devices having thin dielectric layers
US4784975A (en) * 1986-10-23 1988-11-15 International Business Machines Corporation Post-oxidation anneal of silicon dioxide
US4927770A (en) * 1988-11-14 1990-05-22 Electric Power Research Inst. Corp. Of District Of Columbia Method of fabricating back surface point contact solar cells
US4933022A (en) * 1988-11-14 1990-06-12 Board Of Trustees Of The Leland Stanford Univ. & Electric Power Research Institute Solar cell having interdigitated contacts and internal bypass diodes
US4933021A (en) * 1988-11-14 1990-06-12 Electric Power Research Institute Monolithic series-connected solar cells employing shorted p-n junctions for electrical isolation
US5264724A (en) * 1989-02-13 1993-11-23 The University Of Arkansas Silicon nitride for application as the gate dielectric in MOS devices
US4962065A (en) * 1989-02-13 1990-10-09 The University Of Arkansas Annealing process to stabilize PECVD silicon nitride for application as the gate dielectric in MOS devices
EP0459763B1 (en) * 1990-05-29 1997-05-02 Semiconductor Energy Laboratory Co., Ltd. Thin-film transistors
CN1052569C (en) * 1992-08-27 2000-05-17 株式会社半导体能源研究所 Semiconductor device and method for forming the same
JPH0766420A (en) * 1993-08-31 1995-03-10 Matsushita Electric Ind Co Ltd Working method for thin film
JP3518122B2 (en) * 1996-01-12 2004-04-12 ソニー株式会社 Method for manufacturing semiconductor device
US5904575A (en) * 1997-02-14 1999-05-18 Advanced Micro Devices, Inc. Method and apparatus incorporating nitrogen selectively for differential oxide growth
TW388095B (en) * 1997-05-20 2000-04-21 United Microelectronics Corp Method for improving planarization of dielectric layer in interconnect metal process
JP3754234B2 (en) 1998-04-28 2006-03-08 インターナショナル・ビジネス・マシーンズ・コーポレーション Method for forming oxide film on side wall of gate structure
EP1340247B1 (en) * 2000-09-19 2010-11-24 Mattson Technology Inc. Method of forming dielectric films
GB2370043A (en) * 2000-12-12 2002-06-19 Mitel Corp Chemical treatment of silica films
SG110043A1 (en) * 2003-05-07 2005-04-28 Systems On Silicon Mfg Co Pte Rapid thermal annealing of silicon structures
US7632729B2 (en) * 2006-09-27 2009-12-15 Taiwan Semiconductor Manufacturing Co., Ltd. Method for semiconductor device performance enhancement
US8693553B2 (en) * 2007-12-28 2014-04-08 Nokia Corporation Methods, apparatuses, and computer program products for adaptive synchronized decoding of digital video

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
BE674294A (en) * 1964-12-28
US3615873A (en) * 1969-06-03 1971-10-26 Sprague Electric Co Method of stabilizing mos devices
US4431900A (en) * 1982-01-15 1984-02-14 Fairchild Camera & Instrument Corporation Laser induced flow Ge-O based materials

Also Published As

Publication number Publication date
EP0170848B1 (en) 1990-11-07
DE3580417D1 (en) 1990-12-13
EP0170848A2 (en) 1986-02-12
EP0170848A3 (en) 1987-07-01
JPS6142145A (en) 1986-02-28
US4585492A (en) 1986-04-29

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