JPH047864A - Package for semiconductor device - Google Patents
Package for semiconductor deviceInfo
- Publication number
- JPH047864A JPH047864A JP10914790A JP10914790A JPH047864A JP H047864 A JPH047864 A JP H047864A JP 10914790 A JP10914790 A JP 10914790A JP 10914790 A JP10914790 A JP 10914790A JP H047864 A JPH047864 A JP H047864A
- Authority
- JP
- Japan
- Prior art keywords
- lead terminal
- package
- metallized
- package side
- bonded
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 10
- 238000005219 brazing Methods 0.000 claims abstract description 9
- 239000000463 material Substances 0.000 claims description 8
- 239000002184 metal Substances 0.000 abstract description 5
- 238000004299 exfoliation Methods 0.000 abstract 3
- 239000000945 filler Substances 0.000 abstract 3
- 238000000034 method Methods 0.000 abstract 1
- 239000000853 adhesive Substances 0.000 description 4
- 230000001070 adhesive effect Effects 0.000 description 4
- 230000007547 defect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005452 bending Methods 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置用パッケージに関し、特に半田等
の接着剤を使用して搭載されるパッケージに関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a package for a semiconductor device, and particularly to a package mounted using an adhesive such as solder.
従来のパッケージは、第３図に示すように、半導体素子
を搭載する為のヒートシンク３と、このヒートシンクと
機械的に接着されたパッケージ側面部４と、このパッケ
ージ側面部上に形成した電気信号伝達用のメタライズ部
と、このメタライズ部にロー材５により接着されたリー
ド端子ｌで構成されている。As shown in FIG. 3, a conventional package includes a heat sink 3 for mounting a semiconductor element, a package side surface 4 mechanically bonded to the heat sink, and an electrical signal transmission section formed on the package side surface. It consists of a metallized part and a lead terminal l bonded to this metallized part with brazing material 5.
上記のリード端子の表面にメツキさせた金属と、ロー材
２メタライズ部は同一種類の金属であり、リード端子と
メタライズ部は強固に接着されている。パッケージ側面
部はセラミックでできるいる為、パッケージ側面部とメ
タライズ部との接着強度は、リード端子とメタライズ部
との接着強度よりも弱い。The metal plated on the surface of the lead terminal and the brazing material 2 metallized portion are of the same type of metal, and the lead terminal and the metallized portion are firmly bonded. Since the package side surface is made of ceramic, the adhesive strength between the package side surface and the metallized portion is weaker than the adhesive strength between the lead terminal and the metallized portion.
この従来のパッケージは、半導体装置の電気的特性を測
定する際、リード端子に加わる機械的ストレスによりパ
ッケージ側面部とメタライズ部が剥離し、メタライズ部
の腐蝕を侵行させる問題があった。This conventional package has a problem in that when measuring the electrical characteristics of a semiconductor device, mechanical stress applied to the lead terminal causes the side surface of the package to separate from the metallized portion, resulting in corrosion of the metallized portion.
本発明の半導体装置用パッケージは、パッケージ側面の
リード端子下部に凹部を形成し、リード端子とメタライ
ズパターンを接着する際、この凹部にロー材を流し込ん
でメタライズパターンとリード端子とを電気的に接着し
ている。In the semiconductor device package of the present invention, a recess is formed below the lead terminal on the side surface of the package, and when bonding the lead terminal and the metallized pattern, a brazing material is poured into the recess to electrically bond the metallized pattern and the lead terminal. are doing.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の半導体装置用パッケージの一実施例の
断面図である。ヒートシンク３にパッケージ側面部４を
機械的に接着し、先にパッケージ側面部に機械的に接着
されているメタライズ部２と、リード端子１をパッケー
ジ側面部のリード端子下部に設けた凹部すにロー材５を
流し、込み電気的に接着している。FIG. 1 is a sectional view of an embodiment of a package for a semiconductor device according to the present invention. The package side surface 4 is mechanically bonded to the heat sink 3, and the metallized portion 2, which has been mechanically bonded to the package side surface, and the lead terminal 1 are inserted into the recess provided below the lead terminal on the package side surface. The material 5 is poured and electrically bonded.
第２図は、第二の実施例の断面図である。パッケージ側
面部４にリード端子挿入用凹部を設け、リード端子１を
挿入しさらにロー材５を流し込むことにより、リード端
子の弓っ張り強度の向上を図っている。FIG. 2 is a sectional view of the second embodiment. A recess for inserting a lead terminal is provided in the side surface portion 4 of the package, the lead terminal 1 is inserted therein, and a brazing material 5 is poured into the recess, thereby improving the bending strength of the lead terminal.
以上説明したように本発明は、リード端子下部に凹部な
作ることにより、リード端子を、ノくツケージ側面上に
形成したメタライズ部に接着する際、十分なロー材を用
いられる為、メタライズとパッケージ側面との接着強度
を上げ、半導体装置の電気的特性を測定する際に、リー
ド端子に加わる機械的ストレスにより生じるメタライズ
とノくツケージ側面の剥離を防止できる効果がある。As explained above, in the present invention, by creating a concave portion at the bottom of the lead terminal, sufficient brazing material can be used when bonding the lead terminal to the metallized portion formed on the side surface of the socket cage. It has the effect of increasing the adhesive strength with the side surface and preventing peeling of the metallization and the side surface of the cage caused by mechanical stress applied to the lead terminal when measuring the electrical characteristics of a semiconductor device.
従来のパッケージでは１０％程度の不良が発生していた
が本発明のバ４ケージでは不良は発生しない。In conventional packages, about 10% of defects occur, but in the package of the present invention, no defects occur.
第１図は本発明の第一の実施例の断面図、第２図は第２
の実施例の断面図、第３図（ａ） 、 （ｂ）は従来の
パッケージ図である。
図において、
１・・・・・・リード端子、２・・・・・・メタライズ
部、３・・・・・・ヒートシンク、４・・・・・・パッ
ケージ側面部、５・・・・・・ロー材、６・・・・・・
リード端子下部凹部、７・・・・・・リード挿入用凹部
。FIG. 1 is a cross-sectional view of the first embodiment of the present invention, and FIG. 2 is a cross-sectional view of the second embodiment.
3(a) and 3(b) are diagrams of a conventional package. In the figure, 1...Lead terminal, 2...Metallized part, 3...Heat sink, 4...Package side part, 5... Row material, 6...
Lead terminal lower recess, 7... Recess for lead insertion.
Claims (1)
クに接着されたパッケージ側面部と、パッケージ側面部
上に設けたメタライズ部と、メタライズ部上に接着され
たリード端子と、リード端子下部に作られたパッケージ
側面上の凹部が前記リード端子と、ロー材により接着さ
れたことを特徴とする半導体装置用パッケージ。A heat sink for mounting a semiconductor element, a side surface of the package bonded to the heat sink, a metallized portion provided on the side surface of the package, a lead terminal bonded to the metallized portion, and a side surface of the package formed below the lead terminal. A package for a semiconductor device, characterized in that an upper recessed portion is bonded to the lead terminal using a brazing material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10914790A JPH047864A (en) | 1990-04-25 | 1990-04-25 | Package for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10914790A JPH047864A (en) | 1990-04-25 | 1990-04-25 | Package for semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH047864A true JPH047864A (en) | 1992-01-13 |
Family
ID=14502807
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10914790A Pending JPH047864A (en) | 1990-04-25 | 1990-04-25 | Package for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH047864A (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5089245A (en) * | 1973-12-12 | 1975-07-17 | ||
| JPS587345B2 (en) * | 1980-09-22 | 1983-02-09 | 株式会社 阪村機械製作所 | Centrifugal deoiling equipment for small products |
| JPS58110066A (en) * | 1981-12-23 | 1983-06-30 | Nec Kyushu Ltd | Package for semiconductor device |
| JPS6236392A (en) * | 1985-08-09 | 1987-02-17 | Nippon Ester Co Ltd | Organic phosphorus compound |
| JPS63186451A (en) * | 1987-01-29 | 1988-08-02 | Sumitomo Electric Ind Ltd | Integrated circuit package |
-
1990
- 1990-04-25 JP JP10914790A patent/JPH047864A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5089245A (en) * | 1973-12-12 | 1975-07-17 | ||
| JPS587345B2 (en) * | 1980-09-22 | 1983-02-09 | 株式会社 阪村機械製作所 | Centrifugal deoiling equipment for small products |
| JPS58110066A (en) * | 1981-12-23 | 1983-06-30 | Nec Kyushu Ltd | Package for semiconductor device |
| JPS6236392A (en) * | 1985-08-09 | 1987-02-17 | Nippon Ester Co Ltd | Organic phosphorus compound |
| JPS63186451A (en) * | 1987-01-29 | 1988-08-02 | Sumitomo Electric Ind Ltd | Integrated circuit package |
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