JPH0478643U - - Google Patents
Info
- Publication number
- JPH0478643U JPH0478643U JP12280690U JP12280690U JPH0478643U JP H0478643 U JPH0478643 U JP H0478643U JP 12280690 U JP12280690 U JP 12280690U JP 12280690 U JP12280690 U JP 12280690U JP H0478643 U JPH0478643 U JP H0478643U
- Authority
- JP
- Japan
- Prior art keywords
- operand
- subtraction
- exponent part
- inputting
- mantissa
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
- 238000010606 normalization Methods 0.000 description 1
Description
第１図は本考案浮動小数点演算回路の一実施例
の概略構成図、第２図は従来の浮動小数点演算回
路の概略構成図である。
１……第１入力レジスタ（第１入力手段）、２
……第２入力レジスタ（第２入力手段）５……第
１シフタ（第１シフト手段）、６……第２シフタ
（第２シフト手段）、７……演算回路（演算手段
）、８……乗算器、９……正規化回路、１０……
丸め回路、１１……加減算器（減算手段）、１２
……符号レジスタ（記憶手段）。
FIG. 1 is a schematic diagram of an embodiment of a floating point arithmetic circuit according to the present invention, and FIG. 2 is a schematic diagram of a conventional floating point arithmetic circuit. 1...first input register (first input means), 2
...Second input register (second input means) 5...First shifter (first shift means), 6...Second shifter (second shift means), 7... Arithmetic circuit (arithmetic means), 8... ...Multiplier, 9...Normalization circuit, 10...
Rounding circuit, 11... Addition/subtraction device (subtraction means), 12
...Sign register (storage means).
Claims (1)
をオペランドとして入力し、オペランド間で演算
を行う浮動小数点演算回路において、 第１オペランドを入力する第１入力手段と、第
２オペランドを入力する第２入力手段と、第１入
力手段に入力された第１オペランドの指数部と第
２入力手段に入力された第２オペランドの指数部
との減算を被減数の入れ替えが可能に行う減算手
段と、該減算手段により第１オペランドの指数部
から第２オペランドの指数部を減算したときの減
算結果の符号情報を記憶する記憶手段と、減算手
段での減算結果及び記憶手段に記憶された符号情
報に従つて、第１オペランドの仮数部をシフトす
る第１シフト手段と、減算手段での減算結果及び
記憶手段に記憶された符号情報に従つて、第２オ
ペランドの仮数部をシフトする第２シフト手段と
、第１シフト手段から第１オペランドの仮数部を
入力し第２シフト手段から第２オペランドの仮数
部を入力してこれら仮数部の演算を行う演算手段
とを備え、前記減算手段は、前記記憶手段に記憶
された符号情報が負の場合に第２オペランドの指
数部から第１オペランドの指数部を減算すること
を特徴とする浮動小数点演算回路。[Claims for Utility Model Registration] In a floating point arithmetic circuit that receives a numerical value consisting of an exponent part and a mantissa part expressed as an absolute value as an operand and performs an operation between the operands, a first input means for inputting a first operand; , a second input means for inputting the second operand, and subtraction between the exponent part of the first operand inputted to the first input means and the exponent part of the second operand inputted to the second input means, with the minuends swapped. a storage means for storing sign information of the subtraction result when the exponent part of the second operand is subtracted from the exponent part of the first operand by the subtraction means; and a storage means for storing the subtraction result by the subtraction means. a first shifting means for shifting the mantissa part of the first operand according to the sign information stored in the storage means; and a calculation means for inputting the mantissa part of the first operand from the first shifting means, inputting the mantissa part of the second operand from the second shifting means, and calculating the mantissa parts. . A floating point arithmetic circuit, wherein the subtraction means subtracts the exponent part of the first operand from the exponent part of the second operand when the sign information stored in the storage means is negative.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12280690U JPH0478643U (en) | 1990-11-22 | 1990-11-22 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12280690U JPH0478643U (en) | 1990-11-22 | 1990-11-22 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0478643U true JPH0478643U (en) | 1992-07-09 |
Family
ID=31870556
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12280690U Pending JPH0478643U (en) | 1990-11-22 | 1990-11-22 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0478643U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01232423A (en) * | 1988-03-11 | 1989-09-18 | Fujitsu Ltd | Arithmetic circuit |
-
1990
- 1990-11-22 JP JP12280690U patent/JPH0478643U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01232423A (en) * | 1988-03-11 | 1989-09-18 | Fujitsu Ltd | Arithmetic circuit |
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