JPH07261984A - Arithmetic method and unit - Google Patents

Abstract

PURPOSE:To provide an arithmetic method and an arithmetic unit for performing multiplication with signs by the irreducible minimum size and processing procedure of the arithmetic unit of a register or the like without using a unit of operation with sign. CONSTITUTION:In this arithmetic unit 10 provided with a register means 2 for storing a multiplier and a multiplicand and an arithmetic means 3 for performing multiplication based on the multiplier and the multiplicand, the arithmetic means 3 performs the multiplication of integers by providing a without-the-sign operation part for performing the multiplication without the sign for not performing a sign operation to the multiplier of (n) bits {(n) is a natural number} and the multiplicand of (n) bits and generating the multiplier without the sign and the multiplicand without the sign, a multiplication part for calculating the multiplied result of 2n bits based on the multiplier without the sign and the multiplicand without the sign and a subtraction part for subtracting the multiplicand from the register where the value of the upper (n) bits of the multiplied result is stored when the multiplier is provided with a negative sign and subtracting the multiplier from the register where the value of the upper (n) bits of the multiplied result is stored when the multiplicand is provided with the negative sign.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic unit such as a microcomputer, and more particularly to improvement of an arithmetic unit for multiplication.

With the recent development of semiconductor technology, microchip arithmetic units are used in various fields. In particular, since it is real-time processing, a technology that can contribute to speeding up of arithmetic processing is important. On the other hand, it is also required to satisfy compact design such as microchip area and program size reduction. In particular,
In the digital signal processing technique, it is necessary to repeatedly perform similar calculations such as multiplication, and a slight reduction in the calculation procedure leads to a significant reduction in the calculation time of the entire system.

Therefore, there is a need for a technique for sharing common processes as much as possible so as to greatly improve the calculation efficiency with a minimum processing procedure.

[0004]

2. Description of the Related Art Generally, digital operations such as multiplication are performed by operating an arithmetic unit (accumulator or the like) based on a multiplier or a multiplicand stored in a register by an arithmetic unit such as a central processing unit.

Here, when dealing with integers, whether the numerical value is positive or negative becomes a problem. A sign operation is performed by preparing a bit, which is a sign bit, for these multipliers, which specifies whether the multiplier is positive or negative, and performing an integer operation while determining the sign bit state, that is, whether the numerical value is positive or negative, including this sign. In addition, a code bit is treated as a part of a numerical value, that is, a positive numerical value whose MSB is "1", and a simple binary arithmetic operation is performed is called an unsigned arithmetic operation.

In the conventional signed arithmetic, since the multiplication is performed while determining whether the numerical value including the sign bit is positive or negative, an arithmetic unit for performing signed arithmetic different from the unsigned arithmetic is provided. . If a signed arithmetic unit is not provided, the sign information is stored in another register before the operation, converted to an unsigned value, then the unsigned multiplication is performed, and the sign of the operation result is inverted after the operation. Was.

[0007]

However, as described above, in an arithmetic unit that handles a code in multiplication or division, a dedicated signed arithmetic unit must be provided separately from the unsigned arithmetic unit, and therefore the arithmetic operation is performed as a function. Since the arithmetic units that perform similar functions of processing are provided in duplicate, the overhead of the arithmetic units is large. Further, even when the signed arithmetic unit is not used, there is a waste of increasing the work area for determining the code flag and storing the code due to the operation of the code.

[0008] These problems further adversely affect the overall performance in the recent high-level arithmetic processing which doubles the data field and makes heavy use of floating point data.

Therefore, an object of the present invention is to perform unsigned multiplication and signed multiplication with the same arithmetic unit, and to use the signed arithmetic unit without using the minimum size of arithmetic units such as registers and the minimum. An object of the present invention is to provide an arithmetic method and an arithmetic device for performing signed multiplication in a processing procedure.

[0010]

In order to achieve the above object, the invention according to claim 1 uses a register means (2) and an arithmetic means (3) to multiply an n-bit multiplier (n is a natural number) and In an arithmetic method for performing 2n-bit integer arithmetic with an n-bit multiplicand, an unsigned arithmetic step of generating an unsigned multiplier and an unsigned multiplicand by performing unsigned multiplication without performing a sign operation on the multiplier and the multiplicand (step S1)
And a multiplication step of calculating a 2n-bit multiplication result based on the unsigned multiplier and the unsigned multiplicand (step S2)
And the multiplier has a negative sign, the upper n of the multiplication result
The multiplicand is subtracted from the value of the bit, and when the multiplicand has a negative sign, the multiplication step is performed by subtracting the multiplier from the value of the upper n bits of the multiplication result (steps S4, 6). It is characterized by performing.

The invention according to claim 2 is an arithmetic unit comprising: a register means (2) for storing a multiplier and a multiplicand; and an arithmetic means (3) for multiplying based on the multiplier and the multiplicand. A means (3) performs an unsigned multiplication that does not perform a sign operation on an n-bit multiplier (n is a natural number) and an n-bit multiplicand, and generates an unsigned multiplier and an unsigned multiplicand; A multiplication unit which calculates a 2n-bit multiplication result based on the unmultiplied multiplier and the unsigned multiplicand; and when the multiplier has a negative sign, subtracts the multiplicand from the register in which the value of the upper n bits of the multiplication result is stored, When the multiplicand has a negative sign, a subtraction unit that subtracts the multiplier from the register that stores the value of the upper n bits of the multiplication result is used to perform integer multiplication.

[0012]

The signed multiplicand, which is a signed numerical value, is X, the signed multiplier is Y, and the absolute values thereof are the unsigned multiplicand x and the unsigned multiplicand y, respectively.

Since the input values (X, Y) are used as they are for performing unsigned multiplication, X and Y are treated as unsigned numerical values. In the case of a numerical field to be handled and n bits, when X and Y are expressed as unsigned numerical values, the formula (1) is obtained.

Positive: X = x, Y = y Negative: X = 2 ⁿ −x, Y = 2 ⁿ −y (1) For example, if the bit length of n is 16 bits, x ,
y is 16-bit length data.

Positive / negative of the numerical value judged by the signs of X and Y
Is divided into the following cases. When both X and Y are positive X × Y = x × y (2) The result of equation (2) is the same as the signed multiplication result, and
This is an ordinary operation.When one of X and Y is negative When either X or Y is negative due to the exchange law of multiplication
Is sufficient, so let's consider the case where Y is negative.
Get

X × Y = x × (2 ⁿ −y) = 2 ⁿ × x−x × y (3) In the multiplication of n bits, the multiplication result has a total length of 2n bits. Hereinafter, the n bits on the MSB side are referred to as the upper part, and L
The n bits on the SB side are called the lower part.

In the calculation of the lower part, the lower part of the first term on the right side of the equation (3) is zero. Therefore, if only the lower part is taken out, the second term on the right side of the equation (3), that is, −x × y. Become. Since the upper part does not affect the lower part in any way, if the upper part is ignored, the lower part of the unsigned operation result has the same value as the result of the signed operation.

In the calculation of the upper part, the result of the unsigned operation is the value on the right side of the equation (3), that is, 2 ⁿ × x−x × y.
However, since the original calculation result is −x × y, x must be subtracted from the upper part.

At this time, the multiplicand X is a positive numerical value, and X
= X, X is subtracted from the upper part (unsigned numbers are subtracted from each other). The operation result gives the same operation result as the signed operation result.

When X is negative, Y is subtracted from the upper part of the multiplication result by the equation (3). When both X and Y are negative X × Y = (2 ⁿ −x) × (2 ⁿ −y) = 2 ²ⁿ −2 ⁿ × (x + y) + x × y (4) In the calculation of the lower part, Since the lower part of the first term and the second term on the right side of the equation (4) is zero, the numerical value of only the lower part is x × y of the third term. The first term and the second term on the right side of Expression (4), which are the numerical values of the upper part, have no influence on the numerical values of the lower part. Therefore, the numerical value of the lower part is the formula (4)
It becomes the third term on the right side, that is, x × y, which is the same operation result as the signed operation result.

In the calculation of the upper part, the unsigned operation results are the first and second terms of the equation (4), and the original operation result is only the third term. Must be added.

At this time, since X = -x and Y = -y, X and Y are subtracted from the higher order part. The calculation result obtained by this calculation process is 2 ²ⁿ + x × y of the first term and the third term of the formula (4). However, the first term is out of the storage range of the calculation result of 2n bit length and is ignored. You can

Therefore, this operation result gives the same operation result as the signed multiplication result. According to this procedure, even if any register configuration is adopted, an arithmetic method capable of performing an integer arithmetic operation only by an unsigned arithmetic operation.

Further, if this method is applied to an arithmetic unit having only an unsigned arithmetic unit, the operation of the code is not performed,
Integer arithmetic can be achieved.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of an arithmetic unit according to the present invention will be described with reference to the drawings. FIG. 1 shows the configuration of an embodiment of the present invention. As shown in FIG. 1, the arithmetic unit 10 of the present embodiment controls a control unit 1 according to an instruction code of a program supplied from the outside, a multiplier read from an external memory 4,
A register unit 2 having a register that temporarily stores a multiplicand, a calculation result, and the like, and a calculator 3 that performs a calculation specified by the control unit 1 based on the multiplier, the multiplicand, and the like supplied from the register unit 2. It is equipped with.

The register unit 2 is connected to a memory 4 such as a storage device such as a RAM or a ROM so that data can be input / output, and includes a plurality of registers R _{1 to} R _m (m is a natural number). . Each register has a 2n-bit field and can store a multiplication result of an n-bit multiplier and a multiplicand. Similarly, the computing unit 3 is capable of computing n-bit multipliers and multiplicands and 2n-bit additions and subtractions without causing overflow.

Next, the operation will be described based on the flowchart of FIG. 2 and the specific example of FIG. In FIG. 3, B represents a binary number, and a numerical value without a symbol at the end of the numeral indicates a decimal number. According to the program stored in the memory 4 of the arithmetic unit 10, the arithmetic unit 10 advances the arithmetic processing.

First, the control unit 1 of the arithmetic unit 10 reads the multiplicand X and the multiplier Y from the memory 4, and outputs the unsigned multiplicand x and the multiplier y including the sign bit as they are in the register R ₁ and the register R of the register unit 2. Store in ₂ (step S1).

For example, as shown in FIG. 3, the multiplier X (for example, "3") and the multiplicand Y (for example, "-2") which are the basis of the calculation are supplied from the memory 4 or the like. Are stored in the internal registers R ₁ and R ₂ of the arithmetic unit 10.

At this time, the multiplicand X and the multiplier Y are irrespective of whether the numerical values are positive or negative, that is, the sign bit is effective "1",
Regardless of invalid '0', the sign bit is also included in the numerical value and stored in the register. In the figure, n bits (n is a natural number:
Here, it is 4 bits. ) Is stored as it is in the register R ₁ as the unsigned multiplicand x (that is, '3'), and the n-bit multiplier Y is the unsigned multiplier y.
(That is, '14') is stored in the register R ₂ .

Next, the control unit 1 instructs the multiplier 3 to
An unsigned operation based on the values stored in the registers R ₁ and R ₂ is performed. In FIG. 3, registers R ₁ and R ₂
The value of is multiplied by unsigned multiplication in the arithmetic unit 3, and is stored in the register R ₃ as the unsigned multiplication result z ('3 × 14 = 42').

Further, when the multiplicand X has a negative sign (step S3: YES), the unsigned multiplication result z
Subtract the multiplier Y from the value of the upper part of the upper n bits of
This is stored again in the register R ₃ (step S4).

When the multiplier Y has a negative sign (step S5: YES), the multiplicand X is subtracted from the value of the upper part of the upper n bits of the unsigned multiplication result z,
Here, since the multiplier Y is a negative number ('-2'), the multiplicand X'3 'is subtracted from the upper 4 bits of the multiplication result z,
The calculation result is stored in the register R ₃ (step S6).

As a result, the operation result stored in the register R ₄ becomes "-6" when judged as signed data, and when the operation is performed by the signed arithmetic unit ('3 ×-
2 = −6 ′).

As described above, according to the present embodiment, the signed operation can be performed by the operation procedure using only the unsigned multiplier, and the operator 3 can be effectively used. Further, as can be seen from the usage status of each register, no saving operation or bit inverting operation regarding the sign bit is required, and the labor in the procedure of arithmetic processing can be saved. Other Modifications Various modifications are possible without being limited to the above embodiment of the present invention.

For example, in the above embodiment, the arithmetic processing of the microprocessor is assumed, but if it is an arithmetic device such as a digital signal processor that frequently uses integer multiplication,
The present invention can be applied.

[0037]

As described above, according to the first aspect of the present invention, the signed operation can be performed by the unsigned operation procedure, and the number of procedures can be reduced, so that the processing speed is improved. Can contribute to.

According to the second aspect of the present invention, since the arithmetic operation of the positive and negative integers can be performed in a small procedure without using the signed arithmetic unit, the size of one multiplication unit can be reduced. In particular, in recent years when microchips have become smaller and more dense, the fact that the area of the multiplier, which occupies a relatively large area, is reduced to about half has great significance in terms of circuit economy.

[Brief description of drawings]

FIG. 1 is a block diagram showing an arithmetic unit according to an embodiment of the present invention.

FIG. 2 is a flowchart showing a calculation operation of the calculation device according to the embodiment.

FIG. 3 is an explanatory diagram showing an example of actual calculation of numerical values in a register.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Control part 2 ... Register part 3 ... Arithmetic unit 4 ... Memory 10 ... Arithmetic device of this invention

Claims (2)

[Claims] 1. Register means (2) and arithmetic means (3)
Using an n-bit (n is a natural number) multiplier and an n-bit multiplicand to perform an integer operation of 2n bits, the unsigned multiplication is performed on the multiplier and the multiplicand without performing a sign operation, An unsigned operation step (step S1) of generating an unsigned multiplier and an unsigned multiplicand; and 2 based on the unsigned multiplier and the unsigned multiplicand.
A multiplication step of calculating an n-bit multiplication result (step S
2) and, when the multiplier has a negative sign, the multiplicand is subtracted from the value of the upper n bits of the multiplication result, and when the multiplicand has a negative sign, the higher n bits of the multiplication result A subtraction step of subtracting the multiplier from the value (step S4,
6) An arithmetic method characterized by performing an integer multiplication by and. 2. An arithmetic unit comprising: a register means (2) for storing a multiplier and a multiplicand; and an arithmetic means (3) for performing multiplication based on the multiplier and the multiplicand, wherein the arithmetic means (3) is n. An unsigned arithmetic unit that generates an unsigned multiplier and an unsigned multiplicand by performing unsigned multiplication without performing a sign operation on the multiplier of bits (n is a natural number) and the n-bit multiplicand, and the unsigned multiplier and the sign None based on multiplicand 2
a multiplication unit that calculates an n-bit multiplication result; and, if the multiplier has a negative sign, subtracts the multiplicand from a register that stores the value of the upper n bits of the multiplication result, and the multiplicand has a negative sign. And a subtraction unit that subtracts the multiplier from a register that stores the value of the upper n bits of the multiplication result, the integer multiplication is performed.