JPH06180640A - Device and method for division - Google Patents

Abstract

PURPOSE:To cope with optional divisors and dividends by providing a calculating means for obtaining the reciprocal of the divisor in a decimal number, a means for multiplying an arithmetic result and the dividend together and the means for deleting only the number of digits of the arithmetic result from multiplied result. CONSTITUTION:This device is provided with a filter circuit 101 for deleting the low- order bits of the dividend based on the filter value of a prime number resolver 102, the resolver 102 for obtaining the power of two from the inputted divisor, obtaining its exponent as the filter value to be inputted to the filter circuit 101, deleting only the value of the exponent of the power of two within the low-order bits of the inputted divisor and obtaining the remaining bits as the input value of a reciprocal computing element 103, the computing element 103 for obtaining the filter value in order to obtain a divisor result from the result of the multiplication for obtaining the reciprocal of a value inputted from the resolver 102 as a multiplier to be inputted to a multiplier 104, the multiplier 104 for multiplying the multiplier of the computing element 103 and the multiplicand of the filter circuit 101 together and the filter circuit 105 for deleting the low-order bits of the multiplied result of the multiplier 104 based arm the filter value of the computing element 103 and obtaining a divided result.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a division apparatus and method, and more particularly to a division apparatus and method for performing a division operation using a multiplier.

[0002]

2. Description of the Related Art Generally, a binary divisor has a divisor of 2
It is known that in the case of a power of, the lower digit of the dividend is deleted by the exponent of a power of 2 to obtain the division result.

If the divisor is not a power of 2, the division result is previously stored in a ROM (Read Only Mem).
ory) and the like, and the dividend is input to the memory so that the division result can be obtained.

[0004]

However, in the above means, a memory for storing the operation result is required only for performing the division operation, and a circuit for controlling the memory is required. Therefore, the circuit becomes complicated and the number of elements constituting the circuit increases. Further, since it takes time to access the memory, it takes time to obtain the division result.

Further, the conventional means has a drawback that the division result can be obtained only with the contents stored in the memory, and the change of the divisor cannot be dealt with.

[0006]

To this end, the present invention provides a circuit configuration that corresponds to arbitrary divisors and dividends and that obtains the division result by inputting the divisors and dividends.

The present invention is characterized in that a multiplier is used to perform a division operation. It comprises arithmetic means for obtaining the reciprocal of the divisor as a decimal number, means for multiplying the arithmetic result by the dividend, and means for deleting from the multiplication result by the number of digits of the arithmetic result.

Further, in order to simplify the arithmetic circuit in the subsequent stage, means for obtaining a power factor of 2 included in the divisor in advance, and lower digits of the divisor and dividend are included in the power factor of 2 obtained by the means. A means for dividing by a power of 2 is provided by deleting only the exponents that are stored.

With the above configuration, any divisor and dividend can be dealt with, and since a memory for storing the divisor result is not required, the circuit can be simplified and the arithmetic processing can be speeded up.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings.

(Embodiment 1) FIG. 1 shows a block diagram of a divider according to the present invention. FIG. 1 shows the flow from the input of the divisor and the dividend to the divider to the obtaining of the division result. In the figure, 101 is a filter circuit (1) that removes the lower bits of the dividend based on the filter value that is input from the prime number decomposer 102, and 102 is a power of 2 that is calculated from the input divisor, and the exponent is the filter circuit. (1) 10
A prime number decomposer that obtains the filter value input to 1 and deletes only the exponent value of the power of 2 of the lower bits of the input divisor and obtains the remaining bits as the input value of the reciprocal calculator 103, 103 is a multiplier In order to obtain the reciprocal of the value input from the prime factorization unit 102 as a multiplier input to the multiplier 104, and also to obtain the divisor result from the multiplication result obtained from the multiplier 104, the filter circuit (2) 10
Inverse calculator for obtaining the filter value to be input to 5
Reference numeral 04 is a multiplier for multiplying the multiplier given by the reciprocal calculator 103 and the multiplicand given by the filter circuit (1) 101, and 105 is the multiplication obtained by the multiplier 104 based on the filter value given by the reciprocal calculator 103. It is a filter circuit (2) that deletes the lower bits of the result and obtains the division result. Filter circuit (1) 101 and prime number decomposer 102
By providing, the division by the power of 2 included in the divisor in advance is performed by deleting the lower bits of the divisor and the dividend, and the arithmetic processing in the subsequent stage can be simplified.

FIG. 2 shows a detailed block diagram of the prime number decomposer 102. When the divisor is input to the prime number decomposer 102, its value is temporarily stored in the divisor register 108. The value stored in the divisor register 108 is input to the priority encoder (1) 109 and the filter circuit (3) 111. To the priority encoder (1) 109,
The high-order bit and the low-order bit of the divisor register 108 are inverted and input, and as a result, the 1st bit of the value stored in the divisor register 108 when viewed from the high-order bit is "1".
Priority encoder (1) 10
9 results. In the subtractor (1) 110, the number of digits of the divisor input in advance is represented by a binary number,
For example, if there are 16 digits, “1111” is set, and from that value, the priority encoder (1) 109 is set.
Delete the value obtained from. As a result, divisor register 1
It is possible to find the number of digits of "0" consecutive in the lower bits of the value stored in 08, that is, the power of 2 included in the divisor. The value obtained by the subtracter (1) 110 is used as a filter value in the filter circuit (1) 101.
And the filter circuit (3) 111.

FIG. 3 shows a detailed block diagram of the filter circuit (1) 101, the filter circuit (2) 104, and the filter circuit (3) 111. In the filter circuit (1) 101, the filter circuit (2) 104, and the filter circuit (3) 111, the deletion register 106 temporarily stores information about how many lower bits of the input value should be deleted. Further, the selector 107 adds the value stored in the deletion register 106 to the number of bits to be output, selects the bit corresponding to the obtained value from the input value, and outputs it. For example, when “0011” is set in the deletion register 106, the output value of bit 0 is the value corresponding to the third bit of the input value, and the output value of bit 1 is the fourth bit of the input value. The value corresponding to is output. That is, the filter circuit (1) 101,
Filter circuit (2) 104, filter circuit (3) 111
Then, the result obtained by deleting the lower bits by the value stored in the deletion register 106 from the input value is obtained as the output. In the filter circuit (3) 111, of the values stored in the divisor register 108, the subtracter (1) 110
The lower bits are deleted by the value obtained in (i.e., the continuous "0" part of the lower bits is deleted), and the result is input to the reciprocal calculator 103 as a parameter.

FIG. 4 shows a detailed block diagram of the reciprocal calculator 103. When the parameter is input to the reciprocal calculator 103, the priority encoder (2) 113 determines the number of significant digits of the parameter. Priority encoder (2) 11
The result obtained in 3 is added to the number of digits of the value to be obtained by the reciprocal calculator 103 by the adder (1) 122 to obtain the filter value of the filter circuit (2) 104 and input to the adjuster 114. Then, a continuous value of "0" is generated for "1" by the value obtained by the priority encoder (2) 113. For example, the priority encoder 113
When the value of is "0011", the adjuster 114 obtains a value of "10000", which is a series of four "0" s. The subtractor (2) 115 subtracts the parameter from the value obtained by the adjuster 114 and gives the result to the arithmetic unit 116. In the arithmetic unit 116, first, the value obtained from the subtractor (2) 115 is added with “0” to the least significant bit by the shifter 117, and the value is given to the selector 119, the subtractor (3) 118 and the comparator 120. The subtracter (3) 118 subtracts the parameter from the value obtained by the shifter 117, and supplies the result to the selector 119.
The comparator 120 compares the value obtained by the shifter 117 with the parameter, and the result is input to the selector 119 and the bit generator 121. In the selector 119, (value of the shifter 117) ≧ (parameter) If subtractor (3) 1
When the value of 18 is (value of shifter 117) <(parameter), the value of shifter 117 is selected and passed to the next arithmetic unit. In the bit generator 121, as the calculation result of the calculation unit, “1” is given if (value of shifter 117) ≧ (parameter), and “1” if (value of shifter 117) <(parameter). 0 "is generated. Below, the most significant bit is "1"
The calculation by the arithmetic unit 116 is repeated by the number of digits desired to be obtained as the multiplier of the multiplier 104. In the adder (2) 112, "1" is added to the least significant bit in consideration of the number of digits that are truncated without being calculated, and the result is given to the multiplier 104 as a multiplier.

When the dividend is input to the filter circuit (1) 101, lower bits are deleted by the filter value given by the prime number decomposer 102, and the result is given to the multiplier 104 as the multiplicand. That is, the divisor and the dividend are divided by the same value and then input to the multiplier. The filter circuit (2) 105 removes the fractional factor from the result obtained by the multiplier 104, and obtains the division result.

The present embodiment will be described below by actually using values.

5 and 6 show a process in which a numerical value is actually processed by the divider of the present invention. In this example, the divisor is 5120 (“101000000000000 in binary notation”).
0 ”), the dividend is 40204 (“ 100 in binary notation ”)
11110100001100 ") and 40204 is 5
It shows how it is divided by 120. In this example, the divisor and dividend are given as 16-bit binary numbers, and the division result is also 16
It shall be obtained as a binary number of bits.

When the divisor 5120 is input to the prime number decomposer 102 as a 16-bit binary number "0001010000000", the priority encoder (1) 109 encodes a value "0000000000101000" in which the upper bit and the lower bit are reversed. A 4-bit binary number "0101" is obtained. In the subtracter (1) 110, “1111” is stored in advance as the maximum value for encoding the input 16-bit divisor, and that value is subtracted from the value “0101” obtained from the priority encoder (1) 110. Then, “1010” is obtained, and is given to the filter circuit (1) 101 and the filter circuit (3) 111 as a filter value. In the filter circuit (3) 111, the divisor “00010”
Subtractor (1) 110 out of 10000000 "
Lower 10 according to the filter value “1010” given by
Bits are deleted, and "00000000000010"
1 ”is obtained. In the reciprocal calculator 103,“ 0000000000 ”given from the filter circuit (3) 111 is obtained.
00101 "is the priority encoder (2) 113
Is input to a 4-bit binary number "0010".
In the adder (1) 122, the binary number display “1000” of the bit number 16 of the multiplier to be calculated is stored in advance,
This value and "0010" given from the priority encoder (2) 113 are added to obtain "1010", which is given to the filter circuit (2) 105 as a filter value. Further, the adjuster 114 obtains a value “1000” obtained by adding three “0” s to “1” according to “0010” obtained from the priority encoder (2) 113, and the 16-bit expression “000000000000100” is obtained.
0 ”is given to the subtractor (2) 115. Subtractor (2)
At 115, the value “0000” obtained by the adjuster 114
Filter circuit (3) 1 from 000000001000 "
The value obtained in 11 is "00000000000010"
The value obtained by subtracting "1" is "000000000000"
0011 "is given to the arithmetic unit 116. In this example, the number of digits obtained from the reciprocal arithmetic unit is 16 bits, so 15 arithmetic units obtained by subtracting 1 from 16 are required. May be an arbitrary number of digits according to the calculation precision required as a result of division.The process until the multiplier to be given to the multiplier 104 in the calculation unit 116 is shown in FIG. explain.

First, the result "0" from the subtracter (2) 115.
When the first arithmetic unit 116 (which is referred to as arithmetic unit No. 1) receives "00000000000011", the internal shifter 117 adds "0" to the least significant bit and outputs "00000000000011".
"0", and this value and the value "0000000000000101" given from the filter circuit (3) 111 are subtracted by the subtractor (3) 118 to obtain "0000000000".
00001 ″ is input to the selector 119. In the comparator 120, the value of the shifter 117 and the filter circuit (3) are input.
Comparing the values of 111, two states (value of shifter 117)
≧ (value of the filter circuit (3) 111) and (shifter 11
7 value) <(value of filter circuit (3) 111) is given to the selector 119 and the bit generator 121. In this example, assuming that the true state is “1” and the false state is “0”, the arithmetic unit No. When 1, the value of shifter 117 is "0000000".
000000110 ”and the value of the filter circuit (3) 111 is“ 0000000000000101 ”, (value of shifter 117) ≧ (filter circuit (3) 11
The value indicating 1) is “1”, (the value of shifter 117) <
The signal indicating (the value of the filter circuit (3) 111) is “0”.
Becomes In selector 119 (value of shifter 117) ≧
The signal indicating (the value of the filter circuit (3) 111) is "1".
When, the input from the subtracter (3) 118 is (shifter 1
17) <(value of filter circuit (3) 111) is "1", the input from the shifter 117 is selected and output. Arithmetic unit No. In 1, (shifter 11
7) ≧ (value of filter circuit (3) 111) is “1”, the output “0000000000000001” from the subtractor (3) 118 is set to the arithmetic unit No. The result of 1 is given to the next arithmetic unit. In the bit generator 121, when the signal indicating (value of shifter 117) ≧ (value of filter circuit (3) 111) is “1”, “1” is set, (value of shifter 117) <(filter circuit (3)) When the signal indicating the value of 111) is "1", it is "0"
Is output as the calculation result. Arithmetic unit No. At 1, "1" is output. The next arithmetic unit 116 is the arithmetic unit No. 2, the arithmetic unit No. In No. 2, the calculation unit No. Value from 1 "000000000000
0001 ”is received and the same processing as that of the arithmetic unit No. 1 is performed. In the comparator 120, the value“ 00000000000010 ”obtained by the shifter 117 and the value“ 00000 ”given from the filter circuit (3) 111.
00000000101 ", and the value of the filter circuit (3) 111 is large, so (the value of the shifter 117)
A signal indicating <(value of filter circuit (3) 111) is set to “1”. Then, the selector 119 outputs the output "0000" of the shifter 117 as a value to be given to the next arithmetic unit.
"000000000010" is selected and output, and the bit generator 121 outputs "0" as the operation result. Hereinafter, similarly, the operation is repeated up to the fifteenth operation unit, and "1" is added to the most significant bit of the operation result. Value "11"
00110011001100 "is obtained. In the adder (2) 112, 1 which has been rounded down without being calculated
In consideration of the error for the sixth and subsequent arithmetic units, "11001100011001" obtained by the above arithmetic unit.
"1" is added to the least significant bit of 100. The 16-bit binary value "110011" thus obtained.
0011001101 ″ is given to the multiplier 104 as a multiplier.

The dividend is "100111010000.
When 1100 ″ is input to the filter circuit (1) 101, the lower 10 bits are deleted according to the filter value “1010” given from the subtractor (1) 111 in the prime number decomposer 102 to become “000000000000101111”, and the multiplicand is obtained. Is input to the multiplier 104.

In the multiplier 104, the given multiplier "11"
00110011001101 "and multiplicand" 00000
32-bit binary number "000000000000111111001"
In the filter circuit (2) 105, the filter value “10” obtained from the reciprocal calculator 103 as a decimal factor is obtained from the result of the multiplier 104 in the filter circuit (2) 105.
According to "010", the lower 18 bits are deleted to "0000".
000000000111 ", that is, 40204 to 5
The value 7 divided by 120 (rounding down after the decimal point) is obtained.

The divisor for the division operation is 51 in this example.
If there are many factors of powers of 2, such as 20, and if the division operation is performed only with a divisor of a fixed value,
Since the division operation is performed in advance on the divisor and the dividend by the power-of-two factor included in the divisor, the circuit can be simplified as follows.

In FIGS. 7 and 8, numerical values are actually processed by the optimized divider of the present invention in the case where the divisor contains at least 2 to the 10th power as a power factor of 2 like 5120. Show the process. In this example, the lower 10 bits of the divisor and the dividend are deleted. As the reciprocal of the divisor, 1 bit is added to the 6 bits to be obtained as the division result in consideration of the error, and the value of 7 bits may be obtained. . That is, as the multiplier used in this embodiment, the multiplier is 7 bits, the multiplicand is 6 bits, and the obtained multiplication result is 13 bits. 7 bits are deleted from the result of 13 bits as a decimal factor, and 6 bits are divided. The result will be obtained.

The divisor is the priority encoder (1) 1
09 and the input to the subtractor (1) 110 to obtain the filter value (1), which is the same as the above-mentioned means. In the filter circuit (3) 111, the divisor “00010100”
The lower 10 bits of “00000000” are deleted according to the filter value (1), and “000101” is obtained.
Here, at least 10 bits are included in the divisor as a power factor of 2, and 10 bits are always deleted. Therefore, the output of the filter circuit (3) 111 is from 16 bits to 1
It can be 6 bits minus 0 bits. In the reciprocal calculator 103, “000101” given from the filter circuit (3) 111 is the priority encoder (2).
It is input to 113 and a 4-bit binary number “0010” is obtained. In the adder (1) 122, the binary number expression “0111” of the bit number 7 of the multiplier to be obtained is stored in advance, and this value is added to “0010” given from the priority encoder (2) 113 to obtain “1001”. Is obtained and is given to the filter circuit (2) 105 as a filter value. Further, the adjuster 114 obtains a value “1000” obtained by adding three “0” s to “1” according to “0010” obtained from the priority encoder (2) 113, and the subtractor (2) as a 6-bit expression “001000”. Give to 115. The subtractor (2) 115 subtracts the value “000101” obtained by the filter circuit (3) 111 from the value “001000” obtained by the adjuster 114, and the obtained value “000011” is obtained by the subtraction unit 11
Give to 6. The operation performed by the operation unit 116 is the same as that described above, but the number of digits to be obtained as the multiplier in this embodiment is 7 bits, and therefore only 6 operation units are required. Further, the subtractor forming the arithmetic unit is also 6 bits instead of 16 bits. As described above, the 7-bit value “1100” in which “1” is added to the most significant bit of the results of the six arithmetic units 116
110 "is obtained. The adder (2) 112 takes into account the error for the seventh and subsequent arithmetic units that have been truncated without performing the arithmetic operation, and takes" 11 "obtained by the above arithmetic unit.
"1" is added to the least significant bit of "00110." The 7-bit binary number "110011" thus obtained.
1 ”is given to the multiplier 104 as a multiplier.

The dividend is "100111010000.
When 1100 ″ is input to the filter circuit (1) 101, the lower 10 bits are deleted according to the filter value “1010” given from the subtractor (1) 111 in the prime number decomposer 102, and the 6-bit value “1100”. 100111 ″ is input to the multiplier 104 as a multiplicand.

In the multiplier 104, the given multiplier "11"
The multiplication operation of 00111 "and multiplicand" 100111 "is performed to obtain a 13-bit binary number" 011111011000 ".
In the filter circuit (2) 105, the lower 9 bits are deleted from the result of the multiplier 104 according to the filter value “1001” obtained from the reciprocal calculator 103 as a decimal factor, and “0111”, that is, 40204 is obtained. 51
The value “7” divided by 20 is obtained.

As described above, in the present embodiment, the value of the divisor to be input is limited to obtain the division result, and when there are many power factors of 2 included in the divisor, the divisor is previously calculated. Also, the arithmetic circuit in the subsequent stage can be simplified by deleting the lower digit from the dividend by the value of the exponent of the power of 2 included in the divisor.

(Embodiment 2) In the embodiment 1, a power factor of 2 included in a divisor for division is calculated, and a divisor and a dividend are divided in advance by a power factor of 2 included in the divisor, and the latter stage is performed. The means for simplifying the arithmetic circuit of 1. has been described. The means of the first embodiment has an advantage that the configurations of the multiplier and the reciprocal calculator can be simplified when there are many power-of-two factors included in the divisor. However, when the power of 2 factor included in the divisor is small, the advantage of performing the division operation of the divisor and the dividend by the power of 2 factor included in the divisor in advance is lost.

In the second embodiment, means which is advantageous when performing an operation in which the power factor of 2 included in the divisor is small will be described.

FIG. 9 shows a block diagram of the dividing device in the second embodiment. In the figure, the reciprocal calculator 102 and the multiplier 10
4 and the filter circuit (2) 105 have the same configuration as that of the embodiment.

FIG. 10 and FIG. 11 show the steps of processing using numerical values in this embodiment. In this example, the divisor is 25
(“00000000011001” in binary display),
The dividend is 40204 ("1001110" in binary notation)
100001100 ″) and 40204 is divided by 25. In this example, the divisor and dividend are given as 16-bit binary numbers, and the division result is also obtained as 16-bit binary numbers.

When the divisor 25 is input to the reciprocal calculator 103 as a 16-bit binary number "00000000001001001," the 4-bit binary number "0100" is obtained by the priority encoder (2) 113. In the adder (1) 122, the binary number display “10000” of the input multiplier 16 bits 16 is stored in advance, and this value and the priority encoder (2) 1 are stored.
Add “0100” given from 13 to “101
00 "is obtained and given to the filter circuit (2) 105 as a filter value. Further, in the adjuster 114," 010 "obtained from the priority encoder (2) 113.
The value "100", which is obtained by adding five "0" s to "1" according to "0"
000 "is obtained, and the 16-bit expression" 00000000 "is obtained.
It is given to the subtracter (2) 115 as "00100000". In the subtractor (2) 115, the divisor "00000000001011001" is subtracted from the value "0000000000100000" obtained by the adjuster 114, and the obtained value "0000000000000111" is given to the arithmetic unit 116. In this example, since the number of digits to be obtained from the reciprocal calculator 103 is 16 bits, 15 arithmetic units are required by subtracting 1 from 16. The number of digits to be obtained by the reciprocal calculator 103 is obtained as a division result. Any number of digits may be used according to the required calculation accuracy.The process until the multiplier to be given to the multiplier 104 in the calculation unit 116 is shown in FIG.

First, the result "0" from the subtracter (2) 115.
When the first arithmetic unit 116 (this is arithmetic unit No. 1) receives "000000000000111", the internal shifter 117 adds "0" to the least significant bit and outputs "00000000000011".
0 ", and this value and divisor" 00000000000011 "
The value obtained by subtracting "001" by the subtractor (3) 118 is "1111".
111111110101 ″ is input to the selector 119. In the comparator 120, the value of the shifter 117 is compared with the divisor, and two states (value of the shifter 117) ≧ (divisor)
And (value of shifter 117) <(divisor) is set to selector 119
And the bit generator 121. In this example, assuming that the true state is “1” and the false state is “0”, the arithmetic unit N
o. When 1, the value of the shifter 117 is “000000000000”.
0001110 "and the divisor is" 0000000000 "
Since 11001 ”, the signal indicating (value of shifter 117) ≧ (divisor) is“ 0 ”, and the signal indicating (value of shifter 117) <(divisor) is“ 1 ”.
When the signal indicating (value of shifter 117) ≧ (divisor) is “1”, the input from the subtractor (3) 118 is changed to (shifter 11).
When the signal indicating (value of 7) <(divisor) is "1", the input from the shifter 117 is selected and output. Arithmetic unit N
o. In the case of 1, the signal indicating (value of shifter 117) <(divisor) is “1”, so the input from shifter 117 is “00”.
00000000000011110 "is the arithmetic unit No.
The result of 1 is given to the next arithmetic unit. In the bit generator 121, when the signal indicating (value of shifter 117) ≧ (divisor) is “1”, “1” is set, and (value of shifter 117)
When the signal indicating <(divisor) is "1", "0" is output as the operation result. Arithmetic unit No. 1 means “0”
Is output. The next arithmetic unit 116 is changed to the arithmetic unit N
o. 2, the arithmetic unit No. In No. 2, the calculation unit No. Value from 1 "00000000000011
0 "is received and processing similar to that of the arithmetic unit No. 1 is performed. In the comparator 120, the value" 00000000000011100 "obtained by the shifter 117 and the divisor" 0 "are obtained.
00000000000011 1001 "and shifter 1
17 is large (value of shifter 117) ≧ (divisor)
Is set to "1". Then, in the selector 119, as the value to be given to the next arithmetic unit, the subtractor 118
The input "00000000000011" is selected and output, and the bit generator 121 outputs "1" as the operation result. Hereinafter, similarly, the processing is repeated up to the fifteenth operation unit, and the value "101000111101100" is obtained by adding "1" to the most significant bit of the operation result.
0 "is obtained. The adder (2) 112 takes into account the error for the 16th and subsequent arithmetic units that have been truncated without performing the arithmetic operation, and take" 101 "obtained by the above arithmetic unit.
"1" in the least significant bit of 0001111010111 "
Is added. The 16-bit binary value "1010001111011000" thus obtained is supplied to the multiplier 104 as a multiplier.

The dividend is "100111010000"
1100 ″ is directly input to the multiplier 104 as a multiplicand.

In the multiplier 104, the given multiplier "10"
10001111011000 "and multiplicand" 10011 "
32-bit binary number "011001001000001100100"
In the filter circuit (2) 105, the filter value “10” obtained from the reciprocal calculator 103 as a decimal factor is obtained from the result of the multiplier 104.
According to "100", the lower 20 bits are deleted to "0110".
01001000 ", that is, a value" 1608 "obtained by dividing 40204 by 25 (fractions below the decimal point are truncated) is obtained.

As described above, in this embodiment, when the power factor of 2 included in the divisor is small, the inverse calculator, the multiplier and the filter circuit (2) in the first embodiment are used,
Moreover, since the filter circuit (1) and the prime number decomposer for dividing the divisor and the dividend by the power-of-two factor included in the divisor are not required, the circuit can be simplified.

(Example 3) In Example 1 and Example 2,
The embodiment has been described in which the arithmetic circuit is used to obtain the reciprocal of the divisor and the number of digits of the decimal factor included in the multiplication result.

In the third embodiment, an example will be described in which a microprocessor specialized in arithmetic is used to obtain the reciprocal of the divisor or the number of digits of the fractional factor included in the multiplication result.

FIG. 12 shows a block diagram in the third embodiment. In the figure, reference numeral 301 is dedicated to an operation for obtaining a multiplier and a multiplicand to be given to the multiplier 104 and a number of digits of a decimal factor included in a result obtained from the multiplier, from a divisor and a dividend to be given for performing a division operation. Is a microprocessor for. Microprocessor 301 is RO
The processing of the flowchart shown in FIG. 13 is performed based on the program stored in M302.

According to the present embodiment, the microprocessor calculates the reciprocal of the divisor and the number of digits of the fractional factor included in the multiplication result, so that it is used in the first and second embodiments. Since the filter circuit (1), the prime number decomposer, and the reciprocal number calculator are not required, the circuit can be simplified.

As described above, according to this embodiment,
In performing the division operation, means for counting the power of two factors included in the divisor is provided, and means for executing division of the divisor and dividend according to the value obtained by the means is provided, and the reciprocal of the divisor is calculated. By providing the means for obtaining, the division of the dividend and the divisor is realized by using the multiplier, and further, the means for counting the number of digits of the decimal factor included in the multiplication result can accurately obtain the division result. With such a simple circuit configuration, it is possible to realize a division device corresponding to an arbitrary divisor and dividend.

[0042]

As described above, according to the present invention, an arbitrary divisor and dividend can be dealt with, and a memory for storing the result of division is unnecessary, so that the arithmetic processing can be speeded up. .

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a dividing device according to a first embodiment of the present invention,

FIG. 2 is a block diagram showing a configuration example of a prime number decomposer,

FIG. 3 is a block diagram showing a configuration example of filter circuits (1), (2), and (3).

FIG. 4 is a block diagram showing a configuration example of an inverse calculator.

FIG. 5 is a conceptual diagram showing the processing steps of a concrete example for each block in the dividing device according to the first embodiment;

FIG. 6 is a conceptual diagram showing the processing steps of a concrete example for each block in the division device according to the first embodiment;

FIG. 7 is a data processing diagram showing processing steps of a specific example for each block when the circuit is simplified in the division device of the first embodiment;

FIG. 8 is a data processing diagram showing the processing steps of a specific example for each block when the circuit is simplified in the division device of the first embodiment;

FIG. 9 is a block diagram showing a configuration of a dividing device according to a second embodiment.

FIG. 10 is a data processing diagram showing the processing steps of a specific example for each block in the dividing device according to the second embodiment;

FIG. 11 is a data processing diagram showing the processing steps of a specific example for each block in the dividing device according to the second embodiment of the present invention;

FIG. 12 is a block diagram showing a configuration of a dividing device according to a third embodiment.

FIG. 13 is a flowchart showing the operation of the microcomputer of the division device in the third embodiment.

FIG. 14 is a conceptual diagram of processing in the arithmetic unit according to the first embodiment.

FIG. 15 is a conceptual diagram of processing that can be performed in the arithmetic unit according to the second embodiment.

[Explanation of symbols]

 101 filter circuit (1) 102 prime number decomposer 103 reciprocal operator 104 multiplier 105 filter circuit (2) 106 deletion register 107 selector 108 division register 109 priority encoder (1) 110 subtractor 111 filter circuit (3) 112 adder ( 2) 113 priority encoder (2) 114 adjuster 115 subtractor (2) 116 arithmetic unit 117 shifter 118 subtractor (3) 119 selector 120 comparator 121 bit generator 122 adder (1) 301 microprocessor

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Junichi Tanahashi 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. (72) Inventor Morimoto Hajime 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Incorporated (72) Inventor Kenichiro Ono 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. (72) Inventor Tatsuya Sakashita 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc.

Claims (3)

[Claims] 1. A division device for performing a division operation from a divisor and a dividend given by a binary number and obtaining the result, means for obtaining the reciprocal of the divisor and the number of significant digits, and a reciprocal of the divisor obtained by the means. A division device comprising means for multiplying a dividend and a means for obtaining a division result by deleting a fractional factor from the obtained multiplication result based on the number of significant digits. 2. The dividing device according to claim 1, wherein the counting means counts factors of powers of 2 included in the divisor in advance, and an exponent of 2 obtained by the counting means from the divisor and dividend. A dividing device, characterized in that it comprises a means for deleting the lower digit. 3. A division method is carried out from a divisor and a dividend given by a binary number, and in a division method for obtaining the result, the reciprocal of the divisor and the number of significant digits are obtained, and the reciprocal of the obtained divisor and the dividend are multiplied. A division method characterized in that a fractional factor is deleted from the obtained multiplication result based on the number of significant digits to obtain a division result.