JPH0478171B2 - - Google Patents

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Publication number
JPH0478171B2
JPH0478171B2 JP22669284A JP22669284A JPH0478171B2 JP H0478171 B2 JPH0478171 B2 JP H0478171B2 JP 22669284 A JP22669284 A JP 22669284A JP 22669284 A JP22669284 A JP 22669284A JP H0478171 B2 JPH0478171 B2 JP H0478171B2
Authority
JP
Japan
Prior art keywords
aluminum
layer
semiconductor substrate
plate
silicon semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP22669284A
Other languages
Japanese (ja)
Other versions
JPS61105849A (en
Inventor
Hiroaki Sakamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nihon Inter Electronics Corp
Original Assignee
Nihon Inter Electronics Corp
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Filing date
Publication date
Application filed by Nihon Inter Electronics Corp filed Critical Nihon Inter Electronics Corp
Priority to JP59226692A priority Critical patent/JPS61105849A/en
Publication of JPS61105849A publication Critical patent/JPS61105849A/en
Publication of JPH0478171B2 publication Critical patent/JPH0478171B2/ja
Granted legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
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    • H01L2224/273—Manufacturing methods by local deposition of the material of the layer connector
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    • H01L2224/27334—Manufacturing methods by local deposition of the material of the layer connector in solid form using preformed layer
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    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/29124—Aluminium [Al] as principal constituent
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    • H01L2224/30181—On opposite sides of the body
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    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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    • H01L2224/83007—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a permanent auxiliary member being left in the finished device, e.g. aids for holding or protecting the layer connector during or after the bonding process
    • H—ELECTRICITY
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    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
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    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
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    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1301—Thyristor

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Die Bonding (AREA)

Description

【発明の詳細な説明】 ［産業上の利用分野］ この発明は、半導体装置の製造方法に関し、特
にその電極形成方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for forming electrodes thereof.

［従来の技術］ サイリスタ等の半導体装置の電極、例えばシリ
コン半導体基板の上側主面のカソード電極の形成
方法には、次のような大別して２種類の方法があ
る。すなわち１つの方法は所謂同時合金法とい
い、第３図に示すような例えばPE層、NB層、PB
層、NE層を形成した４層サイリスタ構造のシリ
コン半導体基板１の上、下両主面にアルミ板２，
３を介してモリブデンから成るアノード側温度補
償板４、カソード側温度補償板５を配置した後、
所定温度で加熱し、アルミ板２，３を溶融させて
温度補償板４，５とシリコン半導体基板１とを合
金、固着するものである。[Prior Art] There are two types of methods for forming an electrode of a semiconductor device such as a thyristor, for example, a cathode electrode on the upper main surface of a silicon semiconductor substrate. In other words, one method is the so-called simultaneous alloying method, for example, P E layer, N B layer, P B layer as shown in Figure 3.
Aluminum plates 2 ,
After arranging an anode side temperature compensation plate 4 and a cathode side temperature compensation plate 5 made of molybdenum via 3,
The aluminum plates 2 and 3 are heated at a predetermined temperature to melt them, thereby alloying and fixing the temperature compensating plates 4 and 5 and the silicon semiconductor substrate 1.

また、もう１つの方法は、蒸着法といい、この
方法は第３図のアノード側温度補償板４をまずア
ルミ板等を用いてシリコン半導体基板１に合金固
着し、次いで、カソード側のシリコン半導体基板
１の主面にアルミ等を蒸着してカソード電極とす
る方法である。 Another method is the vapor deposition method, in which the anode-side temperature compensating plate 4 shown in FIG. This is a method in which aluminum or the like is deposited on the main surface of the substrate 1 to form a cathode electrode.

［発明が解決しようとする問題点］ 上記従来の電極形成方法において、まず同時合
金法は半導体装置を製作した場合に順方向電圧降
下が大となる傾向にあるという問題点がある。[Problems to be Solved by the Invention] In the conventional electrode forming method described above, there is a problem in that the simultaneous alloying method tends to cause a large forward voltage drop when a semiconductor device is manufactured.

これは、アノード側及びカソード側のモリブデ
ンから成る温度補償板とシリコン半導体基板とを
両者、完全に合金化すると、カソード側シリコン
半導体基板のNE濃度がアルミにより低下又は反
対導電型に反転するためと考察される。すなわ
ち、シリコン半導体基板に対してアルミのぬれ性
は非常に良好であるが、温度補償板としてのモリ
ブデンに対してのぬれ性はあまり良くない。した
がつてモリブデン製の温度補償板とアルミ板とを
完全に合金、固着化するまで加熱温度を上昇させ
ると、カソード側のぬれ性のきわめて良いシリコ
ン半導体基板のNE層へのアルミのくい込みが大
となり、NE層の濃度を低下又は導電型を反転さ
せ、結局順方向電圧降下特性に悪影響を与えるた
めと考えられる。 This is because when the silicon semiconductor substrate and the temperature compensating plate made of molybdenum on the anode and cathode sides are completely alloyed, the N E concentration of the silicon semiconductor substrate on the cathode side is reduced by aluminum or reversed to the opposite conductivity type. It is considered that. That is, although aluminum has very good wettability with respect to a silicon semiconductor substrate, its wettability with molybdenum as a temperature compensation plate is not so good. Therefore, if the heating temperature is increased until the molybdenum temperature compensating plate and the aluminum plate are completely alloyed and bonded, aluminum will penetrate into the N E layer of the silicon semiconductor substrate, which has extremely good wettability on the cathode side. This is thought to be due to the fact that the concentration of the N E layer increases or the conductivity type of the N E layer is reversed, which ultimately has an adverse effect on the forward voltage drop characteristics.

また、シリコン半導体基板のカソード側にあま
り厚いアルミ板を使用すると、シリコン半導体基
板の合金化層が大となり、前記のようにNE層が
アルミにより低下又は反転するため順方向電圧降
下の上昇をきたすのでこの面から制約がありカソ
ード側へ使用するアルミ板は、アノード側に使用
するアルミ板よりも薄いものを使用している。ア
ノード側に使用するアルミ板は厚くし、モリブデ
ンから成る温度補償板とシリコン半導体基板との
合金固着を確実に行う。アノード側はPE層であ
るから導電型を反転させることはない。 In addition, if a too thick aluminum plate is used on the cathode side of the silicon semiconductor substrate, the alloy layer of the silicon semiconductor substrate will become large, and as mentioned above, the N E layer will be lowered or reversed by the aluminum, resulting in an increase in forward voltage drop. Due to this limitation, the aluminum plate used for the cathode side is thinner than the aluminum plate used for the anode side. The aluminum plate used on the anode side is made thick to ensure that the temperature compensating plate made of molybdenum and the silicon semiconductor substrate are alloyed tightly together. Since the anode side is a PE layer, the conductivity type is not reversed.

しかるに、一方ではこの薄いアルミ板を使用す
るためにカソード側の合金、固着化が不十分であ
り、カソード側のモリブデンから成る温度補償板
が部分的に剥離してしまう場合があるという問題
点がある。 However, due to the use of this thin aluminum plate, the alloy on the cathode side is not sufficiently fixed, and the temperature compensating plate made of molybdenum on the cathode side may partially peel off. be.

一方、従来のアルミ蒸着法によるカソード電極
形成方法では、シリコン半導体基板のカソード側
主面全面にアルミが付着してしまい不要部分を除
去するために、ホト・リソ工程等電極形成までに
複雑かつ多くの工程を必要とし半導体装置の製造
原価を大幅に上昇させるという問題点がある。 On the other hand, in the conventional cathode electrode formation method using the aluminum vapor deposition method, aluminum adheres to the entire main surface of the cathode side of the silicon semiconductor substrate, and in order to remove unnecessary parts, the photolithography process etc. are complicated and many steps are required before electrode formation. There is a problem in that this method requires several steps and significantly increases the manufacturing cost of the semiconductor device.

この発明は、上記のような問題点を解消するた
めになされたもので、順方向電圧降下の上昇を防
ぎかつ製造原価の面においても有利な半導体装置
の製造方法を提供することを目的としている。 This invention was made to solve the above-mentioned problems, and aims to provide a method of manufacturing a semiconductor device that prevents an increase in forward voltage drop and is advantageous in terms of manufacturing costs. .

［問題点を解決するための手段］ この発明にかかる半導体装置の製造方法は、カ
ソード側電極の形成には当該カソード側のパター
ン形状に合わせて打ち抜いたアルミ板のみを、ア
ノード側はアルミ板を介して温度補償板を配置し
てシリコン半導体板に同時に合金化して両主面の
電極を形成する。[Means for Solving the Problems] The method for manufacturing a semiconductor device according to the present invention uses only an aluminum plate punched out according to the pattern shape of the cathode side for forming the cathode side electrode, and an aluminum plate for the anode side. A temperature compensating plate is disposed through the silicon semiconductor plate and simultaneously alloyed with the silicon semiconductor plate to form electrodes on both main surfaces.

［作用］ アルミ合金化処理の際にカソード側のモリブデ
ンから成る温度補償板がないために該補償板とシ
リコン半導体基板との合金化固着の良否を全く考
慮する必要がなくなり低温合金化処理が可能とな
るため、半導体装置の順方向電圧降下特性の上昇
を防げかつ工程数も従来の蒸着法に比し、はるか
に少く有利となる。[Function] Since there is no temperature compensating plate made of molybdenum on the cathode side during aluminum alloying treatment, there is no need to consider the quality of alloying adhesion between the compensating plate and the silicon semiconductor substrate, and low-temperature alloying treatment is possible. Therefore, it is possible to prevent the forward voltage drop characteristic of the semiconductor device from increasing, and the number of steps is much smaller than that of the conventional vapor deposition method, which is advantageous.

［実施例］ 以下に、この発明の一実施例を第１図を参照し
て説明する。[Example] An example of the present invention will be described below with reference to FIG.

なお、第３図と同一又は相当部分には同一符号
を付してある。 Note that the same or equivalent parts as in FIG. 3 are given the same reference numerals.

第１図において、シリコン半導体基板１には周
知の方法により、PE層、NB層、PB層、NE層の４
層サイリスタ構造が形成されている。この半導体
基板１の下側主面、すなわちアノード側には20〜
50μｍ程度の厚さのアルミ板２を介してモリブデ
ンから成る温度補償板４が配置される。一方、シ
リコン半導体基板１の上側主面には温度補償板を
合金、固着化する必要がなく、単に半導体基板表
面にアルミの電極層を形成すればよいから、下側
主面よりも板厚の薄い７〜15μｍ程度のアルミ板
３を配置する。また、この実施例では前記基板１
の中央部に補助サイリスタ部を形成したので、そ
のNE層上にもアルミ板３ａを載せた後、非酸化
性雰囲気中で約650〜820℃の範囲で加熱しアノー
ド側の温度補償板４とPE層、カソード側のアル
ミ板３とNE層及び補助サイリスタ部のNE層とア
ルミ板３ａとを合金化し固着化させる。 In FIG. 1, a silicon semiconductor substrate 1 has four layers: a P E layer, an N B layer, a P B layer, and an N E layer, by a well-known method.
A layer thyristor structure is formed. On the lower main surface of this semiconductor substrate 1, that is, on the anode side, there are 20 to
A temperature compensating plate 4 made of molybdenum is placed through an aluminum plate 2 having a thickness of about 50 μm. On the other hand, there is no need to alloy or fix a temperature compensating plate on the upper main surface of the silicon semiconductor substrate 1, and it is sufficient to simply form an aluminum electrode layer on the semiconductor substrate surface. A thin aluminum plate 3 of about 7 to 15 μm is placed. Further, in this embodiment, the substrate 1
Since the auxiliary thyristor part was formed in the center of the N E layer, the aluminum plate 3a was also placed on the N E layer, and then heated in a non-oxidizing atmosphere in the range of about 650 to 820°C to form the anode side temperature compensating plate 4. and P E layer, the cathode side aluminum plate 3 and N E layer, and the auxiliary thyristor N E layer and aluminum plate 3a are alloyed and fixed.

こうして電極が形成されたシリコン半導体基板
１は、例えば第２図に示すようにカソード側には
モリブデンから成る温度補償板５が配置されアノ
ード外部電極６、カソード外部電極７間に挟み外
部から加圧する所謂加圧接触型の半導体装置が完
成する。 The silicon semiconductor substrate 1 on which electrodes have been formed in this way is, for example, as shown in FIG. 2, a temperature compensating plate 5 made of molybdenum is arranged on the cathode side, and is sandwiched between an anode external electrode 6 and a cathode external electrode 7 and pressurized from the outside. A so-called pressure contact type semiconductor device is completed.

なお、上記の実施例では、PE層、NB層、PB層、
NE層から成る４層サイリスタ構造のシリコン半
導体基板を用いる例について説明したが、ダイオ
ード等その他の半導体装置にも適用できることは
いうまでもない。 In addition, in the above embodiment, the P E layer, the N B layer, the P B layer,
Although an example using a silicon semiconductor substrate having a four-layer thyristor structure consisting of N and E layers has been described, it goes without saying that the present invention can also be applied to other semiconductor devices such as diodes.

アルミ板は純アルミ若しくはアルミを主成分と
する合金でもよい。 The aluminum plate may be pure aluminum or an alloy containing aluminum as a main component.

［発明の効果］ この発明は以上のように構成したので、低温合
金化処理が可能であり、したがつて半導体装置の
順方向電圧降下特性に悪影響を与えない。また、
あらかじめシリコン半導体基板のカソード側パタ
ーン形状に合わせて打ち抜いたアルミ板のみを配
置して合金化処理をするので、ホト・リソ工程、
エツチング工程等を不要とし、工程数も増加させ
ないので安価に電極形成ができる等この種の製造
方法を実施するに当り実用的価値が高い。[Effects of the Invention] Since the present invention is configured as described above, low-temperature alloying treatment is possible, and therefore the forward voltage drop characteristics of the semiconductor device are not adversely affected. Also,
Only aluminum plates punched in advance according to the cathode side pattern shape of the silicon semiconductor substrate are placed and alloyed, so the photolithography process,
This type of manufacturing method has high practical value, as it eliminates the need for etching steps and does not increase the number of steps, making it possible to form electrodes at low cost.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は、この発明の一実施例を示す半導体装
置の製造方法の説明図、第２図は上記方法で製作
されたものを用いて半導体装置に組立てた場合の
説明図、第３図は従来同時合金法によるの半導体
装置の製造方法を示す説明図である。 図において、１はシリコン半導体基板、２，
３，３ａはアルミ板、４，５は温度補償板であ
る。 FIG. 1 is an explanatory diagram of a method for manufacturing a semiconductor device showing an embodiment of the present invention, FIG. 2 is an explanatory diagram of a semiconductor device manufactured using the above method, and FIG. FIG. 2 is an explanatory diagram showing a method of manufacturing a semiconductor device using a conventional simultaneous alloying method. In the figure, 1 is a silicon semiconductor substrate, 2,
3 and 3a are aluminum plates, and 4 and 5 are temperature compensation plates.

Claims (1)

【特許請求の範囲】[Claims] １ シリコン半導体基板の上、下主面上にアルミ
板を用いて上、下同時に合金化して電極を形成す
る半導体装置の製造方法において、下側主面のみ
にモリブデンから成る温度補償板をアルミ板を介
して配置し、上側主面には下側主面に配置される
アルミ板の板厚よりも薄い板厚で、かつ、当該上
側主面のパターン形状に合わせたアルミ板のみを
配置して上、下同時に合金化して電極を形成する
ことを特徴とする半導体装置の製造方法。1. In a method for manufacturing a semiconductor device in which aluminum plates are used on the upper and lower main surfaces of a silicon semiconductor substrate and are simultaneously alloyed on the upper and lower sides to form electrodes, a temperature compensating plate made of molybdenum is placed only on the lower main surface of the aluminum plate. , and only an aluminum plate that is thinner than the aluminum plate placed on the lower main surface and that matches the pattern shape of the upper main surface is placed on the upper main surface. A method for manufacturing a semiconductor device, characterized by forming an electrode by simultaneously alloying the upper and lower parts.
JP59226692A 1984-10-30 1984-10-30 Manufacture of semiconductor device Granted JPS61105849A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59226692A JPS61105849A (en) 1984-10-30 1984-10-30 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59226692A JPS61105849A (en) 1984-10-30 1984-10-30 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPS61105849A JPS61105849A (en) 1986-05-23
JPH0478171B2 true JPH0478171B2 (en) 1992-12-10

Family

ID=16849155

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59226692A Granted JPS61105849A (en) 1984-10-30 1984-10-30 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS61105849A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5072312A (en) * 1988-03-15 1991-12-10 Siemens Aktiengesellschaft Thyristor with high positive and negative blocking capability

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5598835A (en) * 1979-01-19 1980-07-28 Mitsubishi Electric Corp Pressure-welded semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5598835A (en) * 1979-01-19 1980-07-28 Mitsubishi Electric Corp Pressure-welded semiconductor device

Also Published As

Publication number Publication date
JPS61105849A (en) 1986-05-23

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