JPH0478166A - Semiconductor memory and manufacture thereof - Google Patents

Abstract

PURPOSE:To realize high speed of a semiconductor memory, to improve resistance to a soft error caused by alpha line and to realize high integration density of a memory cell by forming at least one capacitor electrode through a dielectric film on an island-like single crystalline semiconductor layer side and by forming an access transistor in the island-like single crystalline semiconductor layer. CONSTITUTION:A dielectric isolation island-like single crystalline semiconductor layer 7 and a base 1 for holding it are provided, at least one capacitor electrode 3 is formed at the side of the island-like single crystalline semiconductor layer 7 between the base 1 and the island-like single crystalline semiconductor layer 7 through a dielectric film 5, and an access transistor is formed at the island-like single crystalline semiconductor layer 7. Thereby, high speed of a semiconductor memory can be realized. There is little effect to a charge stored node even if alpha line is injected, and resistance to a soft error caused by a line can be improved. Furthermore, since a structure formed by laminating an access transistor on a capacitor can be realized, an area a memory cell can be reduced. High integration density of a memory cell can be realized in this way.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory and a method for manufacturing the same, and is particularly suitable for application to a dynamic RAM.

[Summary of the Invention] The present invention provides a semiconductor memory having a memory cell constituted by a capacitor and an access transistor.
Between the isolated island-shaped single crystal semiconductor layer and the base holding the island-shaped single crystal semiconductor layer, a dielectric film is provided between the island-shaped single crystal semiconductor layer side (both capacitors By forming electrodes and access transistors in the island-shaped single crystal semiconductor layer, it is possible to increase the speed of semiconductor memory, improve resistance to soft errors caused by alpha rays, and increase the integration density of memory cells. It has been made possible to do so.

[Conventional technology]

As a technology for realizing highly integrated dynamic RAM, access transistors that make up memory cells are thin film transistors using polycrystalline silicon (Si) thin films.
A technique is known in which the area of a memory cell is reduced by stacking the TPT as an access transistor on a capacitor (for example,
JP-A-61-4271, JP-A-61-15686
Publication No. 3).

[Problem to be solved by the invention]

According to the above-mentioned conventional technology, it is possible to achieve high integration density of memory cells, but MOS using single crystal Si
) Since access transistors are formed from TPT, which is inferior to transistors in terms of operating speed, it is difficult to increase the speed of dynamic RAM.

Therefore, an object of the present invention is to provide a semiconductor memory that can achieve high speed.

Another object of the present invention is to provide a semiconductor memory that can improve resistance to soft errors caused by alpha rays.

Another object of the present invention is to provide a semiconductor memory in which memory cells can be highly integrated.

Another object of the present invention is to provide a method for manufacturing a semiconductor memory that can increase the speed of the semiconductor memory, improve resistance to soft errors caused by alpha rays, and increase the integration density of memory cells.

[Means for Solving the Problems] In order to achieve the above object, a first invention provides a semiconductor memory having a memory cell constituted by a capacitor and an access transistor, in which a monocrystalline semiconductor in the form of an isolated island is used. layer (7) and island-shaped single crystal semiconductor layer (7)
A dielectric film (5) is provided on the island-shaped single crystal semiconductor layer (7) side between the base (1) and the island-shaped single crystal semiconductor layer (7). ), and an access transistor is formed in the island-shaped single crystal semiconductor layer (7).

Further, a second invention provides a semiconductor memory having a memory cell constituted by a capacitor and an access transistor, in which an isolated island-shaped single crystal semiconductor layer (7) is provided.
and a base (1) that holds an island-shaped single crystal semiconductor layer (7).
A base (1) and an island-shaped single crystal semiconductor layer (7)
11 capacitor electrodes (16) electrically connected to an island-shaped single crystal semiconductor layer (7) between the first capacitor electrodes (16) and facing the first capacitor electrode (16) via a dielectric film (17). A second capacitor electrode (3) is formed, and an access transistor is formed in the island-shaped single crystal semiconductor layer (7).

Furthermore, a third invention provides a method for manufacturing a semiconductor memory having a memory cell constituted by a capacitor and an access transistor, in which a predetermined groove (13a) is formed in the first main surface of a single crystal semiconductor substrate (13). The process of making grooves (
13a) embedding a polishing stopper (6) in the interior;
A dielectric film (
5) and the step of forming a single crystal semiconductor base FH, (13)
At least one capacitor electrode (3
) of the single crystal semiconductor substrate (13);
bonding the main surface side of the single crystal semiconductor substrate (13) with the base (1), and polishing the single crystal semiconductor substrate (13) from the second main surface side of the single crystal semiconductor substrate (13) until the polishing stopper (6) is exposed. and a process.

[Effect]

According to the semiconductor memory of the first invention configured as described above, the access transistor is formed in the single crystal semiconductor layer (7), and the single crystal semiconductor layer (7) is insulated and separated, so-called SOof (semicond
Since the structure is similar to that of the 1 nsulator), the parasitic capacitance is small, so the T
The operating speed of the access transistor can be improved compared to the case where the access transistor is formed using PT, and thereby the speed of the semiconductor memory can be increased. In addition, since the access transistor is formed not on the semiconductor substrate but on the island-shaped single crystal semiconductor layer (7),
Even if α rays are incident, there is almost no effect on the charge storage node, and therefore resistance to soft errors caused by α rays can be improved. Furthermore, since the access transistor can be stacked on the capacitor, the area per memory cell can be reduced compared to, for example, a planar memory cell, which allows for higher integration density of memory cells. can be achieved.

According to the semiconductor memory of the second invention configured as described above, as in the case of the semiconductor memory of the first invention, the speed of the semiconductor memory is increased, the resistance to soft errors due to α rays is improved, and the memory cell is improved. High integration density can be achieved. In addition, according to the semiconductor memory of the second invention, the capacitor can have a curved structure by utilizing the step formed by the single crystal semiconductor layer (7), so that the effective area of the capacitor can be increased. Therefore, the capacitance of the capacitor can be increased.

According to the method for manufacturing a semiconductor memory of the third invention configured as described above, the island-shaped single crystal semiconductor layer (7) is insulated and isolated by polishing the single crystal semiconductor substrate (13).
is formed. Therefore, by forming an access transistor in this isolated island-shaped single crystal semiconductor layer (7), it is possible to improve the operating speed of the access transistor, thereby increasing the speed of the semiconductor memory. can. Further, since the access transistor can be formed in the island-shaped single crystal semiconductor layer (7) instead of the semiconductor substrate, it is possible to improve resistance to soft errors caused by α rays.

Furthermore, since the access transistor can be stacked on the capacitor, it is possible to achieve a high integration density of the memory cells.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings. The following embodiments are embodiments in which the present invention is applied to a dynamic RAM having a folded bit line configuration.

FIG. 1 shows a dynamic RAM according to a first embodiment of the present invention.
FIG. 2 is a sectional view taken along the line ■-■ in FIG. 1.

As shown in FIGS. 1 and 2, in the dynamic RAM according to the first embodiment, on a reinforcing base 1,
A polycrystalline material 5il1 doped with an impurity such as phosphorus (P) is formed as a capacitor electrode through a flattening film 2.
3 is formed. Reference numeral 4 indicates an insulating film such as a Sing film having a film thickness of about 1,000 mm. This insulating film 4 is formed in a portion corresponding to a contact portion of a bit line BL to a semiconductor region 10, which will be described later. This insulating film 4 is a polycrystalline film 5ill1 as a capacitor electrode.
This is to suppress the influence of the contact portion of the bit line BL due to the contact portion of the bit line BL. Reference numeral 5 indicates a dielectric film.

This dielectric W! As i5, for example, Si0g film, 5
ON consisting of i02 film, Si, N, film and 5iozli
Composite membranes such as O membranes can be used. This dielectric l
! The film thickness of No. 5 is, for example, about 200. Reference numeral 6 indicates an insulating film such as a 5izN film as a polishing stopper.

Reference numeral 7 indicates, for example, a P-type island-shaped single crystal Si layer.

In this case, a polycrystal 5 as a capacitor electrode is provided on the lower surface 7a and three side surfaces 7b, 7c, and 7d of this single-crystal Si layer 7.
il13 are opposed to each other with the dielectric film 5 interposed therebetween. and,
These polycrystalline 5iy13, dielectric film 5 and single crystal Si
Layer 7 forms a capacitor.

On the other hand, on this single crystal Si layer, a gate insulator Wi! such as a SiO□ film is formed. 8 is formed. Further, in this single crystal layer 7, for example, an n-type semiconductor region 9, 10, 11 used as a source region or a drain region.
is formed. WL,, WLz, WLz, WL
4. WLs and WL- indicate word lines. These word lines WL,,WL, ,WL,,WL,,WL,,WL
, for example, a polycrystalline Si film doped with an impurity such as P(7), or a high melting point metal silicide film such as a tungsten silicide (WSi) film on the polycrystalline Si film doped with this impurity. It is formed by stacked polycide films. In this case, word! WL, and semiconductor region 9
．． 10 forms an n-channel MOS transistor as an access transistor. Similarly, word line WL and semiconductor regions 10.degree. 11 form an n-channel MOS transistor as an access transistor.

Reference numeral 12 indicates an interlayer insulating film. Word line WL.

A contact hole C is formed in a predetermined portion of the glabella insulating film 12 and the gate insulating film 11j8 between the word line WL and the word line WL. BL is, for example, aluminum (A
1) Shows a bit line like wiring.

This bit 1iBL is connected to semiconductor region 10 through contact hole C.

Next, a method of manufacturing the dynamic RAM according to the first embodiment configured as described above will be explained.

As shown in FIGS. 3 and 4, first, for example, p-type single crystal S is etched by, for example, reactive ion etching (RIE) method.
For example, the portion corresponding to the element isolation M region of the T-substrate work 3 is
After etching and removing to a depth of approximately 0 to form grooves 13a, the entire surface is etched by, for example, CVD.
After forming an insulating film 6 such as an NJ film and further forming a planarizing layer II (not shown) such as a resist on this insulating film 6 to flatten the surface, the substrate is coated by, for example, RIE. Etching back is performed in a direction perpendicular to the surface, thereby forming an insulating film 6 as a polishing stopper in the groove 13a.
is embedded. Next, for example, by thermal oxidation method, single crystal S
An insulating film 4 and a dielectric film 5 are formed on the i-substrate 13. Next, after forming a polycrystalline Si film 3 on the entire surface by, for example, the CVD method, the polycrystalline 51M13 is doped with an impurity such as P to lower its resistance.

Next, as shown in FIG. 5, a flattening film 2 is formed on the polycrystal 5illJ to flatten the surface, and then this flattening film 2 is bonded to a reinforcing base l.

Next, the single-crystal Si substrate 13 is polished from the main surface side of the single-crystal Si substrate work 3 opposite to the base 1 until the insulating film 6 is exposed. During this polishing, the polishing is automatically stopped when the insulating film 6 serving as a polishing stopper is exposed. By this polishing, an island-shaped single crystal Si layer 7 is formed as shown in FIG.

Next, as shown in FIG. 7, a gate insulating film 8 is formed on this island-shaped single crystal Si layer by, for example, thermal oxidation.

Next, a polycrystalline Si film is formed on the entire surface by CVD method, and this polycrystalline Si! After doping I with an impurity such as P to lower the resistance, this polycrystalline Si film is patterned by etching to form words IiWLWL,, WL3,
WL4. These word lines W forming WL, , WL,
L,,WL2. When forming WL1WL, , WL, , WL using a polycide film, a high melting point metal silicide film is formed on the polycrystalline 5iWl doped with the impurity described above, and then patterned.

Next, these word lines WL,, WL2゜WLz, W
L4. WL5. After ion-implanting an n-type impurity such as arsenic (As) at a high concentration into the single-crystal Si layer 7 using WLb as a mask, annealing is performed to electrically activate the implanted impurity. As a result, as shown in FIGS. 1 and 2, an n'' type semiconductor region 9.to, for example, is formed in the single crystal Si layer 7.

1■ is formed.

Next, after forming an interlayer insulating film 12 on the entire surface by CVD, a contact hole C is formed by etching away a predetermined portion of the interlayer insulating film 12 and the gate insulating film 8.

Next, a ^I film is formed on the entire surface by, for example, sputtering,
This A1 film is patterned into a predetermined shape by etching to form a focus line BL. Thereafter, a Bassi Basigon 11X (not shown) is formed to complete the intended Dynamic RAM.

According to this first embodiment, there are many advantages as follows. First, the access transistor is formed in the single crystal 5iJii7, and since the single crystal Si layer 7 is insulated and isolated from the insulating film 4, dielectric M5, and insulating film 6, the access transistor is formed in the TPT as in the conventional case. The operating speed of the access transistor can be improved compared to the case where the access transistor is formed using a dynamic RA.
It is possible to increase the speed of M. Second, since the access transistor is formed on the single-crystal Si layer 7 rather than on the semiconductor substrate, even if α rays are incident, there is almost no effect on the charge storage node (therefore, the resistance to soft errors caused by α rays is low). You can improve your performance.

Third, since the access transistor is stacked on the capacitor, the area per memory cell can be reduced, and therefore the memory cells can be highly integrated. Fourth, since a capacitor is formed on the lower surface 7a and the three side surfaces 7b, 7c, and 7d of the single-crystal Si layer 7, if the area of the memory cell is the same, the capacitor is smaller than, for example, a conventional Brehner type capacitor. capacity can be increased. Fifth, the capacitor includes the lower surface 7a and side surface 7b of the single crystal Si layer 7.

7c and 7d, it is possible to reduce the level difference on the surface of the dynamic RAM by that much, thereby reducing the possibility that the bit line BL will be broken.

FIG. 8 shows a dynamic RAM according to a second embodiment of the present invention.
FIG. 9 is a sectional view taken along line IX-IX in FIG. 8.

As shown in FIGS. 8 and 9, in the dynamic RAM according to the second embodiment, the insulating film 4 is not formed on the lower surface of the single crystal Si layer 7 as in the first embodiment; Instead, an opening 3a is formed in this portion of the polycrystalline Si film 3. That is, in this case, by removing the portion of the polycrystalline Si film 3 corresponding to the contact portion of the bit line BL with respect to the semiconductor region IO, the contact portion of the bit line BL with the polycrystalline Si film 3 serving as the capacitor electrode is removed. suppressing the impact of The rest of the configuration is the same as that of the dynamic RAM according to the first embodiment, so a description thereof will be omitted.

In the method of manufacturing a dynamic RAM according to the second embodiment, an insulating film 4 is not formed and an opening 3a is formed in a polycrystalline Si film 3.
The method of manufacturing the dynamic RAM according to the first embodiment is the same as that of the first embodiment except that .

This second embodiment has the same advantages as the first embodiment.

FIG. 10 shows a dynamic RA according to a third embodiment of the present invention.
FIG.

As shown in FIG. 10, in the dynamic RAM according to the third embodiment, words liWLwLz, WL
, , WL, , wLs , and an interlayer insulating film 14 is formed to cover WL. This interlayer insulating film 14 has openings 14a in portions corresponding to the semiconductor regions 9 and 11, respectively.
14b is formed. Reference numeral 15a indicates a polycrystalline Si film doped with an impurity such as P, for example. This polycrystalline Si film 15a has an opening 1 formed in the interlayer insulating film 14.
It is in contact with the gate insulating film 8 through 4a and 14b. Therefore, in this case, these polycrystalline Si films 15a
, a dielectric film consisting of a gate insulating film 8 and a single crystal Si layer 7
A capacitor is also formed. That is, in this case, capacitors are formed not only on the lower surface 7a and side surfaces 7b, 7b, and 7c of the single-crystal Si layer 7, but also on the upper surface 7e of the single-crystal Si layer 7 at the openings 14a and 14b. Become.

On the other hand, a contact hole CI is formed in a predetermined portion of the interlayer insulating film 14 and the gate insulating film 8, and a polycrystalline 5ill15b doped with an impurity such as P is in contact with the semiconductor region 10 through this contact hole CI. . Bit lines B and L are in contact with this polycrystalline Si film 15b through a contact hole C2 formed in the glabella insulating film 12. Therefore, the bit line BL is in contact with the semiconductor region 10 through this polycrystal 5ill15b.

Next, two methods of manufacturing the Dynamink RAM according to the third embodiment configured as described above will be explained.

First, in the same way as in the first embodiment, the word line WL+
, WLz , WL:l , WL4 , WLs , WL
, then a glabellar insulating film 1 is formed on the entire surface by CVD method.
form 4. Next, a predetermined portion of the glabellar insulating film 14 is removed by etching to form an opening 14a.

14b. At this time, these openings 14a14b
Since the gate insulating film 8 inside the openings 14a and 14b is also removed by etching, the single crystal Si inside these openings 14a and 14b is removed by thermal oxidation.
A gate insulating film 8 is again formed on the layer. Next, predetermined portions of the glabella insulating film 14 and the gate insulating film 8 are removed by etching to form a contact hole C1. Next, CVD
A polycrystalline Si film is formed on the entire surface by the method, and this polycrystalline Si film is
After doping the film with an impurity such as P to lower its resistance, the polycrystalline Si film is patterned into a predetermined shape by etching. As a result, the polycrystalline Si film 15a,
15b is formed. Next, after forming an interlayer insulating film 12 on the entire surface by CVD, a predetermined portion of the glabellar insulating film 12 is removed by etching to form a contact hole C2. Thereafter, a bit line BL is formed which contacts the polycrystalline Si film 19b through this contact hole C2.

According to the third embodiment, since a capacitor is also formed on the upper surface 7e of the single crystal Si layer 7, the effective area of the capacitor can be made larger than in the first and second embodiments. This allows the capacitance of the capacitor to be further increased. It goes without saying that, like the first embodiment, other advantages include higher speed dynamic RAM, improved resistance to soft errors caused by alpha rays, and higher integration density of memory cells.

FIG. 11 shows a dynamic RA according to a fourth embodiment of the present invention.
FIG.

As shown in FIG. 11, in the dynamic RAM according to the fourth embodiment, a polycrystalline Si film 16 is formed as one capacitor electrode along the lower surface 7a and three side surfaces of the single-crystalline Si layer 7. .

In this case, dielectric films 5 are formed on three side surfaces of the single crystal Si layer 7.
are not formed, and the polycrystalline Si film 16 as one capacitor electrode is in contact with the semiconductor region 9 on these side surfaces. Reference numeral 17 indicates a dielectric film such as a Si0g film. And in this case, polycrystalline S
A capacitor is formed by the i film 16, the dielectric film 17, and the polycrystalline Si film 3.

Next, a method of manufacturing the Dynamink RAM according to the fourth embodiment configured as described above will be explained.

As shown in FIG. 12, for example, first, a single crystal Si substrate 13
After forming the dielectric film 5 thereon, a predetermined portion of the dielectric film 5 is removed by etching to form a groove 13a in this portion. Next, an insulating film 6 as a polishing stopper is embedded in this groove 13a. Next, after forming a polycrystalline Si film 16 over the entire surface, a resist pattern 18 is formed at a predetermined portion on this polycrystalline Si film 16 by lithography.

Next, using this resist pattern 18 as a mask, the polycrystalline Si film 16 is etched in 22 directions perpendicular to the surface of the substrate by, for example, RIE. As a result, as shown in FIG.
The i film 16 is left, and the polycrystalline 5iWX16 is left in the form of a sidewall spacer on the side surface of the trench 1.3a. After this, the resist pattern 18 is removed.

Next, as shown in FIG. 14, a polycrystalline Si film 3 is formed on the entire surface by the CVD method.
After reducing the resistance by doping with impurities such as, the polycrystalline Si film 3 is patterned into the shape of a capacitor electrode by etching.

Thereafter, the steps after forming the flattening film 2 are performed in the same manner as described in the first embodiment, and the desired dynamic RAM is
complete.

According to this fourth embodiment, the capacitor has a curved structure, and the capacitor is also formed on the side wall of the polycrystalline Si film 16, so the effective area of the capacitor can be increased, and the capacitance of the capacitor can therefore be increased. Can be made larger. It goes without saying that, like the first embodiment, there are other advantages such as faster dynamic RAM, improved resistance to soft errors caused by alpha rays, higher integration density of memory cells, and reduced surface steps. .

FIG. 15 shows a dynamic RA according to a fifth embodiment of the present invention.
FIG.

As shown in FIG. 15, the dynamic RAM according to the fifth embodiment uses polycrystalline Si as in the fourth embodiment.
In addition to forming a capacitor by the film 16, dielectric film 17, and polycrystalline Si film 3, on the upper surface of the single crystal Si layer 7,
Polycrystalline Si film 1 doped with an impurity such as P
9a, a stacked capacitor is formed of a dielectric film 20 such as a 5iOz film and a polycrystalline Si film 21 doped with an impurity such as P. Here, the polycrystalline Si film 19a has contact holes C, .
It is in contact with the semiconductor regions 9 and 11 through C. Further, the bit line BL is connected to the semiconductor region IO via a polycrystalline Si film 19b doped with an impurity such as P, for example.
is in contact with.

Next, a method of manufacturing the dynamic RAM according to the fifth embodiment configured as described above will be explained.

First, the process is carried out in the same manner as described in the fourth embodiment, and the word lines WL, , WL2 . WL3. After forming up to WL, , WL, , WL, a glabellar insulating film 14 is formed on the entire surface by CVD. Next, this glabella insulation [14] and a predetermined portion of the gate insulating film 80 are removed by etching to form a contact hole C.
,,C3,C.

form. Next, a polycrystalline Si film is formed on the entire surface using the CVD method, and after doping the polycrystalline Si film with an impurity such as P to lower the resistance, the polycrystalline SiM is patterned into a predetermined shape by etching. do. As a result, polycrystalline Si films 19a and 19b are formed. next,
A dielectric film 20 is formed on these polycrystalline Si films 19a and 19b.
form. Next, a polycrystalline Si film 21 is formed on the entire surface by the CVD method, and after doping the polycrystalline Si film 2I with an impurity such as P to lower the resistance, the polycrystalline Si film 21 is
The film 21 is patterned into a predetermined shape by etching.

Next, after a glabellar insulating film 12 is formed on the entire surface by CVD, predetermined portions of the glabellar insulating film 12 and the dielectric film 2° are etched away to form a contact hole C2.

After this, polycrystalline Si is connected through this contact hole C2.
A focus line BL is formed in contact with the film 19b.

According to this fifth embodiment, not only is a capacitor formed of a polycrystalline Si film 16, a dielectric film 17, and a polycrystalline Si film 3, but also a polycrystalline Si film 19a, Dielectric Wi! 20 and the polycrystalline Si film 21, the effective area of the capacitor can be made extremely large, and therefore the capacitance of the capacitor can be made extremely large. In addition to this, similar to the first embodiment, the speed of the dynamic RAM is increased, the resistance to soft errors due to alpha rays is improved,
Needless to say, it has advantages such as higher integration density of memory cells.

Although the embodiments of the present invention have been specifically described above, the present invention is not limited to the above-described embodiments, and various modifications can be made based on the technical idea of the present invention.

[Effects of the Invention] Since the present invention is configured as described above, it is possible to increase the speed of a semiconductor memory, improve resistance to soft errors caused by alpha rays, and increase the integration density of memory cells.

[Brief explanation of the drawing]

FIG. 1 shows a dynamic RAM according to a first embodiment of the present invention.
2 is a sectional view taken along the line ■-■ in FIG. 1, and FIG. 3 is a plan view of the dynamic RA according to the first embodiment of the present invention.
A plan view for explaining the manufacturing method of M, FIG.
5 to 7 are cross-sectional views for explaining the method of manufacturing a dynamic RAM according to the first embodiment of the present invention, and FIG. 8 is a cross-sectional view taken along the line IV-IV in the figure. 9 is a plan view of the dynamic RAM according to the second embodiment, FIG. 9 is a sectional view taken along the line IX-IX in FIG. 8, FIG. 10 is a sectional view of the dynamic RAM according to the third embodiment of the present invention, and FIG.
The figure is a sectional view of a dynamic RAM according to a fourth embodiment of the present invention, FIGS. The figure is a sectional view of a dynamic RAM according to a fifth embodiment of the present invention. Explanation of main symbols in the drawings 1: Base, 2: Flattening film, 3.15a1619a,
21: Polycrystalline Si film, 5: Dielectric film, 6: Insulating film,
7: Island-shaped single crystal Si layer, 8: Gate insulating film, 9
, 10, 11: semiconductor region, 12.14: interlayer insulating film,
13: Single crystal Si substrate, BL: Focus line. Agent Patent Attorney Masatoshi Sugiura

Claims (3)

[Claims] (1) A semiconductor memory having a memory cell composed of a capacitor and an access transistor, comprising an isolated island-shaped single crystal semiconductor layer and a base holding the island-shaped single crystal semiconductor layer. , at least one capacitor electrode is formed on the island-shaped single-crystal semiconductor layer side between the base and the island-shaped single-crystal semiconductor layer via a dielectric film, and the island-shaped single-crystal semiconductor layer A semiconductor memory characterized in that the above access transistor is formed in a semiconductor memory. (2) A semiconductor memory having a memory cell constituted by a capacitor and an access transistor, comprising an isolated island-shaped single crystal semiconductor layer and a base holding the island-shaped single crystal semiconductor layer. , a first capacitor electrode electrically connected to the island-shaped single crystal semiconductor layer between the base and the island-shaped single crystal semiconductor layer; and a dielectric film interposed between the first capacitor electrode and the island-shaped single crystal semiconductor layer. and a second capacitor electrode facing each other, and the access transistor is formed in the island-shaped single crystal semiconductor layer. (3) A method for manufacturing a semiconductor memory having a memory cell constituted by a capacitor and an access transistor, including the step of forming a predetermined groove in the first main surface of a single crystal semiconductor substrate, and placing a polishing stopper in the groove. a step of embedding, a step of forming a dielectric film on the first main surface of the single crystal semiconductor substrate, and a step of forming at least one capacitor electrode on the first main surface of the single crystal semiconductor substrate. and bonding the first main surface side of the single crystal semiconductor substrate to a base, and polishing the single crystal semiconductor substrate from the second main surface of the single crystal semiconductor substrate until the polishing stopper is exposed. A method for manufacturing a semiconductor memory, comprising the steps of: