JPH0474417A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0474417A JPH0474417A JP18910590A JP18910590A JPH0474417A JP H0474417 A JPH0474417 A JP H0474417A JP 18910590 A JP18910590 A JP 18910590A JP 18910590 A JP18910590 A JP 18910590A JP H0474417 A JPH0474417 A JP H0474417A
- Authority
- JP
- Japan
- Prior art keywords
- diffusion layer
- region
- substrate
- film
- impurity diffusion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 5
- 238000009792 diffusion process Methods 0.000 claims abstract description 48
- 239000012535 impurity Substances 0.000 claims abstract description 23
- 238000000034 method Methods 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 229910052751 metal Inorganic materials 0.000 claims abstract description 4
- 239000002184 metal Substances 0.000 claims abstract description 4
- 238000000151 deposition Methods 0.000 claims description 9
- 238000005468 ion implantation Methods 0.000 claims description 4
- 230000015556 catabolic process Effects 0.000 abstract description 8
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 6
- 238000002513 implantation Methods 0.000 abstract description 5
- 229910052681 coesite Inorganic materials 0.000 abstract description 3
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 3
- 239000000377 silicon dioxide Substances 0.000 abstract description 3
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 3
- 229910052682 stishovite Inorganic materials 0.000 abstract description 3
- 229910052905 tridymite Inorganic materials 0.000 abstract description 3
- 238000010438 heat treatment Methods 0.000 abstract description 2
- 230000009545 invasion Effects 0.000 abstract 2
- 238000001465 metallisation Methods 0.000 description 11
- 230000000694 effects Effects 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 238000002347 injection Methods 0.000 description 5
- 239000007924 injection Substances 0.000 description 5
- 230000010354 integration Effects 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】 産業上の利用分野 本発明は半導体装置の電極形成方法に関する。[Detailed description of the invention] Industrial applications The present invention relates to a method for forming electrodes of semiconductor devices.
従来の技術 従来の半導体基板への金属の堆積方法を第４図に示す。Conventional technology A conventional method of depositing metal onto a semiconductor substrate is shown in FIG.
第４図ｆａｌに示すようにＳｉ基板４０１上のＬＯＧＯ
８酸化膜４０２で分離された領域に深さ０．２μｍのＡ
ｓ拡散層４０４を形成し、ＳｉＯ２膜４０３を堆積した
後、コンタクトホール４０５を開孔する。このとき、コ
ンタクトホール４０５内のＳｉ基板表面には自然酸化膜
４０６が形成されており、Ａｓ拡散層４０４の表面付近
にはＡｓイオン注入によって形成された欠陥４０７が存
在する。LOGO on the Si substrate 401 as shown in FIG.
A with a depth of 0.2 μm is formed in the region separated by the 8 oxide film 402.
After forming the s-diffusion layer 404 and depositing the SiO2 film 403, a contact hole 405 is opened. At this time, a natural oxide film 406 is formed on the surface of the Si substrate in the contact hole 405, and a defect 407 formed by As ion implantation exists near the surface of the As diffusion layer 404.
この試料に第４図（ｂｌに示すＣＶＤ法によってコンタ
クトホール４０５の中に選択的にタングステン膜（以後
Ｗ膜と略す）４０８を堆積すると、自然酸化膜４０６と
欠陥４０７の影響でＷの局部的な入り込み４０９が起こ
る。（例えば、垣内他電子情報通信学会誌、ＳＤＭ８７
−１５０．ｐ３７）発明が解決しようとする課題
このような従来の方法では、Ｓｉ基板４０１の表面に自
然酸化膜４０６やＡｓイオン注入によって形成された欠
陥４０７が存在するために、ＣＶＤ法によってＷ膜４０
８を堆積すると、Ｗの局部的な入り込み４０９が起こり
、このＷの局部的な入り込み４０９が半導体装置のリー
ク電流の増加や耐圧の低下を引き起こし、半導体装置の
製造プロセス上大きな問題となっていた。When a tungsten film (hereinafter abbreviated as W film) 408 is selectively deposited in the contact hole 405 on this sample by the CVD method shown in FIG. (For example, Kakiuchi et al., Journal of the Institute of Electronics, Information and Communication Engineers, SDM87.
-150. p37) Problems to be Solved by the Invention In such a conventional method, since a natural oxide film 406 and defects 407 formed by As ion implantation exist on the surface of the Si substrate 401, the W film 40 is removed by the CVD method.
8, local intrusion 409 of W occurs, and this local intrusion 409 of W causes an increase in leakage current and a decrease in breakdown voltage of the semiconductor device, which is a major problem in the manufacturing process of semiconductor devices. .
本発明はこのような課題を解決するもので、簡単な構成
で半導体装置を製造でき、半導体装置のリーク電流の増
加や耐圧の低下を起こさない、良好な金属の堆積方法を
提供することを目的とするものである。The present invention solves these problems, and aims to provide a good metal deposition method that allows semiconductor devices to be manufactured with a simple configuration and that does not cause an increase in leakage current or a decrease in breakdown voltage of the semiconductor device. That is.
課題を解決するための手段
この課題を解決するために本発明は、半導体基板表面に
形成された第１の不純物拡散領域とほぼ同じかまたは狭
い領域に、第１の不純物拡散領域よりも深く第２の不純
物拡散を行った後に、金属の堆積を行うことにより、リ
ーク電流の増加や耐圧の低下のない、良好な金属の堆積
を形成できるようにしたものである。Means for Solving the Problem In order to solve this problem, the present invention provides a first impurity diffusion region formed on the surface of a semiconductor substrate, in which a first impurity diffusion region is formed in a region that is substantially the same as or narrower than the first impurity diffusion region. By performing metal deposition after performing the impurity diffusion in step 2, it is possible to form a good metal deposit without increasing leakage current or decreasing breakdown voltage.
作用
この構成により不純物拡散領域を広げずに深くすること
ができるので、Ｗの局部的な入り込みが起こった場合に
も、局部的な入り込みが８１基板まで到達することはな
い。その結果、リーク電流の増加や耐圧の低下が起こる
ことはなく、良好な金属の堆積を行うことができる。Effect: This structure allows the impurity diffusion region to be deepened without widening, so even if W locally penetrates, it will not reach the 81 substrate. As a result, good metal deposition can be performed without an increase in leakage current or a decrease in breakdown voltage.
また、Ｗを堆積して電極窓（以後ＣＷと略す）を形成す
ることにより、ＣＷを小さくすることができ半導体装置
の集積度を高めることができることとなる。Furthermore, by depositing W to form an electrode window (hereinafter abbreviated as CW), CW can be made smaller and the degree of integration of the semiconductor device can be increased.
実施例 以下第１図〜第３図を用いて本発明の詳細な説明する。Example The present invention will be explained in detail below using FIGS. 1 to 3.
（実施例１）
第１図（ａ＋〜第１第１図＋ｇ本発明の金属の堆積方法
の第１の実施例を示す。(Example 1) FIG. 1 (a+ to FIG. 1+g) shows a first example of the metal deposition method of the present invention.
まず第１図（ａｌに示すようにＳｉ基板１０１上のＬＯ
ＣＯ３酸化膜１０２で分離された領域に、深さ０．２μ
ｍのＡｓ拡散層１０３を形成し、つぎに、このＡｓ拡散
層の領域より少し狭くかつ深くＰ拡散層を形成するため
に、第１図ｆｂｌに示すようにフォトレジスト１０４を
用いてＰ注入窓１０５を形成し、続いて第１図（Ｃ１の
ようにＰ注入を行ってＰ注大大王１０６形成した後に第
１図ｉｄ）のようにフォトレジスト１０４を除去して熱
処理を行い、Ｐ拡散層１０７を形成する。First, as shown in FIG. 1 (al), the LO on the Si substrate 101
In the area separated by the CO3 oxide film 102, a depth of 0.2μ is formed.
m As diffusion layer 103 is formed, and then, in order to form a P diffusion layer slightly narrower and deeper than the region of this As diffusion layer, a P injection window is formed using a photoresist 104 as shown in FIG. 105 is formed, and then the photoresist 104 is removed and heat treated as shown in FIG. 107 is formed.
つぎに、このようにして形成したＡｓとＰの拡散層上に
、第１図ｔｅｌに示すように５ｉｎ２膜１０８を堆積し
、この５ｉ０２膜１０８に第１図（ｆ）に示すようにＣ
ＷＩ Ｏ９を形成した後に、第１図＋ｇ＋に示すように
ＣＶＤ法によってＣＷ内にのみ選択的にＷ膜を堆積し、
埋め込み電極を形成することができる。Next, a 5in2 film 108 is deposited on the As and P diffusion layer thus formed as shown in FIG.
After forming WI O9, as shown in Figure 1+g+, a W film is selectively deposited only in the CW by CVD method,
A buried electrode can be formed.
本発明の実施例１の方法によれば、Ｐの拡散層によって
Ａｓ拡散のみの０．２μｍよりも０．２μｍ深い０．４
μｍの深さに、基板とのＰｎ結合が形成されるため、Ｗ
の局部的な入り込み１１１が形成された場合にも、Ｗの
局部的な入り込み１１１が８１基板に達せず、接合リー
ク電流の増加や耐圧の低下といった問題か起こる心配か
ない。According to the method of Example 1 of the present invention, the P diffusion layer provides a depth of 0.4 μm, which is 0.2 μm deeper than the 0.2 μm of As diffusion alone.
Since a Pn bond with the substrate is formed at a depth of μm, W
Even if a local intrusion 111 of W is formed, the local intrusion 111 of W will not reach the 81 substrate, and there is no fear that problems such as an increase in junction leakage current or a decrease in breakdown voltage will occur.
なお、本実施例においては、基板としてＳｉ基板を用い
たが、Ｓｉ以外の材料、例えばＧａＡｓなどの化合物半
導体を用いた場合であっても同様の効果が得られる。ま
た拡散する不純物としてｎ形不純物であるＡｓとＰの組
合せを用いたか、拡散深さの異なる不純物拡散の組合せ
であれば、拡散する不純物は何でも構わないし、さらに
同し不純物をマスクを変えて注入し、注入エネルギーを
変えることによって深さの異なる拡散層の組合せを作る
こともできる。またＰ形不純物についても、同様の効果
か得られることはいうまでもない。In this embodiment, a Si substrate is used as the substrate, but the same effect can be obtained even when a material other than Si, for example a compound semiconductor such as GaAs, is used. Furthermore, as long as a combination of n-type impurities As and P is used as the impurity to be diffused, or a combination of impurity diffusions with different diffusion depths, any type of impurity can be used. Furthermore, the same impurity can be implanted by changing the mask. However, it is also possible to create combinations of diffusion layers with different depths by varying the implantation energy. It goes without saying that similar effects can be obtained with P-type impurities.
（実施例２）
第２図（ａ＋〜＋〜図（ｉ）に本発明の金属の堆積方法
の第２の実施例を示す。(Example 2) A second example of the metal deposition method of the present invention is shown in FIG. 2 (a+ to (i)).
まず第２図（ａｌに示すようにＳｉ基板２０１上のＬＯ
ＧＯＳ酸化膜２０２で分離された領域に深さ０．２μｍ
のＡｓ拡散層２０３を形成し、つぎに、このＡｓ拡散層
の領域より少し狭くかつ深くＰ拡散層を形成するように
、フォトレジスト２０４を用いてＰ注入窓２０５を形成
した後にＰ注入を行って、Ｐ注入層２０６を形成する。First, as shown in FIG. 2 (al), the LO on the Si substrate 201
A depth of 0.2 μm is formed in the region separated by the GOS oxide film 202.
Next, P implantation is performed after forming a P injection window 205 using a photoresist 204 so as to form a P diffusion layer slightly narrower and deeper than the region of this As diffusion layer. Then, a P injection layer 206 is formed.
続いて第２図（ｂｌに示すように、レジストを除去して
熱処理を行い、深さ０．４μｍのＰ拡散層２０７を形成
し、厚さ１μｍの５１０２膜２０８を堆積する。つぎに
第２図（Ｃ１に示すように、直径０．５μｍのＣＷ２Ｏ
９を開孔した後、第２図ｆｄｌに示すようにＣＶＤ法に
よってＣＷ内にのみ選択的にＷ膜を堆積し、最後に第２
図ｔｅｌのように厚さ１μｍのＡｌ膜２１２を堆積して
、埋め込みコンタクト電極を形成することができる。Subsequently, as shown in FIG. 2 (bl), the resist is removed and heat treatment is performed to form a P diffusion layer 207 with a depth of 0.4 μm, and a 5102 film 208 with a thickness of 1 μm is deposited. As shown in the figure (C1), CW2O with a diameter of 0.5 μm
After opening the hole 9, a W film is selectively deposited only in the CW by the CVD method as shown in FIG.
A buried contact electrode can be formed by depositing an Al film 212 with a thickness of 1 μm as shown in FIG.
本発明の実施例２の方法によれば、実施例１と同じ理由
により、Ｐの拡散層によって、Ａｓの拡散層深さ０．２
μｍよりも０．２μｍ深い０．４μｍの深さに、基板と
のＰｎ結合が形成されるため、第２図＋ｄｌのＷの局部
的な入り込み１１が形成された場合にも、接合リーク電
流の増加や耐圧の低下などの問題が起こらない。According to the method of Example 2 of the present invention, for the same reason as Example 1, the depth of the As diffusion layer is 0.2 by the P diffusion layer.
Since a Pn bond with the substrate is formed at a depth of 0.4 μm, which is 0.2 μm deeper than μm, even if a local W intrusion 11 of +dl in Fig. 2 is formed, the junction leakage current will be reduced. Problems such as increase in voltage and decrease in withstand voltage do not occur.
実施例２の方法を用いた場合の最も大きな効果は、ＣＷ
の寸法を小さくすることができることである。この結果
、ＣＷをアクティブエリヤを形成する領域（不純物拡散
領域）より小さく形成できるという効果が生まれ、最終
的にはチップ寸法を小さくすることができる。これをわ
かりやすく説明したのが第２図げ）である。第２図げ）
Ｓｌ基板２１３上のＬＯＧＯ９酸化膜２１４で分離され
た領域に深さ０．２μｍのＡｓ拡散層２１５を形成し、
厚さ１μｍの５１０２膜２１６を堆積して、２図ＦＣ＋
と全く同様に、同じ直径０．５μｍのＣＷ２１７を形成
し、厚さ１μｍのＡｌ配線２１８を堆積する。第２図げ
）を見てわかるように、スパッタリング法によるＡｊｌ
’膜の堆積では、直径０．５μｍのコンタクトホールを
埋めることはできず、コンタクトホールの底部にＡｌの
断線２１９か形成される。The greatest effect when using the method of Example 2 is that CW
It is possible to reduce the size of the As a result, the effect that the CW can be formed smaller than the region forming the active area (the impurity diffusion region) is produced, and ultimately the chip size can be reduced. This is explained in an easy-to-understand manner in Figure 2. 2nd figure)
An As diffusion layer 215 with a depth of 0.2 μm is formed in a region separated by a LOGO9 oxide film 214 on the Sl substrate 213,
A 5102 film 216 with a thickness of 1 μm was deposited to form the FC+
In exactly the same manner as above, a CW 217 with the same diameter of 0.5 μm is formed, and an Al wiring 218 with a thickness of 1 μm is deposited. As you can see in Figure 2), Ajl by sputtering method.
By depositing the film, it is not possible to fill a contact hole with a diameter of 0.5 μm, and an Al break 219 is formed at the bottom of the contact hole.
実施例１と実施例２とにあえて分けて示した理由は、こ
のコンタクトホールの直径の問題であり、実施例２の方
法を用いれば、Ａｊ’膜を直接堆積してコンタクト電極
を形成する場合よりもコンタクト寸法を小さくできるこ
とである。すなわち実施例２の方法では直径０．３μｍ
程度のＣＷでもＣＶＤ法によるＷの埋め込みコンタクト
電極を形成することができる。第２図（９〜第２図（ｉ
）でこのことをわかりやすく説明する。すなわち第２図
（ｇ）に示すような従来のＡＡ配線コンタクト電極に代
わって、第２図ｆｈｌに示すような本発明のＷコンタク
ト電極を構成することにより、ＣＷす・イズの縮少がで
きるので、Ｐ拡散層の領域はＡｓ拡散層の領域より十分
狭くでき、Ｐ拡散層の形成によるデバイス特性の変化は
ない。さらにＣＷサイズが縮小できることから、第２図
（ｉｌに示すように不純物拡散領域（以後ＯＤサイズと
称す）の縮小も可能となり、従ってチップサイズそのも
のが縮小できるため、デバイスの集積度を上げることが
できる。The reason why Example 1 and Example 2 are intentionally shown separately is the problem of the diameter of this contact hole.If the method of Example 2 is used, it will be difficult to form a contact electrode by directly depositing the Aj' film. This means that the contact dimensions can be made smaller. That is, in the method of Example 2, the diameter is 0.3 μm.
A buried W contact electrode can be formed by the CVD method even with a certain degree of CW. Figure 2 (9-Figure 2 (i)
) to explain this in an easy-to-understand manner. That is, by configuring the W contact electrode of the present invention as shown in FIG. 2fhl in place of the conventional AA wiring contact electrode as shown in FIG. 2(g), the CW size can be reduced. Therefore, the region of the P diffusion layer can be made sufficiently narrower than the region of the As diffusion layer, and there is no change in device characteristics due to the formation of the P diffusion layer. Furthermore, since the CW size can be reduced, it is also possible to reduce the impurity diffusion region (hereinafter referred to as OD size) as shown in Figure 2 (il), and therefore the chip size itself can be reduced, making it possible to increase the degree of device integration. can.
（実施例３）
第３図ｆａ）〜第３図（Ｃ１に本発明の金属の堆積方法
の第３の実施例を示す。(Example 3) Figures 3fa) to 3(C1) show a third example of the metal deposition method of the present invention.
まず第３図ｆａｔに示すように、Ａｓ拡散層３０４とＢ
拡散層３０５０両方の上のＳ ｉ Ｏ２膜３０３を開孔
してｎ型とｐ型のコンタクトホール３０９および３１０
を形成した後、Ｂ拡散層３０５上のｐ型のコンタクトホ
ール３１０のみをフォトレジスト３０６でカバーし、Ｐ
イオン注入３０７を行って、Ｐ注入層３０８を形成する
。つぎに第３図ｔｂ）に示すように、フォトレジスト３
０６を除去して熱処理を行い、Ｐ拡散層３１１を形成し
、最後に第３図（Ｃ１に示すようにＷ膜３１２とＡｊ７
配線３１３を形成することによって、Ｗの選択堆積によ
るコンタクト配線を行うことができる。First, as shown in FIG. 3, the As diffusion layer 304 and the B
The S i O 2 film 303 on both the diffusion layers 3050 is opened to form n-type and p-type contact holes 309 and 310.
After forming P, only the p-type contact hole 310 on the B diffusion layer 305 is covered with a photoresist 306, and the P
Ion implantation 307 is performed to form a P implantation layer 308. Next, as shown in FIG. 3tb), the photoresist 3
06 is removed and heat treated to form a P diffusion layer 311. Finally, as shown in FIG. 3 (C1), the W film 312 and Aj7 are
By forming the wiring 313, contact wiring can be performed by selectively depositing W.
本発明の実施例３の方法は、本発明の最も容易に実施で
きる方法であり、実用上極めて有用である。The method of Example 3 of the present invention is the method of the present invention that can be implemented most easily and is extremely useful in practice.
発明の効果
以上の実施例の説明からも明らかなように、本発明によ
れば、極めて簡易な構成でＷの局部的な入り込みによる
半導体装置のリーク電流の増加や耐圧の低下が起こらな
い良好な金属の堆積を行うことができる。また、Ｗを堆
積してＣＷを形成することにより、ＣＷを縮小すること
ができ、半導体装置を小型化して集積度を高めることが
でき、実用上極めて有用である。Effects of the Invention As is clear from the above description of the embodiments, the present invention has an extremely simple structure and provides a good structure in which no increase in leakage current or decrease in breakdown voltage of the semiconductor device due to local penetration of W occurs. Metal deposition can be performed. Furthermore, by depositing W to form a CW, the CW can be reduced, the semiconductor device can be miniaturized, and the degree of integration can be increased, which is extremely useful in practice.
第１図（ａ）〜（鎖は本発明の第１の実施例の金属の堆
積方法を示す断面図、第２図（ａｌ〜ｆｉｔ本発明の第
２の実施例の金属の堆積方法を示す断面図、第３図（ａ
）〜＋ｃ＋は本発明の第３の実施例の金属の堆積方法を
示す断面図、第４図（ａｌ、 ｆｂｌは従来の金属の堆
積方法を示す断面図である。
１０１．２０１．３０１・・・・・・Ｓｉ基板、１０２
゜２０２．３０２・・・・・・ＬＯＣＯ８酸化膜、１０
３゜２０３．３０４・・・・・・Ａｓ拡散層、１０４，
２０４゜３０６・・・・・・フォトレジスト、１０５，
２０５・・・・・・Ｐ注入窓、１０６，２０６，３０８
・・・・・・Ｐ注入層、１０７．２０７，３１１・・・
・・・Ｐ拡散層、１０８゜２０８．３０３・・・・・・
Ｓｉｎ、膜、１０９，２０９゜３０９．３１０・・・・
・・電極窓（ＣＷ）、１１０２１０．３１２・・・・・
・Ｗ膜、１１１，２１１・・・・・・Ｗの局部的な入り
込み、２１２，３１３・・・・・・Ａｌ膜。Figures 1(a) to (chains are cross-sectional views showing the metal deposition method of the first embodiment of the present invention, and Figure 2 (al to fit) showing the metal deposition method of the second embodiment of the present invention. Cross-sectional view, Figure 3 (a
)~+c+ are cross-sectional views showing the metal deposition method of the third embodiment of the present invention, and FIG. 4 (al, fbl are cross-sectional views showing the conventional metal deposition method. 101.201.301... ...Si substrate, 102
゜202.302...LOCO8 oxide film, 10
3゜203.304...As diffusion layer, 104,
204゜306...Photoresist, 105,
205...P injection window, 106, 206, 308
...P injection layer, 107.207,311...
...P diffusion layer, 108°208.303...
Sin, membrane, 109,209°309.310...
・・Electrode window (CW), 110210.312・・・・
- W film, 111, 211... Local intrusion of W, 212, 313... Al film.
Claims (2)
域上の絶縁膜を開孔して形成したコンタクトホールに、
前記第１の不純物拡散領域への電極を形成するために、
前記第１の不純物拡散領域とほぼ同じかまたは狭い領域
に、前記第１の不純物拡散領域よりも深く第２の不純物
拡散を行った後に、金属の堆積を行う半導体装置の製造
方法。(1) In the contact hole formed by opening the insulating film on the first impurity diffusion region formed on the surface of the semiconductor substrate,
In order to form an electrode to the first impurity diffusion region,
A method for manufacturing a semiconductor device, comprising performing a second impurity diffusion in a region substantially the same as or narrower than the first impurity diffusion region and deeper than the first impurity diffusion region, and then depositing metal.
ールをマスクとして、第２の不純物拡散のためのイオン
注入を行うことによって第２の不純物拡散層を形成する
請求項１記載の半導体装置の製造方法。(2) The method of manufacturing a semiconductor device according to claim 1, wherein after forming the contact hole, a second impurity diffusion layer is formed by performing ion implantation for second impurity diffusion using the contact hole as a mask.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18910590A JPH0474417A (en) | 1990-07-16 | 1990-07-16 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18910590A JPH0474417A (en) | 1990-07-16 | 1990-07-16 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0474417A true JPH0474417A (en) | 1992-03-09 |
Family
ID=16235450
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18910590A Pending JPH0474417A (en) | 1990-07-16 | 1990-07-16 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0474417A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0714800A (en) * | 1993-04-30 | 1995-01-17 | Internatl Business Mach Corp <Ibm> | Forming contact on front side surface of silicon substrate of silicon-on-insulator (soi) wafer |
| US5476800A (en) * | 1994-01-31 | 1995-12-19 | Burton; Gregory N. | Method for formation of a buried layer for a semiconductor device |
| JP2007019518A (en) * | 2005-07-08 | 2007-01-25 | Infineon Technologies Austria Ag | Semiconductor component having field stop |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5440083A (en) * | 1977-09-05 | 1979-03-28 | Nec Corp | Manufacture of semiconductor device |
| JPS54103672A (en) * | 1978-02-01 | 1979-08-15 | Nec Corp | Production of semiconductor device |
-
1990
- 1990-07-16 JP JP18910590A patent/JPH0474417A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5440083A (en) * | 1977-09-05 | 1979-03-28 | Nec Corp | Manufacture of semiconductor device |
| JPS54103672A (en) * | 1978-02-01 | 1979-08-15 | Nec Corp | Production of semiconductor device |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0714800A (en) * | 1993-04-30 | 1995-01-17 | Internatl Business Mach Corp <Ibm> | Forming contact on front side surface of silicon substrate of silicon-on-insulator (soi) wafer |
| US5476800A (en) * | 1994-01-31 | 1995-12-19 | Burton; Gregory N. | Method for formation of a buried layer for a semiconductor device |
| JP2007019518A (en) * | 2005-07-08 | 2007-01-25 | Infineon Technologies Austria Ag | Semiconductor component having field stop |
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