JPH02180023A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce an emitter area by providing a contact hole in need of connection to an emitter region fully across the size of the emitter region. CONSTITUTION:An annular polysilicon layer 9 for a bipolar transistor is disposed, on which a second resist layer 11 is deposited except for an exposed thin oxide layer 7 portion of an outer peripheral portion of said layer 9 and for part of an insulator layer 6. An external base 10 is disposed with the annular polysilicon layer 9 as a mask. After exfoliation of a third resist layer 14, a CVD coating is deposited over the entire surface, and thereafter a contact hole is formed by fusing and removing portions corresponding to the emitter 12, collector lead region 13, and external base 10 by an RIE process selectively and according to a desired dimension. Hereby, a contact hole for the emitter is not needed to be formed inside the emitter to permit an emitter area to be reduced.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Field of Application) The present invention relates to a bipolar transistor with an emitter having minute dimensions, and particularly to a bipolar transistor using an ion implantation method and suitable for complex devices. be.

(Prior Art) When forming the emitter of a bipolar transistor by ion implantation, first a prepared p-type silicon semiconductor substrate 50 is used, as shown in FIGS.
sb is injected by the usual method to increase the surface concentration to I
It should be about 10"c++-3.

An n-type epitaxial layer 51 is deposited on the surface of the semiconductor substrate including this sb-introduced layer, and the sb introduced at this time is diffused into the silicon semiconductor substrate 50 and auto-doped into the low-type epitaxial layer 51, so that this diffusion layer A resistive buried region 52 is formed which lowers the resistance of the collector region of the transistor, both of which will be described later.

The n-type epitaxial layer 51 is deposited to a thickness of 2.2 to 2.7 μm, and contains p as an impurity of 5 to 8×1011
This n-type epitaxial layer 51
A p-type isolation region 53 divided into islands is provided by selectively doping a p-type impurity such as boron and then performing an activation process, and an island region 54 is formed in the middle thereof. As a method for forming this isolation region, in addition to the diffusion method, it is also possible to use a method of forming a trench groove at a position where this isolation region is to be formed and then burying it with a dielectric material.

On the surface of the n-type epitaxial layer 51 subjected to such treatment, an insulating layer 55 having a thickness of 5,000 to 10,000 angstroms is formed as usual, which functions as a field oxide film of a 1-transistor.

For this insulating layer 55, as shown in FIG. Apply silicon to the oxidation mask. That is, after forming an insulator layer 55 of a predetermined thickness in the so-called field part of the element by placing this mask on the thin part of the figure, the oxide film formed on this thin part is once removed. Then a chemically pure oxide layer 56 is deposited again.

By the way, boron ions are implanted through this thin oxide layer 56 at a dose of 5.times.10@13 cm@-2 and an acceleration voltage of 40 KeV to form the internal base 57 of the bipolar transistor.

Next, it is necessary to install a contact for this internal base 57, but since its concentration is at the limit that can be applied to the formation of an ohmic contact, a new external base 58 is installed. That is, the resist layer 59 is located at a location other than the planned installation location.
After coating with boron at a dose of 1.2X10”cm-
2 is implanted at an acceleration voltage of 40 KeV to form the structure as shown in FIG.

Furthermore, the process moves on to the process of forming the emitter 60 and collector lead-out electrode 61 necessary to perform the function of the transistor. For this purpose, as shown in FIG.
~N epitaxial growth layer 54 that functions as the collector region of the transistor, and the thin oxide layer 5G formed on the internal base 57 and deposited on the surface except for a part of the thin oxide layer 5G corresponding to the planned formation position of the emitter 6o and the collector extraction region 61. The second resist 62 thus formed is patterned by a known photolithography process to form a window, as seen in FIG. 3C.

Using this second resist 62 as a mask, the thin oxide layer 56 exposed in this window is removed by isotropic etching using a solution such as ammonium fluoride, and then arsenic is applied at a dose of about 10"am"-2. It is formed by implantation at an acceleration voltage of 40 KeV.

Next, after removing the second resist 1-62, the entire surface is coated with CVD (
Chemjca] Vapor Depositio
n) After depositing the 5in2 film 63, the emitter 60.
Positions corresponding to the collector extraction region 61 and the external base 58 are selectively removed by isotropic etching means to provide contact holes in each.

As a result, the emitter 60 is exposed. Collector extraction area 61
After depositing Afl or AQ alloy on the entire surface including the external base 58, patterning is performed by RIE method to obtain the pattern shown in FIG. 3d.
The bipolar transistor is completed by forming each electrode 64 as shown in FIG.

(Problem to be Solved by the Invention) In a transistor formed by such a method, the photolithography process is repeated, and the mask alignment process is naturally performed multiple times. Discrepancies must be taken into account.

Furthermore, since the contact hole formed in the emitter region is formed inside the emitter region, its outer diameter must be made larger, which undeniably has the disadvantage of reducing the degree of integration of elements on a semiconductor substrate of a constant area. .

The present invention provides a novel method for manufacturing a semiconductor device that eliminates the above-mentioned drawbacks, and in particular provides a semiconductor device having a fine emitter.

[Structure of the invention]

(Means for Solving the Problems) In order to achieve this object, in the present invention, an annular polysilicon layer is laminated and arranged on a thin oxide layer that is formed adjacent to and continuous with the emitter region, and this is used to form the emitter region. This manufacturing method realizes a small-area emitter by applying it as a self-aligning mask for ion implantation, and also serving as an etching stopper in the contact 1 to hole formation process.

(Function) As mentioned above, bipolar elements are rapidly becoming more complex, and the so-called Bi-MO8 element, in which MO5 elements and bipolar elements are formed in thousands, has been developed and has already entered the stage of practical use. Although there are not many types of composite elements, there is a need for higher speed bipolar elements in r3i-MO3 elements, and we are focusing on the development of such devices.

By the way, in manufacturing this Bi-MO3 element, MO
Due to the structure of the MO5 element, a polycrystalline silicon (hereinafter referred to as polysilicon) Depo (Deposition) process is essential, and the present invention focused on this and changed the polysilicon applied to the gate electrode of the MO5 element to Bi-MO3. This method is used to form the emitter of a bipolar transistor device.

This is because polysilicon for the gate electrode of this MO3 element was simultaneously deposited on a thin oxide layer that was placed continuously and adjacent to the main pure region that was to be used to form the emitter of the bipolar transistor.

As a result, the emitter contact hole does not need to be installed inside the emitter, so its area can be reduced.Furthermore, the high frequency characteristics of the device are improved by reducing the junction capacitance. There is also the advantage of increasing the degree of device integration.

(Example) The present invention will be explained in detail with reference to FIGS. 1a, b, c, and d and FIG. 2. Although descriptions that overlap with those of the prior art may appear for convenience, new numbers will be added to explain them.

FIGS. 1A, 1B, 1D, and 1D show cross-sectional views of the manufacturing process of a medium bipolar element of a composite element according to the present invention, and FIG. 2 is a sectional view showing a reduced state of a bipolar one helangister.

A p-type silicon semiconductor substrate 1 is prepared, and sb is introduced into the substrate from the − surface to a surface concentration of 1×10”cm−”.
After this, an n-type epitaxial layer 2 is deposited on the entire surface including this sb-introduced layer.

The sb introduced during this process is diffused into the silicon semiconductor substrate 1 and doped with O1 (Aut).

Due to the doping phenomenon, an n+ type buried region 3 is formed as shown in FIG. .2 μm~
It was deposited at 2.1 mQ, and the impurity was 5 to 8
Contains 10"Cm-2.

For example, boron is introduced into a selective position of this n-type epitaxial layer 2 and an activation treatment is performed to form an isolation region 4 penetrating the n-type epitaxial layer 2, thereby forming an island region 5 therein. do.

As a means for installing this isolation region, it is also possible to electrically isolate the isolation region by filling a trench groove provided at the intended formation position with a dielectric material.

After completing these steps, the surface of the semiconductor substrate 1 is coated with an insulating layer 6 formed by a selective oxidation method to a thickness of 5,000 to 5,000 nm to be used as a field oxide layer of the device.
By maintaining the thickness at about 10,000 angstroms, the cross-sectional view of FIG. 1a is obtained. Note that this insulator layer 6 is selectively oxidized (L
OGO5) It is not limited to M, and a conventional thermal oxidation film can also be applied.

In the insulator layer 6 shown in this drawing, the thinner part is where the oxidation-resistant mask silicon nitride used when forming the selective oxide film was placed, and is formed by the heat load during this process. oxide layer.

However, for example, C/MO5 constituting the Bi-MO5 element
In devices and bipolar transistors, the higher the chemical purity of the oxide layer placed adjacent to the impurity region, the better the device characteristics will be. Therefore, in this pixel element, after peeling off the oxide layer once provided, a new thin oxide layer 7 of good purity is coated to a thickness of 500 angstroms.

Next, the process moves on to the step of forming the internal base 8 of the bipolar transistor. For this purpose, the surface other than the thin oxide layer 7 is coated with a first resist layer, a pattern is formed by a known photolithography process, and boron is passed through the thin oxide layer 7 using the first resist layer as a mask. Dose amount 5×1013
The internal base 8 is installed by implanting under cII+-2 acceleration voltage conditions of 40 KeV. Its cross-sectional view is shown in FIG. 1a.

After this step, the first resist layer is removed and a step of forming polysilicon layer 9 is started. As mentioned above, this step involves, for example, depositing a polysilicon layer on the entire surface of the semiconductor substrate 1 at the time of forming the gate electrode of the C/MO3 element, and then performing RIE.
(Reactive Ion Etching) to form a pattern that accurately maintains predetermined dimensions.

At the same time, AQ or Af1 alloy (AIl-5i-Cu,
A contact hole is formed by this RIE method in order to make contact with a wiring layer (not shown) made of An-5i).

For this bipolar transistor, a ring-shaped polysilicon layer 9 is provided as shown in FIG. By the way, since the concentration of the internal base 8 is almost at the limit of that required for ohmic contact, the external base 10 is formed to ensure a certain concentration.

Therefore, as shown in FIG. 1, a second resist layer 11 is applied except for the outer peripheral portion of the annular polysilicon layer 9, the exposed thin oxide layer 7, and a portion of the insulating layer 6, and then The pattern is formed by a known photolithography process. Here, using the annular polysilicon layer 9 as a mask, boron is applied at a dose of 1.2 x 10111011 through the obtained window.
The external base 10 is installed by implanting into the internal base with an i acceleration voltage of 40 KeV.

This ion implantation step is carried out through the thin oxide layer 7 as well as the internal base 8.

Further, the emitter 12 and the collector extraction region 13 are formed by arsenic ion implantation. For this purpose, a portion of the thin oxide layer 7 with a thickness of 500 angstroms is carried out in the presence of a third resist layer I4, as shown in FIG. 1C. That is, the layer 14 is deposited on the third resist 1 in areas other than the areas where the emitter 2 and the collector extraction region 13 are to be formed, and as described above, a pattern is formed by a known photolithography process and a thin oxide layer is formed. After dissolving the 7 portions in an isotropic etching process using a solution such as ammonium fluoride, the dose amount is 101.
It is formed by implanting arsenic ions under ion implantation conditions of Sc, -2.

Next, after peeling off the third resist layer 14, apply CV to the entire surface.
After depositing the D coating 15, this emitter 12. A contact hole is formed by selectively dissolving the area corresponding to the collector extraction region 13 and the external base 10 according to the predetermined dimensions by RIE method, and a conductive metal AQ or Af1 alloy of the same type as the wiring layer is formed in this hole. is coated to form each electrode 16 to complete a bipolar one helangister.

In this embodiment, an npn type bipolar transistor is shown, but it can also be applied to a pnp type.

〔Effect of the invention〕

As described above, in the method for manufacturing a semiconductor device according to the present invention, the contact hole necessary for connecting to the emitter region can be installed in the radius of the emitter region.
This has the great advantage of reducing the emitter area.

As a result, the junction capacitance is reduced, and the high frequency characteristics are improved compared to the conventional one.Furthermore, as the emitter area is reduced, the cell area of one helangistor is also reduced, and as a result, the number of elements that can be integrally integrated on the semiconductor substrate increases.

FIG. 2 shows a cross-sectional view and a plan view of a bipolar transistor, making the above-mentioned relationship between the emitter and the contact hole clear.

[Brief explanation of the drawing]

Figures 1 a, b, c, and d are cross-sectional views showing the manufacturing process of the embodiment, Figure 2 is a diagram that shows the cross-sectional view and plan view together, and Figure 3 a, b, c, and d are the conventional FIG. 3 is a cross-sectional view showing the manufacturing process.

Claims (1)

[Claims] A step of covering the surface of a semiconductor layer of a certain conductivity type with an insulating layer, a step of providing an isolation region that penetrates this semiconductor layer portion, and a step of removing the insulating layer portion facing the semiconductor layer surrounded by the isolation region. forming an opening, filling the opening with an oxide layer thinner than the insulating layer, and implanting an impurity of the opposite conductivity type through the thin oxide layer into an adjacent semiconductor layer of a certain conductivity type. a step of forming an annular polysilicon layer on the thin oxide layer; and a step of forming an annular polysilicon layer on the thin oxide layer, a portion of the insulating layer, an outer peripheral portion of the polysilicon layer, and a portion of the thin oxide layer located therebetween. In addition, a first mask layer is coated, and an impurity of an opposite conductivity type is introduced into the internal base region through a thin oxide layer portion defined by the first mask layer and the outer peripheral portion of the annular polysilicon layer. forming an external base region;
removing the first mask layer; covering the annular polysilicon layer with a second mask layer other than the thin oxide layer exposed at the center; and conducting conductivity in the exposed thin oxide layer. a step of introducing type impurities, a step of removing this second mask layer, a step of depositing an interlayer insulating film on the surface of the semiconductor substrate including the annular polysilicon layer, and a step of depositing the interlayer insulating film and the thin oxide layer. It is characterized by comprising a step of selectively removing the polysilicon layer, and a step of installing a contact hole having a diameter smaller than the outer diameter of the annular polysilicon layer in the interlayer insulating film formed continuously on the annular polysilicon layer. A method for manufacturing a semiconductor device.