JPH0529330A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To provide a method of manufacturing a semiconductor device, wherein elements are made fine and where by a high-speed device can be realized. CONSTITUTION:A silicon oxide film 7 and an oxidation-resistance film 8 are formed only in a region along the sidewall of a silicon film 4 which constitutes lead-out electrodes. The latter is used as a mask for an oxidation operation and removed. Thereby, it is utilized to form an ion implantation region 11 whose width is the same as its width. The former is utilized to insulate the extraction electrode 4 from the ion implantation region 11.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device. More specifically, the present invention relates to a method of manufacturing a semiconductor device such as a lateral bipolar transistor using an SOI substrate, which enables miniaturization and speedup of elements.

[0002]

2. Description of the Related Art A lateral bipolar transistor using an SOI substrate has the effect of reducing the parasitic capacitance by using the SOI substrate and, in addition, the base-collector area can be reduced, so that the junction capacitance between the base and collector is reduced. The semiconductor device is capable of reducing In the conventional manufacturing method of the lateral bipolar transistor, the openings of the base, the collector and the emitter are formed by the photolithography technique.

[0003]

In a lateral bipolar transistor using an SOI substrate, it is desirable to provide the emitter contact region and the base region in proximity to each other because the accumulation of minority carriers in the emitter is reduced, which is desirable for high speed operation. That is. In addition, reducing the base width also shortens the base traveling time of the carrier, which also leads to higher speed.

In the conventional manufacturing method, since the openings, electrodes, etc. of the base, collector and emitter are formed by the photolithography technique as described above, these widths are set so that the alignment margin in the photolithography technique and the minimum formable width. It will depend on the dimensions. The lower limit of the alignment margin and the minimum dimension accuracy of the photolithography technique is about 0.25 μm. Therefore, when the photolithography technique is formed with high accuracy, as shown in FIG. 5, the distance between the emitter contact 41 and the base region 42 is about 0.75 μm, and the base width is 0.25 μm.
It will be about. In this figure, 40 is a device layer, 43 is an emitter region, 44 is an insulating film, 45 is an emitter electrode, 46 is a base electrode, A is a photolithography technique alignment margin, and B is the minimum that can be formed by the photolithography technique. It is a dimension.

On the other hand, in a normal vertical bipolar transistor, the alignment margin and the minimum size that can be formed are each about 0.1 μm. Therefore, the lateral bipolar transistor manufactured by the conventional method is a vertical bipolar transistor. However, the distance between the emitter contact region and the base region is long and the base width is wide, which is not suitable for high-speed operation.

It is an object of the present invention to provide a method of manufacturing a semiconductor device capable of realizing a high speed device by enabling miniaturization of elements.

[0007]

A method of manufacturing a semiconductor device according to the present invention is a method of forming a dopant on a part of exposed silicon on a substrate surface separated by silicon oxide and on silicon oxide adjacent to the exposed silicon. The doped silicon film and the silicon oxide film are sequentially stacked to form a predetermined shape, and the dopant in the silicon film is diffused into the underlying silicon by heating to form a diffusion region, and the remaining exposed portion is exposed. After forming a pad oxide film by thinly oxidizing the as-deposited silicon surface, the silicon oxide film and the oxidation resistance are applied only to the region on the pad oxide film along the sidewall of the previously formed silicon film and the silicon oxide film. Film is sequentially formed, and the oxidation resistant film is used as a mask to perform oxidation to further oxidize silicon in the region of the pad oxide film, and the oxidation resistant film. Selectively remove only the pad oxide underneath to expose a silicon region of width comparable to the width of the oxidation resistant film, and in this region, the previously formed silicon. And a step of forming an ion-implanted region by ion-implanting while leaving the silicon oxide film on the side wall of the film and the silicon oxide film.

FIG. 1 shows a diagram for explaining the principle of the method of the present invention. In FIG. 1A, 1 is a silicon oxide substrate, 2 is silicon in an element region on the silicon oxide substrate 1, and the elements are previously separated by a silicon oxide film 3. Further, on a part of the exposed silicon in the device region, a silicon film 4 having a predetermined shape and doped with a dopant and a silicon oxide film 5 thereon are further formed in advance. At this time, the films 4 and 5 are overlaid on the silicon oxide film 3 adjacent to the silicon below them.
Then, the dopant in the silicon film 4 is diffused into the underlying silicon by heating to form the diffusion region 10. Further, a thin pad oxide film 6 is formed on the exposed exposed silicon surface.
Is formed. At this time, it does not matter that a thin oxide film is formed on the sidewalls of the silicon film 4 and the silicon oxide film 5. Then, in the method of the present invention, the silicon oxide film 7 and the oxidation resistant film 8 are sequentially formed only on a partial region of the pad oxide film 6 along the sidewalls of the silicon film 4 and the silicon oxide film 5. In FIG. 1A, W ₁ and W ₂ represent the widths of the silicon oxide film 7 and the oxidation resistant film 8, respectively.

Next, as shown in FIG. 1B, oxidation is performed using the oxidation resistant film 8 as a mask to further oxidize the silicon in the exposed pad oxide film region to form a thick oxide film. 9 is formed. Then, the oxidation resistant film 8 and the pad oxide film under this film are selectively removed in order to expose silicon in a region having a width equal to the width W ₂ of the oxidation resistant film 8. If the dopant is ion-implanted into the silicon of the exposed region using the remaining oxide films 3, 5, 7, 9 as a mask, as shown in FIG. 1C, the width W ₂ of the oxidation resistant film 8 is reduced. An ion-implanted region 11 having a width equal to that of is formed. The silicon oxide film 7 having the width W ₁ adjacent to the removed oxidation resistant film is left as it is, and the extraction electrode constituted by the silicon film 4 in contact with the diffusion region 10 and the ion implantation region 11 are contacted later. An insulating layer that separates the extraction electrode formed by the above is formed.

The silicon film and the silicon oxide film formed in advance on a part of the exposed silicon on the surface of the element-isolated substrate can be sequentially deposited on the entire surface and then patterned together to form a desired shape. The silicon film is doped with a suitable dopant. Doping of the dopant may be performed simultaneously with the deposition of the silicon film. A part of the dopant in the silicon film is diffused into the underlying silicon by heating after patterning to form a diffusion region. Also, the silicon film, which is doped with the dopant, is later used as an extraction electrode for the diffusion region. As will be described later, the silicon film as the extraction electrode has no possibility of coming into contact with the ion implantation zone, so that no tunnel leak current occurs between them. Therefore, the constituent material of the silicon film may be polysilicon or single crystal silicon obtained by epitaxial growth.

The silicon oxide film on the silicon film is used as an insulating film. The silicon oxide film formed only in a partial region on the pad oxide film along the sidewalls of the silicon film and the silicon oxide film which are overlapped is shown in FIG.
As shown by 7 in (a), the silicon oxide film 7 is removed only in the direction perpendicular to the substrate by depositing it on the entire surface by the CVD method and then performing anisotropic etching by reactive ion etching. Then, as shown in FIG. 2B, the silicon oxide film 7 having the width W ₁ can be formed only in the regions along the sidewalls of the silicon film 4 and the silicon oxide film 5 which are formed in advance. At this time, it is considered that a thin oxide film is formed on the sidewalls of the silicon film 4 and the silicon oxide film 5 as shown in FIG. 2A at the time of forming the pad oxide film preceding this. The thin oxide film does not interfere with the method of the present invention. The width W ₁ of the silicon oxide film 7 formed here can be set to about 0.1 μm or less.

A silicon nitride film (Si _x N _y ) or silicon is suitable as the oxidation resistant film 8 of width W ₂ (FIG. 1A) which is further formed next to the silicon oxide film of width W ₁ . It is an oxynitride film (Si _x O _y N _z ). These act as effective masks when further oxidizing the silicon in the region of the pad oxide and prevent oxidation of the silicon underlying the oxidation resistant film. The silicon nitride film and the silicon oxynitride film are deposited on the entire surface by the CVD method and the subsequent reaction as in the case of the silicon oxide film 7 formed before that (FIGS. 2A and 2B). By anisotropic etching by the characteristic ion etching, it can be easily formed on the side of the silicon oxide film 7 as illustrated in FIG.
The width W ₂ of the oxidation resistant film thus formed can be 0.1 μm or less, preferably about 0.05 μm.
Thus, the oxidation resistant film can act as an effective mask during the oxidation operation to prevent the oxidation of the underlying silicon, and along the sidewalls of the previously formed silicon film and silicon oxide film. Further, a film of any material can be used as long as it can be formed only in the region having the width W _{2 by} a suitable method and can be selectively and easily removed later.

When the base region of the lateral bipolar transistor is to be formed, as shown in FIG. 1C, after the oxidation resistant film and the pad oxide film thereunder are removed, the ion-implanted silicon region 11 is removed. An electrode for drawing out the base is formed on the top. This electrode can be easily formed, for example, by depositing polysilicon. More specifically, after the ion implantation, polysilicon is deposited on the entire surface by the CVD method and appropriate impurities such as boron are implanted to reduce the resistance, and then patterning is performed to remove unnecessary polysilicon. Except for this, a base extraction electrode can be formed.

After forming the base extraction electrode, a part of the silicon oxide film on the silicon film forming the emitter extraction electrode and a part of the silicon oxide film on the collector region are opened on the diffusion region, and these openings are formed. A lateral bipolar transistor can be completed by forming a metal on the portion and the base extraction electrode.

[0015]

In the method of the present invention, the oxidation resistant film formed through the silicon oxide film only in the regions along the sidewalls of the previously formed silicon film and silicon oxide film prevents oxidation of silicon thereunder. To oxidize the silicon in other regions, and its removal allows the exposure of unoxidized silicon regions of comparable width.
Since this oxidation resistant film can be formed by self-alignment without relying on photolithography, it exposes an unoxidized silicon region having a width sufficiently narrower than the width of the unoxidized silicon region formed by photolithography. . Then, by ion-implanting into this region, an ion-implanted region having a sufficiently narrow width equivalent to the width of the oxidation resistant film can be obtained.

The silicon oxide film formed prior to the formation of the oxidation resistant film only in the region along the sidewalls of the silicon film and the silicon oxide film formed in advance is exposed by the removal of the oxidation resistant film, and By being left as it is, the extraction electrode formed of the silicon film in contact with the diffusion region and the extraction electrode formed later on the ion implantation region are separated, and serve as an insulating layer that electrically insulates.

[0017]

The present invention will be further described with reference to the following examples.
In this example, the method of the present invention is applied to manufacture of an npn-lateral bipolar transistor. Figure 3 (a)
As shown in (3), element isolation was performed by oxidizing a portion of the SOI substrate other than the silicon element region. In this figure, 21 is silicon in the device region, and 22 and 23 are silicon oxide. The active layer in this element region was n-type, the carrier concentration was 1 × 10 ¹⁷ / cm ³ , and the film thickness was 0.15 μm. Arsenic-doped n-type polysilicon film (thickness: 200 nm) on the entire surface
Is deposited, and a silicon oxide film (thickness 200 nm) is further deposited on it.
Was deposited and patterned into a predetermined shape to form a silicon film 24 and a silicon oxide film 25 as shown in FIG. Then, the exposed silicon in the element region was thinly oxidized to form a pad oxide film 26 having a thickness of about 10 nm. Then, heating was performed at 1000 ° C. for 20 minutes to diffuse the dopant (arsenic) in the polysilicon film 24 into the underlying silicon to form a high-concentration n-type layer, that is, the emitter region 27.

A 100 nm-thickness silicon oxide film is deposited on the entire surface by the CVD method, and then this film is anisotropically removed only in the direction perpendicular to the substrate by reactive ion etching. 28), the silicon oxide film 28 is left only in the regions along the sidewalls of the silicon film 24 and the silicon oxide film 25. Next, a silicon nitride film having a thickness of 50 nm was deposited also by the CVD method, and this film was anisotropically etched by reactive ion etching to leave the silicon nitride film 29 beside the silicon oxide film. The width of the silicon oxide film 28 thus formed is 100 nm, and the width of the silicon nitride film 29 is 50 nm.
was nm.

Next, oxidation is performed, and as shown in FIG. 4 (a), the thickness of the pad oxide film is 10
An oxide film 30 of 0 nm was formed. Then, only the silicon nitride film 29 is selectively removed with hot phosphoric acid, and further the pad oxide film underneath is removed, so that the width of the silicon nitride film 29 is equal to 50 nm.
Exposed width of silicon. Using the remaining oxide film as a mask, boron was implanted into the exposed region of silicon at an acceleration energy of 25 keV at 1 × 10 ¹³ / cm ² to form a base 31 as shown in FIG. 4B.

Next, polysilicon is deposited to a thickness of 200 nm on the entire surface, and boron is accelerated to 1 × 10 ¹⁶ / cm at an acceleration energy of 30 keV.
^{2 was} injected to reduce the resistance, and patterning was performed to form an electrode 32 (FIG. 4C) for drawing out the base. Retaining the resist for patterning the base extraction electrode 32, phosphorus was implanted at 1 × 10 ¹⁶ / cm ² at an acceleration energy of 200 keV and annealed to lower the resistance of the collector region 33 (FIG. 4C). .

Finally, as shown in FIG. 4 (c), the silicon oxide film 25 on the silicon film 24 constituting the emitter extraction electrode and the silicon oxide film 30 in the collector region are opened, and these openings are formed. And metal on the base extraction electrode 32
34, 35 and 36 were formed to complete the npn-lateral bipolar transistor. In the lateral bipolar transistor thus manufactured, the distance between the n-type polysilicon emitter extraction electrode 24 and the base 31 is set to the silicon oxide film 28 left on the sidewalls of the silicon film and the silicon oxide film.
Of the silicon nitride film 29 removed, and the base width is equal to the width of the removed silicon nitride film 29 (about 50 nm in the above embodiment).

[0022]

As described above, according to the method of the present invention, the distance between the emitter extraction electrode and the base is made equal to the width of the silicon oxide film left on the sidewalls of the silicon film and the silicon oxide film. In addition, the base width can be made equal to the width of the removed oxidation resistant film. The widths of the silicon oxide film and the oxidation resistant film cannot be realized by the photolithography technique due to the limitation peculiar to this technique because these films can be formed by self-alignment without using the photolithography technique. Can be narrow enough. Therefore, according to the method of the present invention, the distance between the emitter extraction electrode and the base and the base width can be made sufficiently small, which is satisfactory for the lateral bipolar transistor. Can be realized.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the method of the present invention.

FIG. 2 is a diagram illustrating a method of forming a silicon oxide film formed only in a partial region on the pad oxide film along the sidewalls of the silicon film and the silicon oxide film.

FIG. 3 is a diagram illustrating the first half of the procedure of the embodiment.

FIG. 4 is a diagram illustrating the second half of the procedure of the embodiment.

FIG. 5 is a diagram exemplifying a distance between an emitter electrode and a base and a base width when formed by a photolithography technique.

[Explanation of symbols]

1 ... Silicon oxide substrate 2 ... Silicon 3 ... Silicon oxide film 4 ... Silicon film 5 ... Silicon oxide film 6 ... Pad oxide film 7 ... Sidewall silicon oxide film 8 ... Oxidation resistant film 9 ... Oxide film 10 ... diffusion area 11 ... Ion implantation area

Claims (3)

[Claims] 1. A part of exposed silicon (2) on a surface of a substrate which is element-isolated by silicon oxide (3),
A silicon film (4) doped with a dopant and a silicon oxide film (5) are sequentially stacked on a silicon oxide (3) adjacent to the silicon oxide (3) to form a predetermined shape, and the dopant in the silicon film is ground by heating. The previously formed silicon after diffusing into the silicon to form a diffusion region (10) and thinly oxidizing the remaining exposed silicon surface to form a pad oxide (6). The silicon oxide film (7) and the oxidation resistant film (8) are sequentially formed only on the region on the pad oxide film (6) along the side walls of the film (4) and the silicon oxide film (5), and the oxidation resistance is formed. Of the pad oxide film (6) is further oxidized by performing oxidation using the conductive film (8) as a mask, and only the oxidation resistant film (8) is selectively removed, and the pad below the oxidation resistant film (8) is selectively removed. Remove oxide film Exposing the silicon region having a width equal to the width of the oxidation resistant film (8), and in this region,
The method further comprises the step of ion-implanting while leaving the silicon oxide film (7) on the sidewalls of the silicon film (4) and the silicon oxide film (5) formed in advance to form an ion-implanted region (11). And a method for manufacturing a semiconductor device. 2. The method according to claim 1, wherein the oxidation resistant film (8) is a silicon nitride film or a silicon oxynitride film. 3. The method according to claim 1, wherein the diffusion region (10) is an emitter region of a lateral bipolar transistor and the ion implantation region (11) is a base region of a lateral bipolar transistor.