JPH0474380A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To improve the processing speed by inserting an address pointer, a comparing circuit, a control circuit, and an output control circuit into a data output circuit. CONSTITUTION:This circuit is provided with a comparing circuit 13 for inputting a write pointer signal for showing an address at the time of write and a read pointer signal for showing an address at the time of read and outputting a coincidence output signal only at the time of the same address, a control circuit 6 for inputting the coincidence output signal and a data input signal at the time of write and outputting a control output signal which becomes an output only at the time when an inversion signal of the data input signal at the time of this write and the coincidence output signal both exist, and an output control circuit 14 for inputting a control output signal inserted into a data line of an output circuit and turning off an outut from a memory cell 10 at the time when this control output signal exists. In such a way, a waiting time of a pre scribed time becomes unnecessary, and the processing speed can be increased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and particularly to a same address write/read detection circuit of a serial access memory.

[Conventional technology]

Conventional F I F O (First In First
0ut) memory is a serial access memory that has an input/output format of serial writing and serial reading, and writing and reading can be performed independently and asynchronously in different cycles.

FIG. 3 is a circuit diagram of a conventional example, and FIGS. 4 and 5 are timing diagrams explaining the operation of FIG. 3. If "H" data is written in the memory cell 10 of FIG. 3, and then the opposite "L" data is written, the transistor Q
Lead digit I by 4! By precharging 22, the correct output signal [)out will be output. However, if the transistor size of transistor Q4 is increased, the time until the correct signal Dout is outputted (a certain wait time is required) will be shortened, but the chip size will increase in proportion to the number of lead digit lines 22. . Furthermore, when the memory cell 10 is rewritten from "L" data to "H' data, the transistor Q
1, the correct signal Dout will be output in the time it takes to discharge the read digit line 22.

However, when compared with the precharge time of the transistor Q4, if these transistors Ql and Q4 have the same capability (same transistor size), the precharge time of the transistor Q4 takes longer. In other words, in order to read data written to an arbitrary address, a fixed (several cycles) wait time is required, as can be seen from the timing diagrams shown in FIGS.
-Time) is required.

[Problem to be solved by the invention]

The conventional circuit described above has a limitation in that a certain waiting time is required to read data written to an arbitrary address.

Information devices for image processing such as TVs, facsimiles, and copy machines are required to be faster.
If you try to write data to an arbitrary address and read that data at the same time, there is a drawback that data from the previous line may be output.

An object of the present invention is to eliminate such drawbacks, eliminate the need for a certain waiting time, and provide a semiconductor integrated circuit with increased processing speed.

[Means to solve the problem]

The structure of the present invention is a semiconductor integrated circuit consisting of a serial access memory that uses a dynamic memory cell that can perform writing and reading asynchronously and outputs data from this memory cell to a data line via an output circuit. a comparison circuit that inputs a write pointer signal indicating the address and a read pointer signal indicating the address at the time of reading and outputs a match output signal only when the address is the same, and inputs the match output signal and the data input signal at the time of the write. A control circuit that outputs a control output signal that is output only when the inverted signal of the data input signal at the time of writing and the coincidence output signal are both present, and a control circuit that is inserted into the data line of the output circuit and inputs the control output signal. The present invention is characterized by comprising an output control circuit that is controlled to turn off the output from the memory cell when this control output signal is present.

In the present invention, the output control circuit includes a first transistor having a gate connected to a control output signal, a source grounded, and a drain connected to an output data line, and a source connected to the drain of the first transistor to output the control output signal. It consists of a second transistor having a gate connected to an inverted signal and a drain connected to the output end of the output circuit.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a partial circuit diagram of one embodiment of the present invention, and FIG. 2 is a partial circuit diagram of an embodiment of the present invention.
9, which is a timing diagram of the figure, is a timing diagram of the present embodiment, in which an address pointer 11,
12, a comparison circuit 13, a control circuit (AND) 6, and an output control circuit 14 are inserted.

Assume that a signal having a timing as shown in FIG. 2 is applied to the circuit of this embodiment. However, write data is taken in at the rising edge after the cycle, and read data is defined at the rising edge after the cycle. This timing is such that data is written to an arbitrary address and read at the same time.

External clock signals are input to the write clock (WCK) and read clock (RCK) of the circuit shown in FIG. R1
~ Output as R3. These outputs are input to a comparison circuit 13, where the signals W1, R, , W2
and R2...W, and R, respectively, corresponding address signals are compared. If the comparison results match, it is determined that they are at the same address, and "H" data is output to the output A5 of the comparison circuit 13. The output A5 of this comparison circuit 13 and the inverted signal A4 in the inverter 4 of the write data input A3 are input to the AND circuit 6, and the write and read are at the same address, and the write data input is "L I + data". Only when the contact A6 is "A", the transistor Q6 is turned on, and data is output from the memory cell 10.

This contact A6 is connected to transistor Q5. It serves as an input to the output control circuit 14 consisting of Q6. If they are not at the same number, the contact A6 is "L", the transistor Q5 is turned off, the transistor Q6 is turned on, and data is output from the memory processor 10.

Light and league are in the same location, and light data input
When it becomes "L", contact A6 becomes "H", transistor Q5 turns on, transistor Q6 turns off, contact A7 becomes "L", and the data output becomes "L".
becomes.

〔Effect of the invention〕

As described above, the present invention has the advantage that when reading data written to an arbitrary address, the waiting time of a certain period of time, which was a limitation, is no longer necessary, and the processing speed can be increased.

[Brief explanation of drawings]

FIG. 1 is a partial circuit diagram of one embodiment of the present invention, and FIG. 2 is a partial circuit diagram of an embodiment of the present invention.
FIG. 3 is a partial circuit diagram of an example of a conventional serial access memory, and FIGS. 4 and 5 are waveform diagrams explaining the operation of FIG. 3. 1.3.4.5...Inverter, 2...Amplifier, 6
...AND circuit, 10...memory cell, 11...
Write address pointer, 12... Read address pointer, 13... Comparison circuit, 14... Output control circuit, Q1 to Q6... Transistor.

Claims (1)

[Claims] 1. In a semiconductor integrated circuit consisting of a serial access memory that uses a dynamic memory cell in which writing and reading can be performed asynchronously and outputting data from this memory cell to a data line via an output circuit, a comparator circuit that inputs a write pointer signal indicating an address and a read pointer signal indicating an address at the time of reading and outputs a match output signal only when the address is the same; a control circuit that outputs a control output signal that is output only when an inverted signal of the data input signal at the time of writing and the coincidence output signal; and a control circuit that is inserted into the data line of the output circuit and outputs the control output signal. and an output control circuit that is controlled to turn off the output from the memory cell when there is an input control output signal. 2. The output control circuit includes a first transistor whose gate is connected to the control output signal, whose source is grounded, and whose drain is connected to the output data line; 2. The semiconductor integrated circuit according to claim 1, comprising a second transistor having a gate connected to an inverted signal and a drain connected to an output terminal of said output circuit.